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Merge branch 'fix/32mb_120m_v6.0' into 'release/v6.0'

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fix(spi_flash): 1. Fix flash 120m in qio mode failed on esp32p4 (with 32M map enabled) 2. Add C61 32M flash support (backport v6.0)

See merge request espressif/esp-idf!46042
This commit is contained in:
morris
2026-03-23 16:14:19 +08:00
parent 9cdd5ebcee 52d5b1a173
commit ed6a7e267e
23 changed files with 296 additions and 22 deletions
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1
components/esp_hal_mspi/esp32c5/include/hal/spi_flash_ll.h
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@@ -37,6 +37,7 @@ extern "C" {
}\
dev_id; \
})
#define SPI_FLASH_LL_SUPPORT_WB_MODE_INDEPENDENT_CONTROL (1)
// Since ESP32-C5, WB_mode is available, we extend 8 bits to occupy `Continuous Read Mode` bits.
#define SPI_FLASH_LL_CONTINUOUS_MODE_BIT_NUMS (8)

3
components/esp_hal_mspi/esp32c61/include/hal/spi_flash_ll.h
View File

@@ -37,6 +37,7 @@ extern "C" {
}\
dev_id; \
})
#define SPI_FLASH_LL_SUPPORT_WB_MODE_INDEPENDENT_CONTROL (1)
// Since ESP32-C61, WB_mode is available, we extend 8 bits to occupy `Continuous Read Mode` bits.
#define SPI_FLASH_LL_CONTINUOUS_MODE_BIT_NUMS (8)
@@ -70,6 +71,7 @@ typedef union {
#define spi_flash_ll_set_hold(dev, hold_n) gpspi_flash_ll_set_hold((spi_dev_t*)dev, hold_n)
#define spi_flash_ll_set_cs_setup(dev, cs_setup_time) gpspi_flash_ll_set_cs_setup((spi_dev_t*)dev, cs_setup_time)
#define spi_flash_ll_set_extra_address(dev, extra_addr) { /* Not supported on gpspi on ESP32-C61*/ }
#define spi_flash_ll_wb_mode_enable(dev, wb_mode_enable) { /* Not supported on gpspi on ESP32-C61*/ }
#else
#define spi_flash_ll_reset(dev) spimem_flash_ll_reset((spi_mem_dev_t*)dev)
#define spi_flash_ll_cmd_is_done(dev) spimem_flash_ll_cmd_is_done((spi_mem_dev_t*)dev)
@@ -101,6 +103,7 @@ typedef union {
#define spi_flash_ll_sync_reset() spimem_flash_ll_sync_reset()
#define spi_flash_ll_set_common_command_register_info(dev, ctrl_reg, user_reg, user1_reg, user2_reg) spimem_flash_ll_set_common_command_register_info((spi_mem_dev_t*)dev, ctrl_reg, user_reg, user1_reg, user2_reg)
#define spi_flash_ll_get_common_command_register_info(dev, ctrl_reg, user_reg, user1_reg, user2_reg) spimem_flash_ll_get_common_command_register_info((spi_mem_dev_t*)dev, ctrl_reg, user_reg, user1_reg, user2_reg)
#define spi_flash_ll_wb_mode_enable(dev, wb_mode_enable) spimem_flash_ll_wb_mode_enable((spi_mem_dev_t*)dev, wb_mode_enable)
#endif

16
components/esp_hal_mspi/esp32c61/include/hal/spimem_flash_ll.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -557,6 +557,7 @@ static inline int spimem_flash_ll_get_addr_bitlen(spi_mem_dev_t *dev)
__attribute__((always_inline))
static inline void spimem_flash_ll_set_addr_bitlen(spi_mem_dev_t *dev, uint32_t bitlen)
{
dev->cache_fctrl.cache_usr_addr_4byte = (bitlen == 32) ? 1 : 0;
dev->user1.usr_addr_bitlen = (bitlen - 1);
dev->user.usr_addr = bitlen ? 1 : 0;
}
@@ -569,8 +570,19 @@ static inline void spimem_flash_ll_set_addr_bitlen(spi_mem_dev_t *dev, uint32_t
*/
static inline void spimem_flash_ll_set_extra_address(spi_mem_dev_t *dev, uint32_t extra_addr)
{
dev->cache_fctrl.cache_usr_addr_4byte = 0;
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->rd_status, wb_mode, extra_addr);
dev->rd_status.wb_mode_bitlen = 7; // 8 - 1
}
/**
* Enable extra address for bits M0-M7 in DIO/QIO mode.
*
* @param dev Beginning address of the peripheral registers.
* @param wb_mode_enable true for enabling wb_mode
*/
static inline void spimem_flash_ll_wb_mode_enable(spi_mem_dev_t *dev, bool wb_mode_enable)
{
dev->rd_status.wb_mode_en = wb_mode_enable;
}
/**

6
components/esp_hal_mspi/spi_flash_hal_common.inc
View File

@@ -127,11 +127,11 @@ esp_err_t spi_flash_hal_configure_host_io_mode(
if (conf_required) {
int line_width = (io_mode == SPI_FLASH_DIO ? 2 : 4);
dummy_cyclelen_base -= SPI_FLASH_LL_CONTINUOUS_MODE_BIT_NUMS / line_width;
#if !SOC_SPI_MEM_SUPPORT_WB_MODE_INDEPENDENT_CONTROL
#if !SPI_FLASH_LL_SUPPORT_WB_MODE_INDEPENDENT_CONTROL
addr_bitlen += SPI_FLASH_LL_CONTINUOUS_MODE_BIT_NUMS;
#endif
spi_flash_ll_set_extra_address(dev, 0);
#if SOC_SPI_MEM_SUPPORT_WB_MODE_INDEPENDENT_CONTROL
#if SPI_FLASH_LL_SUPPORT_WB_MODE_INDEPENDENT_CONTROL
spi_flash_ll_wb_mode_enable(dev, true);
#endif
}
@@ -227,7 +227,7 @@ esp_err_t spi_flash_hal_common_command(spi_flash_host_inst_t *host, spi_flash_tr
if (trans->miso_len > 0) {
spi_flash_ll_get_buffer_data(dev, trans->miso_data, trans->miso_len);
}
#if SOC_SPI_MEM_SUPPORT_WB_MODE_INDEPENDENT_CONTROL
#if SPI_FLASH_LL_SUPPORT_WB_MODE_INDEPENDENT_CONTROL
spi_flash_ll_wb_mode_enable(dev, false);
#endif
return ESP_OK;