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refactor(mcpwm): make mcpwm_hal independent & cleanup soc_caps

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This commit is contained in:
Chen Chen
2025-11-10 10:47:10 +08:00
parent 0978fc13ae
commit ed64a767ef
57 changed files with 1041 additions and 1216 deletions
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components/esp_hal_mcpwm/CMakeLists.txt
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idf_build_get_property(target IDF_TARGET)
if(${target} STREQUAL "linux")
return() # This component is not supported by the POSIX/Linux simulator
endif()
set(srcs)
set(includes "include")
set(target_folder "${target}")
if(EXISTS "${CMAKE_CURRENT_LIST_DIR}/${target}/include")
list(APPEND includes "${target}/include")
endif()
# MCPWM related source files
if(CONFIG_SOC_MCPWM_SUPPORTED)
list(APPEND srcs "mcpwm_hal.c" "${target_folder}/mcpwm_periph.c")
endif()
idf_component_register(SRCS ${srcs}
INCLUDE_DIRS ${includes}
REQUIRES soc hal)
components/esp_hal_mcpwm/README.md
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# ESP Hardware Abstraction Layer for MCPWM Peripheral
> [!NOTE]
> This component is currently in beta. Its API, behavior, and compatibility may change at any time and without notice; backward compatibility is not guaranteed. Use caution when integrating into production systems.
## Overview
The ESP Hardware Abstraction Layer for Motor Control PWM Peripherals (`esp_hal_mcpwm`) provides a unified interface to interact with MCPWM (Motor Control Pulse Width Modulation) peripherals across all ESP chip families. This component abstracts the hardware-specific details of different MCPWM implementations, enabling consistent usage patterns regardless of the underlying hardware.
The component supports comprehensive MCPWM functionality including:
- PWM signal generation with precise timing control
- Dead-time insertion for motor control applications
- Fault detection and protection mechanisms
- Capture functionality for feedback systems
- Synchronization between multiple MCPWM units
- Event-driven operation modes
components/esp_hal_mcpwm/esp32/include/hal/mcpwm_ll.h
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components/esp_hal_mcpwm/esp32/mcpwm_periph.c
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/*
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/soc.h"
#include "hal/mcpwm_ll.h"
#include "hal/mcpwm_periph.h"
#include "soc/gpio_sig_map.h"
const soc_mcpwm_signal_desc_t soc_mcpwm_signals[2] = {
{
.module_name = "MCPWM0",
.irq_id = ETS_PWM0_INTR_SOURCE,
.operators = {
[0] = {
.generators = {
[0] = {
.pwm_sig = PWM0_OUT0A_IDX
},
[1] = {
.pwm_sig = PWM0_OUT0B_IDX
}
}
},
[1] = {
.generators = {
[0] = {
.pwm_sig = PWM0_OUT1A_IDX
},
[1] = {
.pwm_sig = PWM0_OUT1B_IDX
}
}
},
[2] = {
.generators = {
[0] = {
.pwm_sig = PWM0_OUT2A_IDX
},
[1] = {
.pwm_sig = PWM0_OUT2B_IDX
}
}
}
},
.gpio_faults = {
[0] = {
.fault_sig = PWM0_F0_IN_IDX
},
[1] = {
.fault_sig = PWM0_F1_IN_IDX
},
[2] = {
.fault_sig = PWM0_F2_IN_IDX
}
},
.captures = {
[0] = {
.cap_sig = PWM0_CAP0_IN_IDX
},
[1] = {
.cap_sig = PWM0_CAP1_IN_IDX
},
[2] = {
.cap_sig = PWM0_CAP2_IN_IDX
}
},
.gpio_synchros = {
[0] = {
.sync_sig = PWM0_SYNC0_IN_IDX
},
[1] = {
.sync_sig = PWM0_SYNC1_IN_IDX
},
[2] = {
.sync_sig = PWM0_SYNC2_IN_IDX
}
}
},
{
.module_name = "MCPWM1",
.irq_id = ETS_PWM1_INTR_SOURCE,
.operators = {
[0] = {
.generators = {
[0] = {
.pwm_sig = PWM1_OUT0A_IDX
},
[1] = {
.pwm_sig = PWM1_OUT0B_IDX
}
}
},
[1] = {
.generators = {
[0] = {
.pwm_sig = PWM1_OUT1A_IDX
},
[1] = {
.pwm_sig = PWM1_OUT1B_IDX
}
}
},
[2] = {
.generators = {
[0] = {
.pwm_sig = PWM1_OUT2A_IDX
},
[1] = {
.pwm_sig = PWM1_OUT2B_IDX
}
}
}
},
.gpio_faults = {
[0] = {
.fault_sig = PWM1_F0_IN_IDX
},
[1] = {
.fault_sig = PWM1_F1_IN_IDX
},
[2] = {
.fault_sig = PWM1_F2_IN_IDX
}
},
.captures = {
[0] = {
.cap_sig = PWM1_CAP0_IN_IDX
},
[1] = {
.cap_sig = PWM1_CAP1_IN_IDX
},
[2] = {
.cap_sig = PWM1_CAP2_IN_IDX
}
},
.gpio_synchros = {
[0] = {
.sync_sig = PWM1_SYNC0_IN_IDX
},
[1] = {
.sync_sig = PWM1_SYNC1_IN_IDX
},
[2] = {
.sync_sig = PWM1_SYNC2_IN_IDX
}
}
}
};
components/esp_hal_mcpwm/esp32c5/include/hal/mcpwm_ll.h
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components/esp_hal_mcpwm/esp32c5/mcpwm_periph.c
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/*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/soc.h"
#include "hal/mcpwm_periph.h"
#include "soc/mcpwm_reg.h"
#include "soc/gpio_sig_map.h"
const soc_mcpwm_signal_desc_t soc_mcpwm_signals[1] = {
{
.module_name = "MCPWM0",
.irq_id = ETS_MCPWM0_INTR_SOURCE,
.operators = {
[0] = {
.generators = {
[0] = {
.pwm_sig = PWM0_OUT0A_IDX
},
[1] = {
.pwm_sig = PWM0_OUT0B_IDX
}
}
},
[1] = {
.generators = {
[0] = {
.pwm_sig = PWM0_OUT1A_IDX
},
[1] = {
.pwm_sig = PWM0_OUT1B_IDX
}
}
},
[2] = {
.generators = {
[0] = {
.pwm_sig = PWM0_OUT2A_IDX
},
[1] = {
.pwm_sig = PWM0_OUT2B_IDX
}
}
}
},
.gpio_faults = {
[0] = {
.fault_sig = PWM0_F0_IN_IDX
},
[1] = {
.fault_sig = PWM0_F1_IN_IDX
},
[2] = {
.fault_sig = PWM0_F2_IN_IDX
}
},
.captures = {
[0] = {
.cap_sig = PWM0_CAP0_IN_IDX
},
[1] = {
.cap_sig = PWM0_CAP1_IN_IDX
},
[2] = {
.cap_sig = PWM0_CAP2_IN_IDX
}
},
.gpio_synchros = {
[0] = {
.sync_sig = PWM0_SYNC0_IN_IDX
},
[1] = {
.sync_sig = PWM0_SYNC1_IN_IDX
},
[2] = {
.sync_sig = PWM0_SYNC2_IN_IDX
}
}
}
};
/**
* MCPWM Registers to be saved during sleep retention
* - Clk Configuration registers, e.g.: MCPWM_CLK_CFG_REG
* - Timer Configuration registers, e.g.: MCPWM_TIMER_SYNCI_CFG_REG, MCPWM_TIMER0_CFG0_REG, MCPWM_TIMER0_CFG1_REG, MCPWM_TIMER0_CFG1_REG
* - Operator Configuration registers, e.g.: MCPWM_OPERATOR_TIMERSEL_REG
* |- Generator Configuration registers, e.g.: MCPWM_GEN0_STMP_CFG_REG, MCPWM_GEN0_TSTMP_A_REG, MCPWM_GEN0_TSTMP_B_REG, MCPWM_GEN0_CFG0_REG, MCPWM_GEN0_FORCE_REG, MCPWM_GEN0_A_REG, MCPWM_GEN0_B_REG
* |- Dead Time Configuration registers, e.g.: MCPWM_DT0_CFG_REG, MCPWM_DT0_FED_CFG_REG, MCPWM_DT0_RED_CFG_REG
* |- Carrier Configuration registers, e.g.: MCPWM_CARRIER0_CFG_REG
* └- Fault Handle Configuration registers, e.g.: MCPWM_FAULT_DETECT_REG, MCPWM_FH0_CFG0_REG, MCPWM_FH0_CFG1_REG
* - Capture Timer Configuration registers, e.g.: MCPWM_CAP_TIMER_CFG_REG, MCPWM_CAP_TIMER_PHASE_REG, MCPWM_CAP_CH0_CFG_REG, MCPWM_CAP_CH1_CFG_REG, MCPWM_CAP_CH2_CFG_REG
* - Interrupt enable registers, e.g.: MCPWM_INT_ENA_REG
* - ETM Configurations, e.g.: MCPWM_EVT_EN_REG, MCPWM_EVT_EN2_REG, MCPWM_TASK_EN_REG, MCPWM_OP0_TSTMP_E1_REG, MCPWM_OP0_TSTMP_E2_REG, MCPWM_OP1_TSTMP_E1_REG, MCPWM_OP1_TSTMP_E2_REG, MCPWM_OP2_TSTMP_E1_REG, MCPWM_OP2_TSTMP_E2_REG
* - Misc Configurations, e.g.: MCPWM_UPDATE_CFG_REG
*/
#define MCPWM_RETENTION_REGS_CNT 68
#define MCPWM_RETENTION_REGS_BASE (DR_REG_MCPWM_BASE + 0x0)
static const uint32_t mcpwm_regs_map[4] = {0xefffeeef, 0x7efffbff, 0x1ff18, 0x0};
static const regdma_entries_config_t mcpwm_regs_retention[] = {
// backup stage: save configuration registers
// restore stage: restore the configuration registers
[0] = {
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_MCPWM_LINK(0x00),
MCPWM_RETENTION_REGS_BASE, MCPWM_RETENTION_REGS_BASE,
MCPWM_RETENTION_REGS_CNT, 0, 0,
mcpwm_regs_map[0], mcpwm_regs_map[1],
mcpwm_regs_map[2], mcpwm_regs_map[3]),
.owner = ENTRY(0) | ENTRY(2)
},
// restore stage: trigger a forced update of all active registers
[1] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x01),
MCPWM_UPDATE_CFG_REG(0), MCPWM_GLOBAL_FORCE_UP, MCPWM_GLOBAL_FORCE_UP_M, 1, 0),
.owner = ENTRY(0) | ENTRY(2)
},
[2] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x02),
MCPWM_UPDATE_CFG_REG(0), 0, MCPWM_GLOBAL_FORCE_UP_M, 1, 0),
.owner = ENTRY(0) | ENTRY(2)
},
};
const mcpwm_reg_retention_info_t mcpwm_reg_retention_info[1] = {
[0] = {
.regdma_entry_array = mcpwm_regs_retention,
.array_size = ARRAY_SIZE(mcpwm_regs_retention),
.retention_module = SLEEP_RETENTION_MODULE_MCPWM0
},
};
components/esp_hal_mcpwm/esp32c6/include/hal/mcpwm_ll.h
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components/esp_hal_mcpwm/esp32c6/mcpwm_periph.c
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/*
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/soc.h"
#include "hal/mcpwm_periph.h"
#include "soc/mcpwm_reg.h"
#include "soc/gpio_sig_map.h"
const soc_mcpwm_signal_desc_t soc_mcpwm_signals[1] = {
{
.module_name = "MCPWM0",
.irq_id = ETS_MCPWM0_INTR_SOURCE,
.operators = {
[0] = {
.generators = {
[0] = {
.pwm_sig = PWM0_OUT0A_IDX
},
[1] = {
.pwm_sig = PWM0_OUT0B_IDX
}
}
},
[1] = {
.generators = {
[0] = {
.pwm_sig = PWM0_OUT1A_IDX
},
[1] = {
.pwm_sig = PWM0_OUT1B_IDX
}
}
},
[2] = {
.generators = {
[0] = {
.pwm_sig = PWM0_OUT2A_IDX
},
[1] = {
.pwm_sig = PWM0_OUT2B_IDX
}
}
}
},
.gpio_faults = {
[0] = {
.fault_sig = PWM0_F0_IN_IDX
},
[1] = {
.fault_sig = PWM0_F1_IN_IDX
},
[2] = {
.fault_sig = PWM0_F2_IN_IDX
}
},
.captures = {
[0] = {
.cap_sig = PWM0_CAP0_IN_IDX
},
[1] = {
.cap_sig = PWM0_CAP1_IN_IDX
},
[2] = {
.cap_sig = PWM0_CAP2_IN_IDX
}
},
.gpio_synchros = {
[0] = {
.sync_sig = PWM0_SYNC0_IN_IDX
},
[1] = {
.sync_sig = PWM0_SYNC1_IN_IDX
},
[2] = {
.sync_sig = PWM0_SYNC2_IN_IDX
}
}
}
};
/**
* MCPWM Registers to be saved during sleep retention
* - Clk Configuration registers, e.g.: MCPWM_CLK_CFG_REG
* - Timer Configuration registers, e.g.: MCPWM_TIMER_SYNCI_CFG_REG, MCPWM_TIMER0_CFG0_REG, MCPWM_TIMER0_CFG1_REG, MCPWM_TIMER0_CFG1_REG
* - Operator Configuration registers, e.g.: MCPWM_OPERATOR_TIMERSEL_REG
* |- Generator Configuration registers, e.g.: MCPWM_GEN0_STMP_CFG_REG, MCPWM_GEN0_TSTMP_A_REG, MCPWM_GEN0_TSTMP_B_REG, MCPWM_GEN0_CFG0_REG, MCPWM_GEN0_FORCE_REG, MCPWM_GEN0_A_REG, MCPWM_GEN0_B_REG
* |- Dead Time Configuration registers, e.g.: MCPWM_DT0_CFG_REG, MCPWM_DT0_FED_CFG_REG, MCPWM_DT0_RED_CFG_REG
* |- Carrier Configuration registers, e.g.: MCPWM_CARRIER0_CFG_REG
* └- Fault Handle Configuration registers, e.g.: MCPWM_FAULT_DETECT_REG, MCPWM_FH0_CFG0_REG, MCPWM_FH0_CFG1_REG
* - Capture Timer Configuration registers, e.g.: MCPWM_CAP_TIMER_CFG_REG, MCPWM_CAP_TIMER_PHASE_REG, MCPWM_CAP_CH0_CFG_REG, MCPWM_CAP_CH1_CFG_REG, MCPWM_CAP_CH2_CFG_REG
* - Interrupt enable registers, e.g.: MCPWM_INT_ENA_REG
* - ETM Configurations, e.g.: MCPWM_EVT_EN_REG, MCPWM_TASK_EN_REG
* - Misc Configurations, e.g.: MCPWM_UPDATE_CFG_REG
*/
#define MCPWM_RETENTION_REGS_CNT 61
#define MCPWM_RETENTION_REGS_BASE (DR_REG_MCPWM_BASE + 0x0)
static const uint32_t mcpwm_regs_map[4] = {0xefffeeef, 0x7efffbff, 0x318, 0x0};
static const regdma_entries_config_t mcpwm_regs_retention[] = {
// backup stage: save configuration registers
// restore stage: restore the configuration registers
[0] = {
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_MCPWM_LINK(0x00),
MCPWM_RETENTION_REGS_BASE, MCPWM_RETENTION_REGS_BASE,
MCPWM_RETENTION_REGS_CNT, 0, 0,
mcpwm_regs_map[0], mcpwm_regs_map[1],
mcpwm_regs_map[2], mcpwm_regs_map[3]),
.owner = ENTRY(0) | ENTRY(2)
},
// restore stage: trigger a forced update of all active registers
[1] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x01),
MCPWM_UPDATE_CFG_REG(0), MCPWM_GLOBAL_FORCE_UP, MCPWM_GLOBAL_FORCE_UP_M, 1, 0),
.owner = ENTRY(0) | ENTRY(2)
},
[2] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x02),
MCPWM_UPDATE_CFG_REG(0), 0, MCPWM_GLOBAL_FORCE_UP_M, 1, 0),
.owner = ENTRY(0) | ENTRY(2)
},
};
const mcpwm_reg_retention_info_t mcpwm_reg_retention_info[1] = {
[0] = {
.regdma_entry_array = mcpwm_regs_retention,
.array_size = ARRAY_SIZE(mcpwm_regs_retention),
.retention_module = SLEEP_RETENTION_MODULE_MCPWM0
},
};
components/esp_hal_mcpwm/esp32h2/include/hal/mcpwm_ll.h
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components/esp_hal_mcpwm/esp32h2/mcpwm_periph.c
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/*
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/soc.h"
#include "hal/mcpwm_periph.h"
#include "soc/mcpwm_reg.h"
#include "soc/gpio_sig_map.h"
const soc_mcpwm_signal_desc_t soc_mcpwm_signals[1] = {
{
.module_name = "MCPWM0",
.irq_id = ETS_MCPWM0_INTR_SOURCE,
.operators = {
[0] = {
.generators = {
[0] = {
.pwm_sig = PWM0_OUT0A_IDX
},
[1] = {
.pwm_sig = PWM0_OUT0B_IDX
}
}
},
[1] = {
.generators = {
[0] = {
.pwm_sig = PWM0_OUT1A_IDX
},
[1] = {
.pwm_sig = PWM0_OUT1B_IDX
}
}
},
[2] = {
.generators = {
[0] = {
.pwm_sig = PWM0_OUT2A_IDX
},
[1] = {
.pwm_sig = PWM0_OUT2B_IDX
}
}
}
},
.gpio_faults = {
[0] = {
.fault_sig = PWM0_F0_IN_IDX
},
[1] = {
.fault_sig = PWM0_F1_IN_IDX
},
[2] = {
.fault_sig = PWM0_F2_IN_IDX
}
},
.captures = {
[0] = {
.cap_sig = PWM0_CAP0_IN_IDX
},
[1] = {
.cap_sig = PWM0_CAP1_IN_IDX
},
[2] = {
.cap_sig = PWM0_CAP2_IN_IDX
}
},
.gpio_synchros = {
[0] = {
.sync_sig = PWM0_SYNC0_IN_IDX
},
[1] = {
.sync_sig = PWM0_SYNC1_IN_IDX
},
[2] = {
.sync_sig = PWM0_SYNC2_IN_IDX
}
}
}
};
/**
* MCPWM Registers to be saved during sleep retention
* - Clk Configuration registers, e.g.: MCPWM_CLK_CFG_REG
* - Timer Configuration registers, e.g.: MCPWM_TIMER_SYNCI_CFG_REG, MCPWM_TIMER0_CFG0_REG, MCPWM_TIMER0_CFG1_REG, MCPWM_TIMER0_CFG1_REG
* - Operator Configuration registers, e.g.: MCPWM_OPERATOR_TIMERSEL_REG
* |- Generator Configuration registers, e.g.: MCPWM_GEN0_STMP_CFG_REG, MCPWM_GEN0_TSTMP_A_REG, MCPWM_GEN0_TSTMP_B_REG, MCPWM_GEN0_CFG0_REG, MCPWM_GEN0_FORCE_REG, MCPWM_GEN0_A_REG, MCPWM_GEN0_B_REG
* |- Dead Time Configuration registers, e.g.: MCPWM_DT0_CFG_REG, MCPWM_DT0_FED_CFG_REG, MCPWM_DT0_RED_CFG_REG
* |- Carrier Configuration registers, e.g.: MCPWM_CARRIER0_CFG_REG
* └- Fault Handle Configuration registers, e.g.: MCPWM_FAULT_DETECT_REG, MCPWM_FH0_CFG0_REG, MCPWM_FH0_CFG1_REG
* - Capture Timer Configuration registers, e.g.: MCPWM_CAP_TIMER_CFG_REG, MCPWM_CAP_TIMER_PHASE_REG, MCPWM_CAP_CH0_CFG_REG, MCPWM_CAP_CH1_CFG_REG, MCPWM_CAP_CH2_CFG_REG
* - Interrupt enable registers, e.g.: MCPWM_INT_ENA_REG
* - ETM Configurations, e.g.: MCPWM_EVT_EN_REG, MCPWM_TASK_EN_REG
* - Misc Configurations, e.g.: MCPWM_UPDATE_CFG_REG
*/
#define MCPWM_RETENTION_REGS_CNT 61
#define MCPWM_RETENTION_REGS_BASE (DR_REG_MCPWM_BASE + 0x0)
static const uint32_t mcpwm_regs_map[4] = {0xefffeeef, 0x7efffbff, 0x318, 0x0};
static const regdma_entries_config_t mcpwm_regs_retention[] = {
// backup stage: save configuration registers
// restore stage: restore the configuration registers
[0] = {
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_MCPWM_LINK(0x00),
MCPWM_RETENTION_REGS_BASE, MCPWM_RETENTION_REGS_BASE,
MCPWM_RETENTION_REGS_CNT, 0, 0,
mcpwm_regs_map[0], mcpwm_regs_map[1],
mcpwm_regs_map[2], mcpwm_regs_map[3]),
.owner = ENTRY(0) | ENTRY(2)
},
// restore stage: trigger a forced update of all active registers
[1] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x01),
MCPWM_UPDATE_CFG_REG, MCPWM_GLOBAL_FORCE_UP, MCPWM_GLOBAL_FORCE_UP_M, 1, 0),
.owner = ENTRY(0) | ENTRY(2)
},
[2] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x02),
MCPWM_UPDATE_CFG_REG, 0, MCPWM_GLOBAL_FORCE_UP_M, 1, 0),
.owner = ENTRY(0) | ENTRY(2)
},
};
const mcpwm_reg_retention_info_t mcpwm_reg_retention_info[1] = {
[0] = {
.regdma_entry_array = mcpwm_regs_retention,
.array_size = ARRAY_SIZE(mcpwm_regs_retention),
.retention_module = SLEEP_RETENTION_MODULE_MCPWM0
},
};
components/esp_hal_mcpwm/esp32p4/include/hal/mcpwm_ll.h
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components/esp_hal_mcpwm/esp32p4/mcpwm_periph.c
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/*
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/soc.h"
#include "hal/mcpwm_periph.h"
#include "soc/mcpwm_reg.h"
#include "soc/gpio_sig_map.h"
const soc_mcpwm_signal_desc_t soc_mcpwm_signals[2] = {
{
.module_name = "MCPWM0",
.irq_id = ETS_PWM0_INTR_SOURCE,
.operators = {
[0] = {
.generators = {
[0] = {
.pwm_sig = PWM0_CH0_A_PAD_OUT_IDX
},
[1] = {
.pwm_sig = PWM0_CH0_B_PAD_OUT_IDX
}
}
},
[1] = {
.generators = {
[0] = {
.pwm_sig = PWM0_CH1_A_PAD_OUT_IDX
},
[1] = {
.pwm_sig = PWM0_CH1_B_PAD_OUT_IDX
}
}
},
[2] = {
.generators = {
[0] = {
.pwm_sig = PWM0_CH2_A_PAD_OUT_IDX
},
[1] = {
.pwm_sig = PWM0_CH2_B_PAD_OUT_IDX
}
}
}
},
.gpio_faults = {
[0] = {
.fault_sig = PWM0_F0_PAD_IN_IDX
},
[1] = {
.fault_sig = PWM0_F1_PAD_IN_IDX
},
[2] = {
.fault_sig = PWM0_F2_PAD_IN_IDX
}
},
.captures = {
[0] = {
.cap_sig = PWM0_CAP0_PAD_IN_IDX
},
[1] = {
.cap_sig = PWM0_CAP1_PAD_IN_IDX
},
[2] = {
.cap_sig = PWM0_CAP2_PAD_IN_IDX
}
},
.gpio_synchros = {
[0] = {
.sync_sig = PWM0_SYNC0_PAD_IN_IDX
},
[1] = {
.sync_sig = PWM0_SYNC1_PAD_IN_IDX
},
[2] = {
.sync_sig = PWM0_SYNC2_PAD_IN_IDX
}
}
},
{
.module_name = "MCPWM1",
.irq_id = ETS_PWM1_INTR_SOURCE,
.operators = {
[0] = {
.generators = {
[0] = {
.pwm_sig = PWM1_CH0_A_PAD_OUT_IDX
},
[1] = {
.pwm_sig = PWM1_CH0_B_PAD_OUT_IDX
}
}
},
[1] = {
.generators = {
[0] = {
.pwm_sig = PWM1_CH1_A_PAD_OUT_IDX
},
[1] = {
.pwm_sig = PWM1_CH1_B_PAD_OUT_IDX
}
}
},
[2] = {
.generators = {
[0] = {
.pwm_sig = PWM1_CH2_A_PAD_OUT_IDX
},
[1] = {
.pwm_sig = PWM1_CH2_B_PAD_OUT_IDX
}
}
}
},
.gpio_faults = {
[0] = {
.fault_sig = PWM1_F0_PAD_IN_IDX
},
[1] = {
.fault_sig = PWM1_F1_PAD_IN_IDX
},
[2] = {
.fault_sig = PWM1_F2_PAD_IN_IDX
}
},
.captures = {
[0] = {
.cap_sig = PWM1_CAP0_PAD_IN_IDX
},
[1] = {
.cap_sig = PWM1_CAP1_PAD_IN_IDX
},
[2] = {
.cap_sig = PWM1_CAP2_PAD_IN_IDX
}
},
.gpio_synchros = {
[0] = {
.sync_sig = PWM1_SYNC0_PAD_IN_IDX
},
[1] = {
.sync_sig = PWM1_SYNC1_PAD_IN_IDX
},
[2] = {
.sync_sig = PWM1_SYNC2_PAD_IN_IDX
}
}
}
};
#if SOC_MCPWM_SUPPORT_SLEEP_RETENTION
/**
* MCPWM Registers to be saved during sleep retention
* - Clk Configuration registers, e.g.: MCPWM_CLK_CFG_REG
* - Timer Configuration registers, e.g.: MCPWM_TIMER_SYNCI_CFG_REG, MCPWM_TIMER0_CFG0_REG, MCPWM_TIMER0_CFG1_REG, MCPWM_TIMER0_CFG1_REG
* - Operator Configuration registers, e.g.: MCPWM_OPERATOR_TIMERSEL_REG
* |- Generator Configuration registers, e.g.: MCPWM_GEN0_STMP_CFG_REG, MCPWM_GEN0_TSTMP_A_REG, MCPWM_GEN0_TSTMP_B_REG, MCPWM_GEN0_CFG0_REG, MCPWM_GEN0_FORCE_REG, MCPWM_GEN0_A_REG, MCPWM_GEN0_B_REG
* |- Dead Time Configuration registers, e.g.: MCPWM_DT0_CFG_REG, MCPWM_DT0_FED_CFG_REG, MCPWM_DT0_RED_CFG_REG
* |- Carrier Configuration registers, e.g.: MCPWM_CARRIER0_CFG_REG
* └- Fault Handle Configuration registers, e.g.: MCPWM_FAULT_DETECT_REG, MCPWM_FH0_CFG0_REG, MCPWM_FH0_CFG1_REG
* - Capture Timer Configuration registers, e.g.: MCPWM_CAP_TIMER_CFG_REG, MCPWM_CAP_TIMER_PHASE_REG, MCPWM_CAP_CH0_CFG_REG, MCPWM_CAP_CH1_CFG_REG, MCPWM_CAP_CH2_CFG_REG
* - Interrupt enable registers, e.g.: MCPWM_INT_ENA_REG
* - ETM Configurations, e.g.: MCPWM_EVT_EN_REG, MCPWM_TASK_EN_REG
* - Misc Configurations, e.g.: MCPWM_UPDATE_CFG_REG
*/
#define MCPWM_RETENTION_REGS_CNT 68
#define MCPWM_RETENTION_REGS_BASE(i) REG_MCPWM_BASE(i)
static const uint32_t mcpwm_regs_map[4] = {0xefffeeef, 0x7efffbff, 0x1ff18, 0x0};
#define MCPWM_SLEEP_RETENTION_ENTRIES(mcpwm_port) { \
/* backup stage: save configuration registers \
restore stage: restore the configuration registers */ \
[0] = { .config = REGDMA_LINK_ADDR_MAP_INIT( \
REGDMA_MCPWM_LINK(0x00), \
MCPWM_RETENTION_REGS_BASE(mcpwm_port), \
MCPWM_RETENTION_REGS_BASE(mcpwm_port), \
MCPWM_RETENTION_REGS_CNT, 0, 0, \
mcpwm_regs_map[0], mcpwm_regs_map[1], \
mcpwm_regs_map[2], mcpwm_regs_map[3]), \
.owner = ENTRY(0)}, \
/* restore stage: trigger a forced update of all active registers*/ \
[1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x01), \
MCPWM_UPDATE_CFG_REG(mcpwm_port), MCPWM_GLOBAL_FORCE_UP, MCPWM_GLOBAL_FORCE_UP_M, 1, 0), \
.owner = ENTRY(0) }, \
[2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x02), \
MCPWM_UPDATE_CFG_REG(mcpwm_port), 0, MCPWM_GLOBAL_FORCE_UP_M, 1, 0), \
.owner = ENTRY(0) }, \
};
static const regdma_entries_config_t mcpwm0_regs_retention[] = MCPWM_SLEEP_RETENTION_ENTRIES(0);
static const regdma_entries_config_t mcpwm1_regs_retention[] = MCPWM_SLEEP_RETENTION_ENTRIES(1);
const mcpwm_reg_retention_info_t mcpwm_reg_retention_info[2] = {
[0] = {
.regdma_entry_array = mcpwm0_regs_retention,
.array_size = ARRAY_SIZE(mcpwm0_regs_retention),
.retention_module = SLEEP_RETENTION_MODULE_MCPWM0
},
[1] = {
.regdma_entry_array = mcpwm1_regs_retention,
.array_size = ARRAY_SIZE(mcpwm1_regs_retention),
.retention_module = SLEEP_RETENTION_MODULE_MCPWM1
},
};
#endif //SOC_MCPWM_SUPPORT_SLEEP_RETENTION
components/esp_hal_mcpwm/esp32s3/include/hal/mcpwm_ll.h
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components/esp_hal_mcpwm/esp32s3/mcpwm_periph.c
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/*
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/soc.h"
#include "hal/mcpwm_periph.h"
#include "soc/gpio_sig_map.h"
const soc_mcpwm_signal_desc_t soc_mcpwm_signals[2] = {
{
.module_name = "MCPWM0",
.irq_id = ETS_PWM0_INTR_SOURCE,
.operators = {
[0] = {
.generators = {
[0] = {
.pwm_sig = PWM0_OUT0A_IDX
},
[1] = {
.pwm_sig = PWM0_OUT0B_IDX
}
}
},
[1] = {
.generators = {
[0] = {
.pwm_sig = PWM0_OUT1A_IDX
},
[1] = {
.pwm_sig = PWM0_OUT1B_IDX
}
}
},
[2] = {
.generators = {
[0] = {
.pwm_sig = PWM0_OUT2A_IDX
},
[1] = {
.pwm_sig = PWM0_OUT2B_IDX
}
}
}
},
.gpio_faults = {
[0] = {
.fault_sig = PWM0_F0_IN_IDX
},
[1] = {
.fault_sig = PWM0_F1_IN_IDX
},
[2] = {
.fault_sig = PWM0_F2_IN_IDX
}
},
.captures = {
[0] = {
.cap_sig = PWM0_CAP0_IN_IDX
},
[1] = {
.cap_sig = PWM0_CAP1_IN_IDX
},
[2] = {
.cap_sig = PWM0_CAP2_IN_IDX
}
},
.gpio_synchros = {
[0] = {
.sync_sig = PWM0_SYNC0_IN_IDX
},
[1] = {
.sync_sig = PWM0_SYNC1_IN_IDX
},
[2] = {
.sync_sig = PWM0_SYNC2_IN_IDX
}
}
},
{
.module_name = "MCPWM1",
.irq_id = ETS_PWM1_INTR_SOURCE,
.operators = {
[0] = {
.generators = {
[0] = {
.pwm_sig = PWM1_OUT0A_IDX
},
[1] = {
.pwm_sig = PWM1_OUT0B_IDX
}
}
},
[1] = {
.generators = {
[0] = {
.pwm_sig = PWM1_OUT1A_IDX
},
[1] = {
.pwm_sig = PWM1_OUT1B_IDX
}
}
},
[2] = {
.generators = {
[0] = {
.pwm_sig = PWM1_OUT2A_IDX
},
[1] = {
.pwm_sig = PWM1_OUT2B_IDX
}
}
}
},
.gpio_faults = {
[0] = {
.fault_sig = PWM1_F0_IN_IDX
},
[1] = {
.fault_sig = PWM1_F1_IN_IDX
},
[2] = {
.fault_sig = PWM1_F2_IN_IDX
}
},
.captures = {
[0] = {
.cap_sig = PWM1_CAP0_IN_IDX
},
[1] = {
.cap_sig = PWM1_CAP1_IN_IDX
},
[2] = {
.cap_sig = PWM1_CAP2_IN_IDX
}
},
.gpio_synchros = {
[0] = {
.sync_sig = PWM1_SYNC0_IN_IDX
},
[1] = {
.sync_sig = PWM1_SYNC1_IN_IDX
},
[2] = {
.sync_sig = PWM1_SYNC2_IN_IDX
}
}
}
};
components/esp_hal_mcpwm/include/hal/mcpwm_hal.h
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/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use in application code.
* See readme.md in hal/include/hal/readme.md
******************************************************************************/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef struct mcpwm_dev_t *mcpwm_soc_handle_t; // MCPWM SOC layer handle
/**
* @brief HAL layer configuration
*/
typedef struct {
int group_id; // Indicate the MCPWM hardware group
} mcpwm_hal_init_config_t;
/**
* Context that should be maintained by both the driver and the HAL
*/
typedef struct {
mcpwm_soc_handle_t dev; // MCPWM SOC layer handle
} mcpwm_hal_context_t;
/**
* @brief Initialize the internal state of the HAL.
*
* @param hal Context of the HAL layer.
* @param init_config Configuration for the HAL to be used only once.
*/
void mcpwm_hal_init(mcpwm_hal_context_t *hal, const mcpwm_hal_init_config_t *init_config);
/**
* @brief Deinitialize the HAL driver.
*
* @param hal Context of the HAL layer.
*/
void mcpwm_hal_deinit(mcpwm_hal_context_t *hal);
/**
* @brief Reset MCPWM timer
*
* @param hal Context of the HAL layer.
* @param timer_id Timer ID
*/
void mcpwm_hal_timer_reset(mcpwm_hal_context_t *hal, int timer_id);
/**
* @brief Reset MCPWM operator
*
* @param hal Context of the HAL layer.
* @param oper_id Operator ID
*/
void mcpwm_hal_operator_reset(mcpwm_hal_context_t *hal, int oper_id);
/**
* @brief Reset MCPWM generator
*
* @param hal Context of the HAL layer.
* @param oper_id Operator ID
* @param gen_id Generator ID
*/
void mcpwm_hal_generator_reset(mcpwm_hal_context_t *hal, int oper_id, int gen_id);
#ifdef __cplusplus
}
#endif
components/esp_hal_mcpwm/include/hal/mcpwm_periph.h
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/*
* SPDX-FileCopyrightText: 2019-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc_caps.h"
#include "soc/periph_defs.h"
#include "soc/regdma.h"
#if SOC_HAS(MCPWM)
#include "hal/mcpwm_ll.h"
#endif
#if SOC_MCPWM_SUPPORT_SLEEP_RETENTION
#include "soc/retention_periph_defs.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_HAS(MCPWM)
typedef struct {
const char *module_name;
const int irq_id;
struct {
struct {
const uint32_t pwm_sig;
} generators[MCPWM_LL_GET(GENERATORS_PER_OPERATOR)];
} operators[MCPWM_LL_GET(OPERATORS_PER_GROUP)];
struct {
const uint32_t fault_sig;
} gpio_faults[MCPWM_LL_GET(GPIO_FAULTS_PER_GROUP)];
struct {
const uint32_t cap_sig;
} captures[MCPWM_LL_GET(CAPTURE_CHANNELS_PER_TIMER)];
struct {
const uint32_t sync_sig;
} gpio_synchros[MCPWM_LL_GET(GPIO_SYNCHROS_PER_GROUP)];
} soc_mcpwm_signal_desc_t;
extern const soc_mcpwm_signal_desc_t soc_mcpwm_signals[MCPWM_LL_GET(GROUP_NUM)];
#if SOC_MCPWM_SUPPORT_SLEEP_RETENTION
typedef struct {
const regdma_entries_config_t *regdma_entry_array;
uint32_t array_size;
const periph_retention_module_t retention_module;
} mcpwm_reg_retention_info_t;
extern const mcpwm_reg_retention_info_t mcpwm_reg_retention_info[MCPWM_LL_GET(GROUP_NUM)];
#endif // SOC_MCPWM_SUPPORT_SLEEP_RETENTION
#endif // SOC_HAS(MCPWM)
#ifdef __cplusplus
}
#endif
components/esp_hal_mcpwm/mcpwm_hal.c
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/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdlib.h>
#include "soc/soc_caps.h"
#include "hal/mcpwm_hal.h"
#include "hal/mcpwm_ll.h"
void mcpwm_hal_init(mcpwm_hal_context_t *hal, const mcpwm_hal_init_config_t *init_config)
{
hal->dev = MCPWM_LL_GET_HW(init_config->group_id);
mcpwm_ll_group_enable_shadow_mode(hal->dev);
mcpwm_ll_group_flush_shadow(hal->dev);
}
void mcpwm_hal_deinit(mcpwm_hal_context_t *hal)
{
hal->dev = NULL;
}
void mcpwm_hal_timer_reset(mcpwm_hal_context_t *hal, int timer_id)
{
mcpwm_ll_timer_set_count_mode(hal->dev, timer_id, MCPWM_TIMER_COUNT_MODE_PAUSE);
mcpwm_ll_timer_update_period_at_once(hal->dev, timer_id);
// disable sync input and output by default
mcpwm_ll_timer_disable_sync_out(hal->dev, timer_id);
mcpwm_ll_timer_enable_sync_input(hal->dev, timer_id, false);
mcpwm_ll_timer_clear_sync_input(hal->dev, timer_id);
}
void mcpwm_hal_operator_reset(mcpwm_hal_context_t *hal, int oper_id)
{
// allow to update action, compare, and dead time configuration
mcpwm_ll_operator_stop_update_action(hal->dev, oper_id, false);
mcpwm_ll_operator_update_action_at_once(hal->dev, oper_id);
mcpwm_ll_deadtime_stop_update_delay(hal->dev, oper_id, false);
mcpwm_ll_deadtime_update_delay_at_once(hal->dev, oper_id);
for (int i = 0; i < MCPWM_LL_GET(COMPARATORS_PER_OPERATOR); i++) {
mcpwm_ll_operator_stop_update_compare(hal->dev, oper_id, i, false);
mcpwm_ll_operator_update_compare_at_once(hal->dev, oper_id, i);
}
mcpwm_ll_brake_enable_cbc_refresh_on_tez(hal->dev, oper_id, false);
mcpwm_ll_fault_enable_cbc_refresh_on_tep(hal->dev, oper_id, false);
mcpwm_ll_brake_enable_soft_cbc(hal->dev, oper_id, false);
mcpwm_ll_brake_enable_soft_ost(hal->dev, oper_id, false);
}
void mcpwm_hal_generator_reset(mcpwm_hal_context_t *hal, int oper_id, int gen_id)
{
mcpwm_ll_generator_reset_actions(hal->dev, oper_id, gen_id);
mcpwm_ll_gen_disable_continue_force_action(hal->dev, oper_id, gen_id);
mcpwm_ll_gen_disable_noncontinue_force_action(hal->dev, oper_id, gen_id);
}