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refactor(i2s): rename the confusing port number

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This commit is contained in:
laokaiyao
2024-10-23 18:16:57 +08:00
parent 96632b7b02
commit ecb52d3af3
36 changed files with 119 additions and 173 deletions
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components/soc/esp32c3/i2s_periph.c
+1 -1
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@@ -29,6 +29,6 @@ const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_NUM] = {
.data_out_sigs[1] = I2SO_SD1_OUT_IDX,
.data_in_sig = I2SI_SD_IN_IDX,
.irq = ETS_I2S1_INTR_SOURCE,
.irq = ETS_I2S0_INTR_SOURCE,
}
};
components/soc/esp32c3/include/soc/interrupts.h
+2 -2
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@@ -35,7 +35,7 @@ typedef enum {
ETS_GPIO_NMI_SOURCE, /**< interrupt of GPIO, NMI*/
ETS_SPI1_INTR_SOURCE, /**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/
ETS_SPI2_INTR_SOURCE, /**< interrupt of SPI2, level*/
ETS_I2S1_INTR_SOURCE, /**< interrupt of I2S1, level*/
ETS_I2S0_INTR_SOURCE, /**< interrupt of I2S0, level*/
ETS_UART0_INTR_SOURCE, /**< interrupt of UART0, level*/
ETS_UART1_INTR_SOURCE, /**< interrupt of UART1, level*/
ETS_LEDC_INTR_SOURCE, /**< interrupt of LED PWM, level*/
@@ -51,7 +51,7 @@ typedef enum {
ETS_TG0_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, WATCH DOG, level*/
ETS_TG1_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER0, level*/
ETS_TG1_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, WATCHDOG, level*/
ETS_CACHE_IA_INTR_SOURCE, /**< interrupt of Cache Invalied Access, LEVEL*/
ETS_CACHE_IA_INTR_SOURCE, /**< interrupt of Cache Invalid Access, LEVEL*/
ETS_SYSTIMER_TARGET0_INTR_SOURCE, /**< interrupt of system timer 0 */
ETS_SYSTIMER_TARGET1_INTR_SOURCE, /**< interrupt of system timer 1 */
ETS_SYSTIMER_TARGET2_INTR_SOURCE, /**< interrupt of system timer 2 */
components/soc/esp32c3/include/soc/periph_defs.h
+1 -1
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@@ -18,7 +18,7 @@ typedef enum {
PERIPH_UART1_MODULE,
PERIPH_USB_DEVICE_MODULE,
PERIPH_I2C0_MODULE,
PERIPH_I2S1_MODULE,
PERIPH_I2S0_MODULE,
PERIPH_TIMG0_MODULE,
PERIPH_TIMG1_MODULE,
PERIPH_UHCI0_MODULE,
components/soc/esp32c3/interrupts.c
+6 -14
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@@ -1,16 +1,8 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/interrupts.h"
@@ -35,7 +27,7 @@ const char *const esp_isr_names[] = {
[17] = "GPIO_NMI",
[18] = "SPI1",
[19] = "SPI2",
[20] = "I2S1",
[20] = "I2S0",
[21] = "UART0",
[22] = "UART1",
[23] = "LEDC",
components/soc/esp32c3/register/soc/interrupt_core0_reg.h
+6 -6
View File
@@ -174,13 +174,13 @@ extern "C" {
#define INTERRUPT_CORE0_SPI_INTR_2_MAP_V 0x1F
#define INTERRUPT_CORE0_SPI_INTR_2_MAP_S 0
#define INTERRUPT_CORE0_I2S1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x050)
/* INTERRUPT_CORE0_I2S1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
#define INTERRUPT_CORE0_I2S_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x050)
/* INTERRUPT_CORE0_I2S_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: */
#define INTERRUPT_CORE0_I2S1_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_I2S1_INT_MAP_M ((INTERRUPT_CORE0_I2S1_INT_MAP_V)<<(INTERRUPT_CORE0_I2S1_INT_MAP_S))
#define INTERRUPT_CORE0_I2S1_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_I2S1_INT_MAP_S 0
#define INTERRUPT_CORE0_I2S_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_I2S_INT_MAP_M ((INTERRUPT_CORE0_I2S_INT_MAP_V)<<(INTERRUPT_CORE0_I2S_INT_MAP_S))
#define INTERRUPT_CORE0_I2S_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_I2S_INT_MAP_S 0
#define INTERRUPT_CORE0_UART_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x054)
/* INTERRUPT_CORE0_UART_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
components/soc/esp32c3/register/soc/sensitive_reg.h
+15 -15
View File
@@ -1308,12 +1308,12 @@ extern "C" {
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_S))
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_V 0x3
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_S 22
/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
/*description: */
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 0x00000003
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_S))
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_V 0x3
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_S 14
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0 0x00000003
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_S))
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_V 0x3
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_S 14
/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
/*description: */
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN 0x00000003
@@ -1574,12 +1574,12 @@ extern "C" {
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_S))
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_V 0x3
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_S 22
/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
/*description: */
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 0x00000003
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_S))
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_V 0x3
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_S 14
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0 0x00000003
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_S))
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_V 0x3
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_S 14
/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
/*description: */
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN 0x00000003
@@ -2152,12 +2152,12 @@ extern "C" {
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_S))
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_V 0x3
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_S 22
/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
/*description: */
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1 0x00000003
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_S))
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_V 0x3
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_S 14
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0 0x00000003
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0_S))
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0_V 0x3
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0_S 14
/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
/*description: */
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN 0x00000003
components/soc/esp32c3/register/soc/sensitive_struct.h
+3 -3
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@@ -583,7 +583,7 @@ typedef volatile struct sensitive_dev_s {
uint32_t reserved6 : 4;
uint32_t reg_core_0_pif_pms_constrain_world_0_can: 2; /*core_0_pif_pms_constrain_world_0_can*/
uint32_t reserved12 : 2;
uint32_t reg_core_0_pif_pms_constrain_world_0_i2s1: 2; /*core_0_pif_pms_constrain_world_0_i2s1*/
uint32_t reg_core_0_pif_pms_constrain_world_0_i2s0: 2; /*core_0_pif_pms_constrain_world_0_i2s0*/
uint32_t reserved16 : 6;
uint32_t reg_core_0_pif_pms_constrain_world_0_rwbt: 2; /*core_0_pif_pms_constrain_world_0_rwbt*/
uint32_t reserved24 : 2;
@@ -661,7 +661,7 @@ typedef volatile struct sensitive_dev_s {
uint32_t reserved6 : 4;
uint32_t reg_core_0_pif_pms_constrain_world_1_can: 2; /*core_0_pif_pms_constrain_world_1_can*/
uint32_t reserved12 : 2;
uint32_t reg_core_0_pif_pms_constrain_world_1_i2s1: 2; /*core_0_pif_pms_constrain_world_1_i2s1*/
uint32_t reg_core_0_pif_pms_constrain_world_1_i2s0: 2; /*core_0_pif_pms_constrain_world_1_i2s0*/
uint32_t reserved16 : 6;
uint32_t reg_core_0_pif_pms_constrain_world_1_rwbt: 2; /*core_0_pif_pms_constrain_world_1_rwbt*/
uint32_t reserved24 : 2;
@@ -898,7 +898,7 @@ typedef volatile struct sensitive_dev_s {
uint32_t reserved6 : 4;
uint32_t reg_backup_bus_pms_constrain_can: 2; /*backup_bus_pms_constrain_can*/
uint32_t reserved12 : 2;
uint32_t reg_backup_bus_pms_constrain_i2s1: 2; /*backup_bus_pms_constrain_i2s1*/
uint32_t reg_backup_bus_pms_constrain_i2s0: 2; /*backup_bus_pms_constrain_i2s0*/
uint32_t reserved16 : 6;
uint32_t reg_backup_bus_pms_constrain_rwbt: 2; /*backup_bus_pms_constrain_rwbt*/
uint32_t reserved24 : 2;
components/soc/esp32c3/register/soc/system_reg.h
+11 -23
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -134,12 +134,12 @@ extern "C" {
#define SYSTEM_SPI2_DMA_CLK_EN_M (BIT(22))
#define SYSTEM_SPI2_DMA_CLK_EN_V 0x1
#define SYSTEM_SPI2_DMA_CLK_EN_S 22
/* SYSTEM_I2S1_CLK_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */
/* SYSTEM_I2S0_CLK_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_I2S1_CLK_EN (BIT(21))
#define SYSTEM_I2S1_CLK_EN_M (BIT(21))
#define SYSTEM_I2S1_CLK_EN_V 0x1
#define SYSTEM_I2S1_CLK_EN_S 21
#define SYSTEM_I2S0_CLK_EN (BIT(21))
#define SYSTEM_I2S0_CLK_EN_M (BIT(21))
#define SYSTEM_I2S0_CLK_EN_V 0x1
#define SYSTEM_I2S0_CLK_EN_S 21
/* SYSTEM_PWM1_CLK_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_PWM1_CLK_EN (BIT(20))
@@ -236,12 +236,6 @@ extern "C" {
#define SYSTEM_UART1_CLK_EN_M (BIT(5))
#define SYSTEM_UART1_CLK_EN_V 0x1
#define SYSTEM_UART1_CLK_EN_S 5
/* SYSTEM_I2S0_CLK_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_I2S0_CLK_EN (BIT(4))
#define SYSTEM_I2S0_CLK_EN_M (BIT(4))
#define SYSTEM_I2S0_CLK_EN_V 0x1
#define SYSTEM_I2S0_CLK_EN_S 4
/* SYSTEM_WDG_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
/*description: */
#define SYSTEM_WDG_CLK_EN (BIT(3))
@@ -384,12 +378,12 @@ extern "C" {
#define SYSTEM_SPI2_DMA_RST_M (BIT(22))
#define SYSTEM_SPI2_DMA_RST_V 0x1
#define SYSTEM_SPI2_DMA_RST_S 22
/* SYSTEM_I2S1_RST : R/W ;bitpos:[21] ;default: 1'b0 ; */
/* SYSTEM_I2S0_RST : R/W ;bitpos:[21] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_I2S1_RST (BIT(21))
#define SYSTEM_I2S1_RST_M (BIT(21))
#define SYSTEM_I2S1_RST_V 0x1
#define SYSTEM_I2S1_RST_S 21
#define SYSTEM_I2S0_RST (BIT(21))
#define SYSTEM_I2S0_RST_M (BIT(21))
#define SYSTEM_I2S0_RST_V 0x1
#define SYSTEM_I2S0_RST_S 21
/* SYSTEM_PWM1_RST : R/W ;bitpos:[20] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_PWM1_RST (BIT(20))
@@ -486,12 +480,6 @@ extern "C" {
#define SYSTEM_UART1_RST_M (BIT(5))
#define SYSTEM_UART1_RST_V 0x1
#define SYSTEM_UART1_RST_S 5
/* SYSTEM_I2S0_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_I2S0_RST (BIT(4))
#define SYSTEM_I2S0_RST_M (BIT(4))
#define SYSTEM_I2S0_RST_V 0x1
#define SYSTEM_I2S0_RST_S 4
/* SYSTEM_WDG_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_WDG_RST (BIT(3))
components/soc/esp32c3/register/soc/system_struct.h
+5 -5
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -54,7 +54,7 @@ typedef volatile struct system_dev_s {
uint32_t reg_spi01_clk_en : 1; /*reg_spi01_clk_en*/
uint32_t reg_uart_clk_en : 1; /*reg_uart_clk_en*/
uint32_t reg_wdg_clk_en : 1; /*reg_wdg_clk_en*/
uint32_t reg_i2s0_clk_en : 1; /*reg_i2s0_clk_en*/
uint32_t reserved_04 : 1; /*reserved*/
uint32_t reg_uart1_clk_en : 1; /*reg_uart1_clk_en*/
uint32_t reg_spi2_clk_en : 1; /*reg_spi2_clk_en*/
uint32_t reg_i2c_ext0_clk_en : 1; /*reg_i2c_ext0_clk_en*/
@@ -71,7 +71,7 @@ typedef volatile struct system_dev_s {
uint32_t reg_i2c_ext1_clk_en : 1; /*reg_i2c_ext1_clk_en*/
uint32_t reg_can_clk_en : 1; /*reg_can_clk_en*/
uint32_t reg_pwm1_clk_en : 1; /*reg_pwm1_clk_en*/
uint32_t reg_i2s1_clk_en : 1; /*reg_i2s1_clk_en*/
uint32_t reg_i2s0_clk_en : 1; /*reg_i2s0_clk_en*/
uint32_t reg_spi2_dma_clk_en : 1; /*reg_spi2_dma_clk_en*/
uint32_t reg_usb_device_clk_en : 1; /*reg_usb_device_clk_en*/
uint32_t reg_uart_mem_clk_en : 1; /*reg_uart_mem_clk_en*/
@@ -108,7 +108,7 @@ typedef volatile struct system_dev_s {
uint32_t reg_spi01_rst : 1; /*reg_spi01_rst*/
uint32_t reg_uart_rst : 1; /*reg_uart_rst*/
uint32_t reg_wdg_rst : 1; /*reg_wdg_rst*/
uint32_t reg_i2s0_rst : 1; /*reg_i2s0_rst*/
uint32_t reserved_04 : 1; /*reserved*/
uint32_t reg_uart1_rst : 1; /*reg_uart1_rst*/
uint32_t reg_spi2_rst : 1; /*reg_spi2_rst*/
uint32_t reg_i2c_ext0_rst : 1; /*reg_i2c_ext0_rst*/
@@ -125,7 +125,7 @@ typedef volatile struct system_dev_s {
uint32_t reg_i2c_ext1_rst : 1; /*reg_i2c_ext1_rst*/
uint32_t reg_can_rst : 1; /*reg_can_rst*/
uint32_t reg_pwm1_rst : 1; /*reg_pwm1_rst*/
uint32_t reg_i2s1_rst : 1; /*reg_i2s1_rst*/
uint32_t reg_i2s0_rst : 1; /*reg_i2s0_rst*/
uint32_t reg_spi2_dma_rst : 1; /*reg_spi2_dma_rst*/
uint32_t reg_usb_device_rst : 1; /*reg_usb_device_rst*/
uint32_t reg_uart_mem_rst : 1; /*reg_uart_mem_rst*/