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feat(soc): add SOC_USB_FSLS_PHY_NUM for USB-OTG targets

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Introduce SOC_USB_FSLS_PHY_NUM on ESP32-S2, ESP32-S3 and ESP32-P4 to
expose the number of FSLS USB_WRAP PHYs available on each target. This
separates FSLS USB_WRAP support from OTG/UTMI support so that downstream
code can gate FSLS PHY handling independently.
This commit is contained in:
igor.masar
2026-04-24 13:30:58 +02:00
parent e385341956
commit eba0a57f95
6 changed files with 15 additions and 0 deletions
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components/soc/esp32s2/include/soc/Kconfig.soc_caps.in
+4
View File
@@ -907,6 +907,10 @@ config SOC_USB_OTG_PERIPH_NUM
int
default 1
config SOC_USB_FSLS_PHY_NUM
int
default 1
config SOC_SHA_DMA_MAX_BUFFER_SIZE
int
default 3968
components/soc/esp32s2/include/soc/soc_caps.h
+1
View File
@@ -381,6 +381,7 @@
/*-------------------------- USB CAPS ----------------------------------------*/
#define SOC_USB_OTG_PERIPH_NUM (1U)
#define SOC_USB_FSLS_PHY_NUM (1U)
/*--------------------------- SHA CAPS ---------------------------------------*/
/* Max amount of bytes in a single DMA operation is 4095,