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Merge branch 'change/bu_lp_console_c5' into 'master'

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change(lp_uart): Enable low-power UART functionality of ULP core on ESP32C5

Closes IDF-8633

See merge request espressif/esp-idf!31922
This commit is contained in:
Liu Xiao Yu
2024-07-09 15:54:00 +08:00
parent 048f297a44 66f7731bd8
commit ea5a48836d
6 changed files with 14 additions and 8 deletions
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components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
+4
View File
@@ -143,6 +143,10 @@ config SOC_LP_PERIPHERALS_SUPPORTED
bool
default y
config SOC_ULP_LP_UART_SUPPORTED
bool
default y
config SOC_CLK_TREE_SUPPORTED
bool
default y
components/soc/esp32c5/include/soc/soc_caps.h
+1 -1
View File
@@ -64,7 +64,7 @@
// #define SOC_LP_AON_SUPPORTED 1 // TODO: [ESP32C5] IDF-8638
#define SOC_LP_PERIPHERALS_SUPPORTED 1
// #define SOC_LP_I2C_SUPPORTED 1 // TODO: [ESP32C5] IDF-8634
// #define SOC_ULP_LP_UART_SUPPORTED 1 // TODO: [ESP32C5] IDF-8633
#define SOC_ULP_LP_UART_SUPPORTED 1
#define SOC_CLK_TREE_SUPPORTED 1
// #define SOC_ASSIST_DEBUG_SUPPORTED 1 // TODO: [ESP32C5] IDF-8663
#define SOC_WDT_SUPPORTED 1
components/ulp/lp_core/include/lp_core_uart.h
+2 -2
View File
@@ -23,7 +23,7 @@ extern "C" {
#define LP_UART_DEFAULT_RX_GPIO_NUM GPIO_NUM_15
#define LP_UART_DEFAULT_RTS_GPIO_NUM (-1)
#define LP_UART_DEFAULT_CTS_GPIO_NUM (-1)
#elif CONFIG_IDF_TARGET_ESP32C6
#elif (CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32C5)
#define LP_UART_DEFAULT_TX_GPIO_NUM GPIO_NUM_5
#define LP_UART_DEFAULT_RX_GPIO_NUM GPIO_NUM_4
#define LP_UART_DEFAULT_RTS_GPIO_NUM GPIO_NUM_2
@@ -83,7 +83,7 @@ typedef struct {
#define LP_UART_DEFAULT_CLOCK_CONFIG() \
.lp_uart_source_clk = LP_UART_SCLK_DEFAULT, \
/* Default LP UART GPIO settings and protocol parametes */
/* Default LP UART GPIO settings and protocol parameters */
#define LP_CORE_UART_DEFAULT_CONFIG() \
{ \
LP_UART_DEFAULT_GPIO_CONFIG() \