diff --git a/components/esp_hw_support/port/esp32p4/pmu_param.c b/components/esp_hw_support/port/esp32p4/pmu_param.c
index a099e2b2f13..99b410fdce7 100644
--- a/components/esp_hw_support/port/esp32p4/pmu_param.c
+++ b/components/esp_hw_support/port/esp32p4/pmu_param.c
@@ -343,7 +343,7 @@ uint32_t get_act_hp_dbias(void)
     uint32_t hp_cali_dbias = HP_CALI_ACTIVE_DBIAS_DEFAULT;
     uint32_t blk_version = efuse_hal_blk_version();
     uint32_t hp_cali_dbias_efuse = 0;
-    if (blk_version >= 2) {
+    if (blk_version >= 2 && blk_version < 100) {
         hp_cali_dbias_efuse = efuse_ll_get_active_hp_dbias();
     }
     if (hp_cali_dbias_efuse > 0) {
@@ -364,7 +364,7 @@ uint32_t get_act_lp_dbias(void)
     uint32_t lp_cali_dbias = LP_CALI_ACTIVE_DBIAS_DEFAULT;
     uint32_t blk_version = efuse_hal_blk_version();
     uint32_t lp_cali_dbias_efuse = 0;
-    if (blk_version >= 2) {
+    if (blk_version >= 2 && blk_version < 100) {
         lp_cali_dbias_efuse = efuse_ll_get_active_lp_dbias();
     }
     if (lp_cali_dbias_efuse > 0) {
diff --git a/components/esp_hw_support/port/esp32p4/pmu_pvt.c b/components/esp_hw_support/port/esp32p4/pmu_pvt.c
index 03a07258caf..c9c7ca21a42 100644
--- a/components/esp_hw_support/port/esp32p4/pmu_pvt.c
+++ b/components/esp_hw_support/port/esp32p4/pmu_pvt.c
@@ -34,7 +34,7 @@ static uint8_t get_lp_hp_gap(void)
     int8_t lp_hp_gap = 0;
     uint32_t blk_version = efuse_hal_blk_version();
     uint8_t lp_hp_gap_efuse = 0;
-    if (blk_version >= 2) {
+    if (blk_version >= 2 && blk_version < 100) {
         lp_hp_gap_efuse = efuse_ll_get_dbias_vol_gap();
         bool gap_flag = lp_hp_gap_efuse >> 4;
         uint8_t gap_abs_value = lp_hp_gap_efuse & 0xf;
@@ -78,7 +78,7 @@ static uint32_t pvt_get_lp_dbias(void)
 void pvt_auto_dbias_init(void)
 {
     uint32_t blk_version = efuse_hal_blk_version();
-    if (blk_version >= 2) {
+    if (blk_version >= 2 && blk_version < 100) {
         SET_PERI_REG_MASK(HP_SYS_CLKRST_REF_CLK_CTRL2_REG, HP_SYS_CLKRST_REG_REF_160M_CLK_EN);
         SET_PERI_REG_MASK(HP_SYS_CLKRST_SOC_CLK_CTRL1_REG, HP_SYS_CLKRST_REG_PVT_SYS_CLK_EN);
         /*config for dbias func*/
@@ -121,7 +121,7 @@ void pvt_auto_dbias_init(void)
 void pvt_func_enable(bool enable)
 {
     uint32_t blk_version = efuse_hal_blk_version();
-    if (blk_version >= 2){
+    if (blk_version >= 2 && blk_version < 100){
 
         if (enable) {
             SET_PERI_REG_MASK(HP_SYS_CLKRST_REF_CLK_CTRL2_REG, HP_SYS_CLKRST_REG_REF_160M_CLK_EN);
diff --git a/components/esp_hw_support/port/esp32p4/rtc_clk.c b/components/esp_hw_support/port/esp32p4/rtc_clk.c
index 709feb2ec30..bc7ea881111 100644
--- a/components/esp_hw_support/port/esp32p4/rtc_clk.c
+++ b/components/esp_hw_support/port/esp32p4/rtc_clk.c
@@ -220,6 +220,7 @@ static void rtc_clk_cpu_freq_to_cpll_mhz(int cpu_freq_mhz, hal_utils_clk_div_t *
     uint32_t mem_divider = 1;
     uint32_t sys_divider = 1; // We are not going to change this
     uint32_t apb_divider = 1;
+#if CONFIG_ESP32P4_SELECTS_REV_LESS_V2
     switch (cpu_freq_mhz) {
     case 360:
         mem_divider = 2;
@@ -240,6 +241,28 @@ static void rtc_clk_cpu_freq_to_cpll_mhz(int cpu_freq_mhz, hal_utils_clk_div_t *
         // To avoid such case, we will strictly do abort here.
         abort();
     }
+#else
+    switch (cpu_freq_mhz) {
+    case 400:
+        mem_divider = 2;
+        apb_divider = 2;
+        break;
+    case 200:
+        mem_divider = 1;
+        apb_divider = 2;
+        break;
+    case 100:
+        mem_divider = 1;
+        apb_divider = 1;
+        break;
+    default:
+        // Unsupported configuration
+        // This is dangerous to modify dividers. Hardware could automatically correct the divider, and it won't be
+        // reflected to the registers. Therefore, you won't even be able to calculate out the real mem_clk, apb_clk freq.
+        // To avoid such case, we will strictly do abort here.
+        abort();
+    }
+#endif
 
     // If it's upscaling, the divider of MEM/SYS/APB needs to be increased, to avoid illegal intermediate states,
     // the clock divider should be updated in the order from the APB_CLK to CPU_CLK.
@@ -285,6 +308,7 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *ou
 
     // Keep default CPLL at 360MHz
     uint32_t xtal_freq = (uint32_t)rtc_clk_xtal_freq_get();
+#if CONFIG_ESP32P4_SELECTS_REV_LESS_V2
     if (freq_mhz <= xtal_freq && freq_mhz != 0) {
         divider.integer = xtal_freq / freq_mhz;
         real_freq_mhz = (xtal_freq + divider.integer / 2) / divider.integer; /* round */
@@ -292,7 +316,6 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *ou
             // no suitable divider
             return false;
         }
-
         source_freq_mhz = xtal_freq;
         source = SOC_CPU_CLK_SRC_XTAL;
     } else if (freq_mhz == 90) {
@@ -310,6 +333,30 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *ou
         source = SOC_CPU_CLK_SRC_CPLL;
         source_freq_mhz = CLK_LL_PLL_360M_FREQ_MHZ;
         divider.integer = 1;
+    } else {
+        // unsupported frequency
+        return false;
+    }
+#else
+    if (freq_mhz <= xtal_freq && freq_mhz != 0) {
+        divider.integer = xtal_freq / freq_mhz;
+        real_freq_mhz = (xtal_freq + divider.integer / 2) / divider.integer; /* round */
+        if (real_freq_mhz != freq_mhz) {
+            // no suitable divider
+            return false;
+        }
+        source_freq_mhz = xtal_freq;
+        source = SOC_CPU_CLK_SRC_XTAL;
+    } else if (freq_mhz == 100) {
+        real_freq_mhz = freq_mhz;
+        source = SOC_CPU_CLK_SRC_CPLL;
+        source_freq_mhz = CLK_LL_PLL_400M_FREQ_MHZ;
+        divider.integer = 4;
+    } else if (freq_mhz == 200) {
+        real_freq_mhz = freq_mhz;
+        source = SOC_CPU_CLK_SRC_CPLL;
+        source_freq_mhz = CLK_LL_PLL_400M_FREQ_MHZ;
+        divider.integer = 2;
     } else if (freq_mhz == 400) {
         // If CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ selects 400MHz, then at app startup stage will need a CPLL calibration to raise its freq from 360MHz to 400MHz
         real_freq_mhz = freq_mhz;
@@ -320,6 +367,7 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *ou
         // unsupported frequency
         return false;
     }
+#endif
     *out_config = (rtc_cpu_freq_config_t) {
         .source = source,
         .div = divider,
diff --git a/components/esp_system/port/soc/esp32p4/Kconfig.cpu b/components/esp_system/port/soc/esp32p4/Kconfig.cpu
index 18ad8025983..9a9ab5c0955 100644
--- a/components/esp_system/port/soc/esp32p4/Kconfig.cpu
+++ b/components/esp_system/port/soc/esp32p4/Kconfig.cpu
@@ -1,7 +1,8 @@
 choice ESP_DEFAULT_CPU_FREQ_MHZ
     prompt "CPU frequency"
     default ESP_DEFAULT_CPU_FREQ_MHZ_40 if IDF_ENV_FPGA || ESP_BRINGUP_BYPASS_CPU_CLK_SETTING
-    default ESP_DEFAULT_CPU_FREQ_MHZ_360
+    default ESP_DEFAULT_CPU_FREQ_MHZ_360 if ESP32P4_SELECTS_REV_LESS_V2
+    default ESP_DEFAULT_CPU_FREQ_MHZ_400
     help
         CPU frequency to be set on application startup.
 
@@ -10,9 +11,13 @@ choice ESP_DEFAULT_CPU_FREQ_MHZ
         depends on IDF_ENV_FPGA || ESP_BRINGUP_BYPASS_CPU_CLK_SETTING
     config ESP_DEFAULT_CPU_FREQ_MHZ_360
         bool "360 MHz"
+        depends on ESP32P4_SELECTS_REV_LESS_V2
+    config ESP_DEFAULT_CPU_FREQ_MHZ_400
+        bool "400 MHz"
 endchoice
 
 config ESP_DEFAULT_CPU_FREQ_MHZ
     int
     default 40 if ESP_DEFAULT_CPU_FREQ_MHZ_40
     default 360 if ESP_DEFAULT_CPU_FREQ_MHZ_360
+    default 400 if ESP_DEFAULT_CPU_FREQ_MHZ_400