feat(hal): graudate the parlio hal driver into a new component

components/esp_hal_parlio/include/hal/parlio_hal.h

@@ -0,0 +1,47 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*******************************************************************************
+ * NOTICE
+ * The hal is not public api, don't use in application code.
+ * See readme.md in hal/include/hal/readme.md
+ ******************************************************************************/
+
+#pragma once
+
+#include <stdint.h>
+#include "hal/parlio_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct parl_io_dev_t *parlio_soc_handle_t; // Parallel IO SOC layer handle
+
+/**
+ * @brief HAL context type of Parallel IO driver
+ */
+typedef struct {
+    parlio_soc_handle_t regs; /*!< Parallel IO Register base address */
+} parlio_hal_context_t;
+
+/**
+ * @brief Initialize the Parallel IO HAL driver
+ *
+ * @param hal: Parallel IO HAL context
+ */
+void parlio_hal_init(parlio_hal_context_t *hal);
+
+/**
+ * @brief Deinitialize the Parallel IO HAL driver
+ *
+ * @param hal: Parallel IO HAL context
+ */
+void parlio_hal_deinit(parlio_hal_context_t *hal);
+
+#ifdef __cplusplus
+}
+#endif

components/esp_hal_parlio/include/hal/parlio_periph.h

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+/*
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+#include "soc/periph_defs.h"
+#if SOC_PARLIO_SUPPORTED
+#include "soc/parl_io_reg.h"
+#include "soc/parl_io_struct.h"
+#endif
+#include "soc/regdma.h"
+#if SOC_PARLIO_SUPPORT_SLEEP_RETENTION
+#include "soc/retention_periph_defs.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if SOC_PARLIO_SUPPORTED
+typedef struct {
+    struct {
+        struct {
+            const int data_sigs[SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH];
+            const int clk_out_sig;
+            const int clk_in_sig;
+            const int cs_sig;
+        } tx_units[SOC_PARLIO_TX_UNITS_PER_GROUP];
+        struct {
+            const int data_sigs[SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH];
+            const int clk_out_sig;
+            const int clk_in_sig;
+        } rx_units[SOC_PARLIO_RX_UNITS_PER_GROUP];
+        const int tx_irq_id;
+        const int rx_irq_id;
+        const shared_periph_module_t module;
+        const char *module_name;
+    } groups[SOC_PARLIO_GROUPS];
+} parlio_signal_conn_t;
+
+extern const parlio_signal_conn_t parlio_periph_signals;
+
+#if SOC_PARLIO_SUPPORT_SLEEP_RETENTION
+typedef struct {
+    const periph_retention_module_t retention_module;
+    const regdma_entries_config_t *regdma_entry_array;
+    uint32_t array_size;
+} parlio_reg_retention_info_t;
+
+extern const parlio_reg_retention_info_t parlio_reg_retention_info[SOC_PARLIO_GROUPS];
+#endif // SOC_PARLIO_SUPPORT_SLEEP_RETENTION
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/esp_hal_parlio/include/hal/parlio_types.h

@@ -0,0 +1,71 @@
+/*
+ * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "soc/soc_caps.h"
+#include "soc/clk_tree_defs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Parallel IO sample edge
+ */
+typedef enum {
+    PARLIO_SAMPLE_EDGE_NEG, /*!< Sample data on falling edge of clock */
+    PARLIO_SAMPLE_EDGE_POS, /*!< Sample data on rising edge of clock */
+} parlio_sample_edge_t;
+
+/**
+ * @brief Parallel IO bit packing order
+ *
+ * Data in memory:
+ * Byte 0: MSB < B0.7 B0.6 B0.5 B0.4 B0.3 B0.2 B0.1 B0.0 > LSB
+ * Byte 1: MSB < B1.7 B1.6 B1.5 B1.4 B1.3 B1.2 B1.1 B1.0 > LSB
+ *
+ * Output on line (PARLIO_BIT_PACK_ORDER_LSB):
+ *          Cycle 0   Cycle 1   Cycle 2  ---> time
+ * GPIO 0:   B0.0      B0.4      B1.0
+ * GPIO 1:   B0.1      B0.5      B1.1
+ * GPIO 2:   B0.2      B0.6      B1.2
+ * GPIO 3:   B0.3      B0.7      B1.3
+ *
+ * Output on line (PARLIO_BIT_PACK_ORDER_MSB):
+ *          Cycle 0   Cycle 1   Cycle 2  ---> time
+ * GPIO 0:   B0.4      B0.0      B1.4
+ * GPIO 1:   B0.5      B0.1      B1.5
+ * GPIO 2:   B0.6      B0.2      B1.6
+ * GPIO 3:   B0.7      B0.3      B1.7
+ */
+typedef enum {
+    PARLIO_BIT_PACK_ORDER_LSB, /*!< Bit pack order: LSB */
+    PARLIO_BIT_PACK_ORDER_MSB, /*!< Bit pack order: MSB */
+} parlio_bit_pack_order_t;
+
+#if SOC_PARLIO_SUPPORTED
+/**
+ * @brief Parallel IO clock source
+ * @note User should select the clock source based on the power and resolution requirement
+ */
+typedef soc_periph_parlio_clk_src_t parlio_clock_source_t;
+
+/// Maximum data width of TX unit
+#define PARLIO_TX_UNIT_MAX_DATA_WIDTH SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH
+/// Maximum data width of RX unit
+#define PARLIO_RX_UNIT_MAX_DATA_WIDTH SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH
+#else
+typedef int parlio_clock_source_t;
+#define PARLIO_TX_UNIT_MAX_DATA_WIDTH 0
+#define PARLIO_RX_UNIT_MAX_DATA_WIDTH 0
+#endif // SOC_PARLIO_SUPPORTED
+
+#ifdef __cplusplus
+}
+#endif