mirror of
https://github.com/espressif/esp-idf.git
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feat(hal): graudate the parlio hal driver into a new component
This commit is contained in:
laokaiyao
@@ -0,0 +1,18 @@
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idf_build_get_property(target IDF_TARGET)
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if(${target} STREQUAL "linux")
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return() # This component is not supported by the POSIX/Linux simulator
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endif()
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set(srcs)
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set(includes "include")
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if(EXISTS "${CMAKE_CURRENT_LIST_DIR}/${target}/include")
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list(APPEND includes "${target}/include")
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endif()
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if(CONFIG_SOC_PARLIO_SUPPORTED)
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list(APPEND srcs "${target}/parlio_periph.c" "parlio_hal.c")
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endif()
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idf_component_register(SRCS ${srcs}
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INCLUDE_DIRS ${includes}
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REQUIRES soc hal)
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@@ -0,0 +1,81 @@
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# ESP Hardware Abstraction Layer for Parallel IO Peripheral(s)
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> [!NOTE]
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> This component is currently in beta. Its API, behavior, and compatibility may change at any time and without notice; backward compatibility is not guaranteed. Use caution when integrating into production systems.
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## Overview
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The `esp_hal_parlio` component provides a **Hardware Abstraction Layer** for Parallel IO (PARLIO) peripherals across all ESP-IDF supported targets. PARLIO enables high-speed parallel data transfer between the ESP chip and external devices, supporting both transmit (TX) and receive (RX) operations with configurable data widths and timing characteristics.
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## Architecture
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The PARLIO HAL is structured in two main sub-layers:
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1. **HAL Layer (Upper)**: Defines the operational steps and data structures required to control PARLIO peripherals (e.g., initialization, unit configuration, transfer start/stop).
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2. **Low-Level Layer (Bottom)**: Serves as a translation layer between the HAL and the register files defined in the `soc` component, handling target-specific register configurations.
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## Supported PARLIO Units
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This HAL supports PARLIO peripherals with the following units depending on the ESP chip:
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- **TX Unit**: Transmits parallel data to external devices
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- Configurable data width
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- Clock output or external clock input support
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- Chip select (CS) signal support (on some chips)
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- Valid signal generation and delay control
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- **RX Unit**: Receives parallel data from external devices
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- Configurable data width
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- Clock input support
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- Multiple sampling modes (level-controlled, pulse-controlled, software-controlled)
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- Timeout detection support
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## Features
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### Clock Configuration
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- Multiple clock source selection
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- Configurable clock divider with integer and fractional support (on some chips)
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- Independent clock configuration for TX and RX units
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### Data Transfer Control
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- Configurable bus width
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- Bit packing order configuration (LSB/MSB)
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- Sample clock edge selection (rising/falling edge)
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- Frame length configuration
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### RX Unit Features
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- Level-controlled receive mode with active high/low enable signal
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- Pulse-controlled receive mode with configurable start/end pulse counting
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- Software-controlled receive mode
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- RX timeout detection and threshold configuration
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- Clock gating support
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- Data line as enable signal support
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### TX Unit Features
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- Data length configuration
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- Clock gating support
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- Valid signal generation and delay control (on some chips)
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- Idle data value configuration
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- DMA EOF condition support (on some chips)
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### Interrupt and Event Handling
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- TX FIFO empty event
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- RX FIFO full event
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- TX EOF (End of Frame) event
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- Interrupt enable/disable and status management
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### Power Management
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- Sleep retention support (on some chips)
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- Register state preservation during sleep
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## Usage
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The HAL functions primarily serve ESP-IDF peripheral drivers such as `esp_driver_parlio`.
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Advanced developers can use these interfaces directly when implementing custom drivers, with the understanding that API stability is not guaranteed.
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## Dependencies
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- `soc`: Provides chip-specific register definitions
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- `hal`: Core hardware abstraction utilities and macros
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@@ -0,0 +1,713 @@
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/*
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* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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// Note that most of the register operations in this layer are non-atomic operations.
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#pragma once
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#include <stdbool.h>
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#include <stdint.h>
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#include "hal/assert.h"
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#include "hal/misc.h"
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#include "hal/hal_utils.h"
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#include "soc/pcr_struct.h"
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#include "soc/parl_io_struct.h"
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#include "hal/parlio_types.h"
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#define PARLIO_LL_RX_MAX_BYTES_PER_FRAME 0xFFFF
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#define PARLIO_LL_RX_MAX_CLK_INT_DIV 0x10000
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#define PARLIO_LL_RX_MAX_CLK_FRACT_DIV 0 // Not support fractional divider
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#define PARLIO_LL_RX_MAX_TIMEOUT 0xFFFF
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#define PARLIO_LL_TX_MAX_BITS_PER_FRAME 0x7FFFF
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#define PARLIO_LL_TX_MAX_CLK_INT_DIV 0x10000
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#define PARLIO_LL_TX_MAX_CLK_FRACT_DIV 0 // Not support fractional divider
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#define PARLIO_LL_EVENT_TX_FIFO_EMPTY (1 << 0)
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#define PARLIO_LL_EVENT_RX_FIFO_FULL (1 << 1)
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#define PARLIO_LL_EVENT_TX_EOF (1 << 2)
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#define PARLIO_LL_EVENT_TX_MASK (PARLIO_LL_EVENT_TX_FIFO_EMPTY | PARLIO_LL_EVENT_TX_EOF)
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#define PARLIO_LL_EVENT_RX_MASK (PARLIO_LL_EVENT_RX_FIFO_FULL)
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#define PARLIO_LL_TX_DATA_LINE_AS_CLK_GATE 7 // TXD[7] can be used as clock gate signal
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#define PARLIO_LL_TX_VALID_MAX_DELAY 32767
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef enum {
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PARLIO_LL_RX_EOF_COND_RX_FULL, /*!< RX unit generates EOF event when it receives enough data */
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PARLIO_LL_RX_EOF_COND_EN_INACTIVE, /*!< RX unit generates EOF event when the external enable signal becomes inactive */
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} parlio_ll_rx_eof_cond_t;
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typedef enum {
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PARLIO_LL_TX_EOF_COND_DATA_LEN, /*!< TX unit generates EOF event when it transmits particular data bit length that specified in `tx_bitlen`. */
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PARLIO_LL_TX_EOF_COND_DMA_EOF, /*!< TX unit generates EOF event when the DMA EOF takes place */
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} parlio_ll_tx_eof_cond_t;
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/**
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* @brief Enable or disable the parlio peripheral APB clock
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*
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* @param group_id The group id of the parlio module
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* @param enable Set true to enable, false to disable
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*/
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static inline void parlio_ll_enable_bus_clock(int group_id, bool enable)
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{
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(void)group_id;
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PCR.parl_io_conf.parl_clk_en = enable;
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}
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/**
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* @brief Reset the parlio module
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*
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* @param group_id The group id of the parlio module
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*/
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static inline void parlio_ll_reset_register(int group_id)
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{
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(void)group_id;
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PCR.parl_io_conf.parl_rst_en = 1;
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PCR.parl_io_conf.parl_rst_en = 0;
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}
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///////////////////////////////////////RX Unit///////////////////////////////////////
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/**
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* @brief Set the clock source for the RX unit
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*
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* @param dev Parallel IO register base address
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* @param src Clock source
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*/
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static inline void parlio_ll_rx_set_clock_source(parl_io_dev_t *dev, parlio_clock_source_t src)
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{
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(void)dev;
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uint32_t clk_sel = 0;
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switch (src) {
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case PARLIO_CLK_SRC_XTAL:
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clk_sel = 0;
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break;
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case PARLIO_CLK_SRC_RC_FAST:
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clk_sel = 1;
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break;
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case PARLIO_CLK_SRC_PLL_F240M:
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clk_sel = 2;
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break;
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case PARLIO_CLK_SRC_EXTERNAL:
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clk_sel = 3;
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break;
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default: // unsupported clock source
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HAL_ASSERT(false);
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break;
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}
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PCR.parl_clk_rx_conf.parl_clk_rx_sel = clk_sel;
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}
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/**
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* @brief Set the clock divider for the RX unit
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*
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* @param dev Parallel IO register base address
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* @param clk_div Clock division with integral part, no fractional part on C5
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*/
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static inline void parlio_ll_rx_set_clock_div(parl_io_dev_t *dev, const hal_utils_clk_div_t *clk_div)
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{
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(void)dev;
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HAL_ASSERT(clk_div->integer > 0 && clk_div->integer <= PARLIO_LL_RX_MAX_CLK_INT_DIV);
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HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.parl_clk_rx_conf, parl_clk_rx_div_num, clk_div->integer - 1);
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}
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/**
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* @brief Reset the RX unit Core clock domain
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*
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* @param dev Parallel IO register base address
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*/
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static inline void parlio_ll_rx_reset_clock(parl_io_dev_t *dev)
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{
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(void)dev;
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PCR.parl_clk_rx_conf.parl_rx_rst_en = 1;
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PCR.parl_clk_rx_conf.parl_rx_rst_en = 0;
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}
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/**
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* @brief Enable the RX unit Core clock domain
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*
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* @param dev Parallel IO register base address
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* @param en True to enable, False to disable
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*/
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__attribute__((always_inline))
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static inline void parlio_ll_rx_enable_clock(parl_io_dev_t *dev, bool en)
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{
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(void)dev;
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PCR.parl_clk_rx_conf.parl_clk_rx_en = en;
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}
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/**
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* @brief Set the condition to generate the RX EOF event
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*
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* @param dev Parallel IO register base address
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* @param cond RX EOF condition
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*/
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__attribute__((always_inline))
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static inline void parlio_ll_rx_set_eof_condition(parl_io_dev_t *dev, parlio_ll_rx_eof_cond_t cond)
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{
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dev->rx_genrl_cfg.rx_eof_gen_sel = cond;
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}
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/**
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* @brief Start RX unit to sample the input data
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*
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* @param dev Parallel IO register base address
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* @param en True to start, False to stop
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*/
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__attribute__((always_inline))
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static inline void parlio_ll_rx_start(parl_io_dev_t *dev, bool en)
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{
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dev->rx_start_cfg.rx_start = en;
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}
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/**
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* @brief Set the receive length
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*
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* @note The receive length can be used to generate DMA EOF signal, or to work as a frame end delimiter
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*
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* @param dev Parallel IO register base address
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* @param bitlen Number of bits to receive in the next transaction, bitlen must be a multiple of 8
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*/
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__attribute__((always_inline))
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static inline void parlio_ll_rx_set_recv_bit_len(parl_io_dev_t *dev, uint32_t bitlen)
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{
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dev->rx_data_cfg.rx_bitlen = bitlen;
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}
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/**
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* @brief Set the sub mode of the level controlled receive mode
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*
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* @param dev Parallel IO register base address
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* @param active_low_en Level of the external enable signal, true for active low, false for active high
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*/
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__attribute__((always_inline))
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static inline void parlio_ll_rx_set_level_recv_mode(parl_io_dev_t *dev, bool active_low_en)
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{
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dev->rx_mode_cfg.rx_smp_mode_sel = 0;
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dev->rx_mode_cfg.rx_ext_en_inv = active_low_en;
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}
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/**
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* @brief Set the sub mode of the pulse controlled receive mode
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*
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* @param dev Parallel IO register base address
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* @param start_inc Whether the start pulse is counted
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* @param end_inc Whether the end pulse is counted
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* @param end_by_len Whether to use the frame length to determine the end of the frame
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* @param pulse_inv Whether the pulse is inverted
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*/
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__attribute__((always_inline))
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static inline void parlio_ll_rx_set_pulse_recv_mode(parl_io_dev_t *dev, bool start_inc, bool end_inc, bool end_by_len, bool pulse_inv)
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{
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uint32_t submode = 0;
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uint32_t step = 1;
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if (end_by_len) {
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submode += 4;
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} else { // end by pulse
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step = 2;
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if (!end_inc) {
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submode += 1;
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}
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}
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if (!start_inc) {
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submode += step;
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}
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dev->rx_mode_cfg.rx_smp_mode_sel = 1;
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dev->rx_mode_cfg.rx_pulse_submode_sel = submode;
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dev->rx_mode_cfg.rx_ext_en_inv = pulse_inv;
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}
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/**
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* @brief Set the receive mode to software controlled receive mode
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*
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* @param dev Parallel IO register base address
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*/
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__attribute__((always_inline))
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static inline void parlio_ll_rx_set_soft_recv_mode(parl_io_dev_t *dev)
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{
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dev->rx_mode_cfg.rx_smp_mode_sel = 2;
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}
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/**
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* @brief Whether to start the software controlled receive mode
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*
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* @param dev Parallel IO register base address
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* @param en True to enable, False to disable
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*/
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static inline void parlio_ll_rx_start_soft_recv(parl_io_dev_t *dev, bool en)
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{
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dev->rx_mode_cfg.rx_sw_en = en;
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}
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/**
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* @brief Set the sample clock edge
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*
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* @param dev Parallel IO register base address
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* @param edge Sample clock edge
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*/
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__attribute__((always_inline))
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static inline void parlio_ll_rx_set_sample_clock_edge(parl_io_dev_t *dev, parlio_sample_edge_t edge)
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{
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dev->rx_clk_cfg.rx_clk_i_inv = edge;
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dev->rx_clk_cfg.rx_clk_o_inv = edge;
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}
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/**
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* @brief Set the order to pack bits into one byte
|
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*
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* @param dev Parallel IO register base address
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* @param order Packing order
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*/
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__attribute__((always_inline))
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static inline void parlio_ll_rx_set_bit_pack_order(parl_io_dev_t *dev, parlio_bit_pack_order_t order)
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{
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dev->rx_data_cfg.rx_data_order_inv = order;
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}
|
||||
|
||||
/**
|
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* @brief Set the bus width of the RX unit
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*
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* @param dev Parallel IO register base address
|
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* @param width Bus width
|
||||
*/
|
||||
static inline void parlio_ll_rx_set_bus_width(parl_io_dev_t *dev, uint32_t width)
|
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{
|
||||
uint32_t width_sel = 0;
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||||
switch (width) {
|
||||
case 8:
|
||||
width_sel = 3;
|
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break;
|
||||
case 4:
|
||||
width_sel = 2;
|
||||
break;
|
||||
case 2:
|
||||
width_sel = 1;
|
||||
break;
|
||||
case 1:
|
||||
width_sel = 0;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(false);
|
||||
}
|
||||
dev->rx_data_cfg.rx_bus_wid_sel = width_sel;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reset RX Async FIFO
|
||||
*
|
||||
* @note During the reset of the asynchronous FIFO, it takes two clock cycles to synchronize within AHB clock domain (GDMA) and Core clock domain.
|
||||
* The reset synchronization must be performed two clock cycles in advance.
|
||||
* @note If the next frame transfer needs to be reset, you need to first switch to the internal free-running clock,
|
||||
* and then switch to the actual clock after the reset is completed.
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
*/
|
||||
static inline void parlio_ll_rx_reset_fifo(parl_io_dev_t *dev)
|
||||
{
|
||||
dev->fifo_cfg.rx_fifo_srst = 1;
|
||||
dev->fifo_cfg.rx_fifo_srst = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set which data line as the enable signal
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param line_num Data line number (0-15)
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_rx_treat_data_line_as_en(parl_io_dev_t *dev, uint32_t line_num)
|
||||
{
|
||||
dev->rx_mode_cfg.rx_ext_en_sel = line_num;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Whether to enable the RX clock gating
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param en True to enable, False to disable
|
||||
*/
|
||||
static inline void parlio_ll_rx_enable_clock_gating(parl_io_dev_t *dev, bool en)
|
||||
{
|
||||
dev->rx_genrl_cfg.rx_gating_en = en;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable RX timeout feature
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param en True to enable, False to disable
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_rx_enable_timeout(parl_io_dev_t *dev, bool en)
|
||||
{
|
||||
dev->rx_genrl_cfg.rx_timeout_en = en;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the threshold of RX timeout
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param thres Threshold of RX timeout
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_rx_set_timeout_thres(parl_io_dev_t *dev, uint32_t thres)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->rx_genrl_cfg, rx_timeout_thres, thres);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update the RX configuration, to make the new configuration take effect
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_rx_update_config(parl_io_dev_t *dev)
|
||||
{
|
||||
dev->reg_update.rx_reg_update = 1;
|
||||
while (dev->reg_update.rx_reg_update);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the RX fifo cycle count
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @return
|
||||
* - RX fifo cycle count
|
||||
*/
|
||||
static inline uint32_t parlio_ll_rx_get_fifo_cycle_cnt(parl_io_dev_t *dev)
|
||||
{
|
||||
return dev->rx_st0.rx_cnt;
|
||||
}
|
||||
|
||||
///////////////////////////////////TX Unit///////////////////////////////////////
|
||||
|
||||
/**
|
||||
* @brief Set the clock source for the TX unit
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param src Clock source
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_tx_set_clock_source(parl_io_dev_t *dev, parlio_clock_source_t src)
|
||||
{
|
||||
(void)dev;
|
||||
uint32_t clk_sel = 0;
|
||||
switch (src) {
|
||||
case PARLIO_CLK_SRC_XTAL:
|
||||
clk_sel = 0;
|
||||
break;
|
||||
case PARLIO_CLK_SRC_RC_FAST:
|
||||
clk_sel = 1;
|
||||
break;
|
||||
case PARLIO_CLK_SRC_PLL_F240M:
|
||||
clk_sel = 2;
|
||||
break;
|
||||
case PARLIO_CLK_SRC_EXTERNAL:
|
||||
clk_sel = 3;
|
||||
break;
|
||||
|
||||
default: // unsupported clock source
|
||||
HAL_ASSERT(false);
|
||||
break;
|
||||
}
|
||||
PCR.parl_clk_tx_conf.parl_clk_tx_sel = clk_sel;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the clock divider for the TX unit
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param clk_div Clock division with integral part, no fractional part on C5
|
||||
*/
|
||||
static inline void parlio_ll_tx_set_clock_div(parl_io_dev_t *dev, const hal_utils_clk_div_t *clk_div)
|
||||
{
|
||||
(void)dev;
|
||||
HAL_ASSERT(clk_div->integer > 0 && clk_div->integer <= PARLIO_LL_RX_MAX_CLK_INT_DIV);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.parl_clk_tx_conf, parl_clk_tx_div_num, clk_div->integer - 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reset the TX unit Core clock domain
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_tx_reset_clock(parl_io_dev_t *dev)
|
||||
{
|
||||
(void)dev;
|
||||
PCR.parl_clk_tx_conf.parl_tx_rst_en = 1;
|
||||
PCR.parl_clk_tx_conf.parl_tx_rst_en = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the TX unit Core clock domain
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param en True to enable, False to disable
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_tx_enable_clock(parl_io_dev_t *dev, bool en)
|
||||
{
|
||||
(void)dev;
|
||||
PCR.parl_clk_tx_conf.parl_clk_tx_en = en;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the data length to be transmitted
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param bitlen Data length in bits, must be a multiple of 8
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_tx_set_trans_bit_len(parl_io_dev_t *dev, uint32_t bitlen)
|
||||
{
|
||||
dev->tx_data_cfg.tx_bitlen = bitlen;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if tx size can be determined by DMA
|
||||
*
|
||||
* @param dev Parallel IO register base address (not used)
|
||||
*/
|
||||
static inline bool parlio_ll_tx_support_dma_eof(parl_io_dev_t *dev)
|
||||
{
|
||||
(void)dev;
|
||||
return true;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the condition to generate the TX EOF event
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param cond TX EOF condition
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_tx_set_eof_condition(parl_io_dev_t *dev, parlio_ll_tx_eof_cond_t cond)
|
||||
{
|
||||
dev->tx_genrl_cfg.tx_eof_gen_sel = cond;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Whether to enable the TX clock gating
|
||||
*
|
||||
* @note The MSB of TXD will be taken as the gating enable signal
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param en True to enable, False to disable
|
||||
*/
|
||||
static inline void parlio_ll_tx_enable_clock_gating(parl_io_dev_t *dev, bool en)
|
||||
{
|
||||
dev->tx_genrl_cfg.tx_gating_en = en;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Start TX unit to transmit data
|
||||
*
|
||||
* @note The hardware monitors the rising edge of tx_start as the trigger signal.
|
||||
* Once the transmission starts, it cannot be stopped by clearing tx_start.
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param en True to start, False to reset the reg state (not meaning the TX unit will be stopped)
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_tx_start(parl_io_dev_t *dev, bool en)
|
||||
{
|
||||
dev->tx_start_cfg.tx_start = en;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the clock gating from the valid signal
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param en If set to true, the clock is gated by the valid signal, otherwise it is gated by the MSB of the data line.
|
||||
*/
|
||||
static inline void parlio_ll_tx_clock_gating_from_valid(parl_io_dev_t *dev, bool en)
|
||||
{
|
||||
dev->tx_genrl_cfg.tx_valid_output_en = en;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set TX valid signal delay
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param start_delay Number of clock cycles to delay
|
||||
* @param stop_delay Number of clock cycles to delay
|
||||
* @return true: success, false: valid delay is not supported
|
||||
*/
|
||||
static inline bool parlio_ll_tx_set_valid_delay(parl_io_dev_t *dev, uint32_t start_delay, uint32_t stop_delay)
|
||||
{
|
||||
if (start_delay > PARLIO_LL_TX_VALID_MAX_DELAY || stop_delay > PARLIO_LL_TX_VALID_MAX_DELAY) {
|
||||
return false;
|
||||
}
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->tx_cs_cfg, tx_cs_start_delay, start_delay);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->tx_cs_cfg, tx_cs_stop_delay, stop_delay);
|
||||
return true;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the sample clock edge
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param edge Sample clock edge
|
||||
*/
|
||||
static inline void parlio_ll_tx_set_sample_clock_edge(parl_io_dev_t *dev, parlio_sample_edge_t edge)
|
||||
{
|
||||
dev->tx_clk_cfg.tx_clk_i_inv = edge;
|
||||
dev->tx_clk_cfg.tx_clk_o_inv = edge;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the order to unpack bits from a byte
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param order Packing order
|
||||
*/
|
||||
static inline void parlio_ll_tx_set_bit_pack_order(parl_io_dev_t *dev, parlio_bit_pack_order_t order)
|
||||
{
|
||||
dev->tx_data_cfg.tx_data_order_inv = order;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the bus width of the TX unit
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param width Bus width
|
||||
*/
|
||||
static inline void parlio_ll_tx_set_bus_width(parl_io_dev_t *dev, uint32_t width)
|
||||
{
|
||||
uint32_t width_sel = 0;
|
||||
switch (width) {
|
||||
case 8:
|
||||
width_sel = 3;
|
||||
break;
|
||||
case 4:
|
||||
width_sel = 2;
|
||||
break;
|
||||
case 2:
|
||||
width_sel = 1;
|
||||
break;
|
||||
case 1:
|
||||
width_sel = 0;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(false);
|
||||
}
|
||||
dev->tx_data_cfg.tx_bus_wid_sel = width_sel;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reset TX Async FIFO
|
||||
*
|
||||
* @note During the reset of the asynchronous FIFO, it takes two clock cycles to synchronize within AHB clock domain (GDMA) and Core clock domain.
|
||||
* The reset synchronization must be performed two clock cycles in advance.
|
||||
* @note If the next frame transfer needs to be reset, you need to first switch to the internal free-running clock,
|
||||
* and then switch to the actual clock after the reset is completed.
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_tx_reset_fifo(parl_io_dev_t *dev)
|
||||
{
|
||||
dev->fifo_cfg.tx_fifo_srst = 1;
|
||||
dev->fifo_cfg.tx_fifo_srst = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the value to output on the TXD when the TX unit is in IDLE state
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param value Value to output
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_tx_set_idle_data_value(parl_io_dev_t *dev, uint32_t value)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->tx_genrl_cfg, tx_idle_value, value);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check whether the TX unit is ready
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @return true: ready, false: busy
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool parlio_ll_tx_is_ready(parl_io_dev_t *dev)
|
||||
{
|
||||
return dev->st.tx_ready;
|
||||
}
|
||||
|
||||
////////////////////////////////////Interrupt////////////////////////////////////////////////
|
||||
|
||||
/**
|
||||
* @brief Enable Parallel IO interrupt for specific event mask
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param mask Event mask
|
||||
* @param enable True to enable, False to disable
|
||||
*/
|
||||
static inline void parlio_ll_enable_interrupt(parl_io_dev_t *dev, uint32_t mask, bool enable)
|
||||
{
|
||||
if (enable) {
|
||||
dev->int_ena.val |= mask;
|
||||
} else {
|
||||
dev->int_ena.val &= ~mask;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get interrupt status for TX unit
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @return Interrupt status
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t parlio_ll_tx_get_interrupt_status(parl_io_dev_t *dev)
|
||||
{
|
||||
return dev->int_st.val & PARLIO_LL_EVENT_TX_MASK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get interrupt status for RX unit
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @return Interrupt status
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t parlio_ll_rx_get_interrupt_status(parl_io_dev_t *dev)
|
||||
{
|
||||
return dev->int_st.val & PARLIO_LL_EVENT_RX_MASK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear Parallel IO interrupt status by mask
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param mask Interrupt status mask
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_clear_interrupt_status(parl_io_dev_t *dev, uint32_t mask)
|
||||
{
|
||||
dev->int_clr.val = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get interrupt status register address
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @return Register address
|
||||
*/
|
||||
static inline volatile void *parlio_ll_get_interrupt_status_reg(parl_io_dev_t *dev)
|
||||
{
|
||||
return &dev->int_st;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,81 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "hal/parlio_periph.h"
|
||||
#include "soc/gpio_sig_map.h"
|
||||
|
||||
const parlio_signal_conn_t parlio_periph_signals = {
|
||||
.groups = {
|
||||
[0] = {
|
||||
.module_name = "PARLIO0",
|
||||
.tx_irq_id = ETS_PARL_IO_TX_INTR_SOURCE,
|
||||
.rx_irq_id = ETS_PARL_IO_RX_INTR_SOURCE,
|
||||
.tx_units = {
|
||||
[0] = {
|
||||
.data_sigs = {
|
||||
PARL_TX_DATA0_IDX,
|
||||
PARL_TX_DATA1_IDX,
|
||||
PARL_TX_DATA2_IDX,
|
||||
PARL_TX_DATA3_IDX,
|
||||
PARL_TX_DATA4_IDX,
|
||||
PARL_TX_DATA5_IDX,
|
||||
PARL_TX_DATA6_IDX,
|
||||
PARL_TX_DATA7_IDX,
|
||||
},
|
||||
.clk_out_sig = PARL_TX_CLK_OUT_IDX,
|
||||
.clk_in_sig = PARL_TX_CLK_IN_IDX,
|
||||
.cs_sig = PARL_TX_CS_O_IDX,
|
||||
}
|
||||
},
|
||||
.rx_units = {
|
||||
[0] = {
|
||||
.data_sigs = {
|
||||
PARL_RX_DATA0_IDX,
|
||||
PARL_RX_DATA1_IDX,
|
||||
PARL_RX_DATA2_IDX,
|
||||
PARL_RX_DATA3_IDX,
|
||||
PARL_RX_DATA4_IDX,
|
||||
PARL_RX_DATA5_IDX,
|
||||
PARL_RX_DATA6_IDX,
|
||||
PARL_RX_DATA7_IDX,
|
||||
},
|
||||
.clk_out_sig = PARL_RX_CLK_OUT_IDX,
|
||||
.clk_in_sig = PARL_RX_CLK_IN_IDX,
|
||||
}
|
||||
}
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/**
|
||||
* PARLIO Registers to be saved during sleep retention
|
||||
* - Tx Configuration registers, e.g.: PARL_IO_TX_DATA_CFG_REG, PARL_IO_TX_GENRL_CFG_REG
|
||||
* - Rx Configuration registers, e.g.: PARL_IO_RX_MODE_CFG_REG, PARL_IO_RX_DATA_CFG_REG, PARL_IO_RX_GENRL_CFG_REG
|
||||
* - CLK Configuration registers, e.g.: PARL_IO_RX_CLK_CFG_REG, PARL_IO_TX_CLK_CFG_REG
|
||||
* - Interrupt enable registers, e.g.: PARL_IO_INT_ENA_REG
|
||||
*/
|
||||
#define PARLIO_RETENTION_REGS_CNT 8
|
||||
#define PARLIO_RETENTION_REGS_BASE (DR_REG_PARL_IO_BASE + 0x0)
|
||||
static const uint32_t parlio_regs_map[4] = {0x60457, 0x0, 0x0, 0x0};
|
||||
static const regdma_entries_config_t parlio_regs_retention[] = {
|
||||
// backup stage: save configuration registers
|
||||
// restore stage: restore the configuration registers
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PARLIO_LINK(0x00), \
|
||||
PARLIO_RETENTION_REGS_BASE, PARLIO_RETENTION_REGS_BASE, \
|
||||
PARLIO_RETENTION_REGS_CNT, 0, 0, \
|
||||
parlio_regs_map[0], parlio_regs_map[1], \
|
||||
parlio_regs_map[2], parlio_regs_map[3]), \
|
||||
.owner = ENTRY(0) | ENTRY(2)
|
||||
}, \
|
||||
};
|
||||
const parlio_reg_retention_info_t parlio_reg_retention_info[SOC_PARLIO_GROUPS] = {
|
||||
[0] = {
|
||||
.regdma_entry_array = parlio_regs_retention,
|
||||
.array_size = ARRAY_SIZE(parlio_regs_retention),
|
||||
.retention_module = SLEEP_RETENTION_MODULE_PARLIO0
|
||||
},
|
||||
};
|
||||
@@ -0,0 +1,690 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// Note that most of the register operations in this layer are non-atomic operations.
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include "hal/assert.h"
|
||||
#include "hal/misc.h"
|
||||
#include "hal/hal_utils.h"
|
||||
#include "soc/pcr_struct.h"
|
||||
#include "soc/parl_io_struct.h"
|
||||
#include "hal/parlio_types.h"
|
||||
|
||||
#define PARLIO_LL_RX_MAX_BYTES_PER_FRAME 0xFFFF
|
||||
#define PARLIO_LL_RX_MAX_CLK_INT_DIV 0x10000
|
||||
#define PARLIO_LL_RX_MAX_CLK_FRACT_DIV 0 // Not support fractional divider
|
||||
#define PARLIO_LL_RX_MAX_TIMEOUT 0xFFFF
|
||||
|
||||
#define PARLIO_LL_TX_MAX_BYTES_PER_FRAME 0xFFFF
|
||||
#define PARLIO_LL_TX_MAX_BITS_PER_FRAME (PARLIO_LL_TX_MAX_BYTES_PER_FRAME * 8)
|
||||
#define PARLIO_LL_TX_MAX_CLK_INT_DIV 0x10000
|
||||
#define PARLIO_LL_TX_MAX_CLK_FRACT_DIV 0 // Not support fractional divider
|
||||
|
||||
#define PARLIO_LL_EVENT_TX_FIFO_EMPTY (1 << 0)
|
||||
#define PARLIO_LL_EVENT_RX_FIFO_FULL (1 << 1)
|
||||
#define PARLIO_LL_EVENT_TX_EOF (1 << 2)
|
||||
#define PARLIO_LL_EVENT_TX_MASK (PARLIO_LL_EVENT_TX_EOF) // On C6, TX FIFO EMPTY event always comes with TX EOF event. We don't enable it
|
||||
#define PARLIO_LL_EVENT_RX_MASK (PARLIO_LL_EVENT_RX_FIFO_FULL)
|
||||
|
||||
#define PARLIO_LL_TX_DATA_LINE_AS_VALID_SIG 15 // TXD[15] can be used a valid signal
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
PARLIO_LL_RX_EOF_COND_RX_FULL, /*!< RX unit generates EOF event when it receives enough data */
|
||||
PARLIO_LL_RX_EOF_COND_EN_INACTIVE, /*!< RX unit generates EOF event when the external enable signal becomes inactive */
|
||||
} parlio_ll_rx_eof_cond_t;
|
||||
|
||||
typedef enum {
|
||||
PARLIO_LL_TX_EOF_COND_DATA_LEN, /*!< TX unit generates EOF event when it transmits particular data bit length that specified in `tx_bitlen`. */
|
||||
PARLIO_LL_TX_EOF_COND_DMA_EOF, /*!< TX unit generates EOF event when the DMA EOF takes place */
|
||||
} parlio_ll_tx_eof_cond_t;
|
||||
|
||||
/**
|
||||
* @brief Enable or disable the parlio peripheral APB clock
|
||||
*
|
||||
* @param group_id The group id of the parlio module
|
||||
* @param enable Set true to enable, false to disable
|
||||
*/
|
||||
static inline void parlio_ll_enable_bus_clock(int group_id, bool enable)
|
||||
{
|
||||
(void)group_id;
|
||||
PCR.parl_io_conf.parl_clk_en = enable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reset the parlio module
|
||||
*
|
||||
* @param group_id The group id of the parlio module
|
||||
*/
|
||||
static inline void parlio_ll_reset_register(int group_id)
|
||||
{
|
||||
(void)group_id;
|
||||
PCR.parl_io_conf.parl_rst_en = 1;
|
||||
PCR.parl_io_conf.parl_rst_en = 0;
|
||||
}
|
||||
|
||||
///////////////////////////////////////RX Unit///////////////////////////////////////
|
||||
|
||||
/**
|
||||
* @brief Set the clock source for the RX unit
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param src Clock source
|
||||
*/
|
||||
static inline void parlio_ll_rx_set_clock_source(parl_io_dev_t *dev, parlio_clock_source_t src)
|
||||
{
|
||||
(void)dev;
|
||||
uint32_t clk_sel = 0;
|
||||
switch (src) {
|
||||
case PARLIO_CLK_SRC_XTAL:
|
||||
clk_sel = 0;
|
||||
break;
|
||||
case PARLIO_CLK_SRC_PLL_F240M:
|
||||
clk_sel = 1;
|
||||
break;
|
||||
case PARLIO_CLK_SRC_RC_FAST:
|
||||
clk_sel = 2;
|
||||
break;
|
||||
case PARLIO_CLK_SRC_EXTERNAL:
|
||||
clk_sel = 3;
|
||||
break;
|
||||
|
||||
default: // unsupported clock source
|
||||
HAL_ASSERT(false);
|
||||
break;
|
||||
}
|
||||
PCR.parl_clk_rx_conf.parl_clk_rx_sel = clk_sel;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the clock divider for the RX unit
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param clk_div Clock division with integral part, no fractional part on C6
|
||||
*/
|
||||
static inline void parlio_ll_rx_set_clock_div(parl_io_dev_t *dev, const hal_utils_clk_div_t *clk_div)
|
||||
{
|
||||
(void)dev;
|
||||
HAL_ASSERT(clk_div->integer > 0 && clk_div->integer <= PARLIO_LL_RX_MAX_CLK_INT_DIV);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.parl_clk_rx_conf, parl_clk_rx_div_num, clk_div->integer - 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reset the RX unit Core clock domain
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_rx_reset_clock(parl_io_dev_t *dev)
|
||||
{
|
||||
(void)dev;
|
||||
PCR.parl_clk_rx_conf.parl_rx_rst_en = 1;
|
||||
PCR.parl_clk_rx_conf.parl_rx_rst_en = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the RX unit Core clock domain
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param en True to enable, False to disable
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_rx_enable_clock(parl_io_dev_t *dev, bool en)
|
||||
{
|
||||
(void)dev;
|
||||
PCR.parl_clk_rx_conf.parl_clk_rx_en = en;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the condition to generate the RX EOF event
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param cond RX EOF condition
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_rx_set_eof_condition(parl_io_dev_t *dev, parlio_ll_rx_eof_cond_t cond)
|
||||
{
|
||||
dev->rx_cfg0.rx_eof_gen_sel = cond;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Start RX unit to sample the input data
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param en True to start, False to stop
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_rx_start(parl_io_dev_t *dev, bool en)
|
||||
{
|
||||
dev->rx_cfg0.rx_start = en;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the receive length
|
||||
*
|
||||
* @note The receive length can be used to generate DMA EOF signal, or to work as a frame end delimiter
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param bitlen Number of bits to receive in the next transaction, bitlen must be a multiple of 8
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_rx_set_recv_bit_len(parl_io_dev_t *dev, uint32_t bitlen)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->rx_cfg0, rx_data_bytelen, bitlen / 8);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the sub mode of the level controlled receive mode
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param active_low_en Level of the external enable signal, true for active low, false for active high
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_rx_set_level_recv_mode(parl_io_dev_t *dev, bool active_low_en)
|
||||
{
|
||||
dev->rx_cfg0.rx_smp_mode_sel = 0;
|
||||
dev->rx_cfg0.rx_level_submode_sel = active_low_en;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the sub mode of the pulse controlled receive mode
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param start_inc Whether the start pulse is counted
|
||||
* @param end_inc Whether the end pulse is counted
|
||||
* @param end_by_len Whether to use the frame length to determine the end of the frame
|
||||
* @param pulse_inv Whether the pulse is inverted
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_rx_set_pulse_recv_mode(parl_io_dev_t *dev, bool start_inc, bool end_inc, bool end_by_len, bool pulse_inv)
|
||||
{
|
||||
uint32_t submode = 0;
|
||||
uint32_t step = 1;
|
||||
if (end_by_len) {
|
||||
submode += 4;
|
||||
} else {
|
||||
step = 2;
|
||||
if (!end_inc) {
|
||||
submode += 1;
|
||||
}
|
||||
}
|
||||
if (!start_inc) {
|
||||
submode += step;
|
||||
}
|
||||
if (pulse_inv) {
|
||||
submode += 6;
|
||||
}
|
||||
dev->rx_cfg0.rx_smp_mode_sel = 1;
|
||||
dev->rx_cfg0.rx_pulse_submode_sel = submode;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the receive mode to software controlled receive mode
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_rx_set_soft_recv_mode(parl_io_dev_t *dev)
|
||||
{
|
||||
dev->rx_cfg0.rx_smp_mode_sel = 2;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Whether to start the software controlled receive mode
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param en True to enable, False to disable
|
||||
*/
|
||||
static inline void parlio_ll_rx_start_soft_recv(parl_io_dev_t *dev, bool en)
|
||||
{
|
||||
dev->rx_cfg0.rx_sw_en = en;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the sample clock edge
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param edge Sample clock edge
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_rx_set_sample_clock_edge(parl_io_dev_t *dev, parlio_sample_edge_t edge)
|
||||
{
|
||||
dev->rx_cfg0.rx_clk_edge_sel = edge;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the order to pack bits into one byte
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param order Packing order
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_rx_set_bit_pack_order(parl_io_dev_t *dev, parlio_bit_pack_order_t order)
|
||||
{
|
||||
dev->rx_cfg0.rx_bit_pack_order = order;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the bus width of the RX unit
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param width Bus width
|
||||
*/
|
||||
static inline void parlio_ll_rx_set_bus_width(parl_io_dev_t *dev, uint32_t width)
|
||||
{
|
||||
uint32_t width_sel = 0;
|
||||
switch (width) {
|
||||
case 16:
|
||||
width_sel = 0;
|
||||
break;
|
||||
case 8:
|
||||
width_sel = 1;
|
||||
break;
|
||||
case 4:
|
||||
width_sel = 2;
|
||||
break;
|
||||
case 2:
|
||||
width_sel = 3;
|
||||
break;
|
||||
case 1:
|
||||
width_sel = 4;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(false);
|
||||
}
|
||||
dev->rx_cfg0.rx_bus_wid_sel = width_sel;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reset RX Async FIFO
|
||||
*
|
||||
* @note During the reset of the asynchronous FIFO, it takes two clock cycles to synchronize within AHB clock domain (GDMA) and Core clock domain.
|
||||
* The reset synchronization must be performed two clock cycles in advance.
|
||||
* @note If the next frame transfer needs to be reset, you need to first switch to the internal free-running clock,
|
||||
* and then switch to the actual clock after the reset is completed.
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_rx_reset_fifo(parl_io_dev_t *dev)
|
||||
{
|
||||
dev->rx_cfg0.rx_fifo_srst = 1;
|
||||
dev->rx_cfg0.rx_fifo_srst = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set which data line as the enable signal
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param line_num Data line number (0-15)
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_rx_treat_data_line_as_en(parl_io_dev_t *dev, uint32_t line_num)
|
||||
{
|
||||
dev->rx_cfg1.rx_ext_en_sel = line_num;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable RX timeout feature
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param en True to enable, False to disable
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_rx_enable_timeout(parl_io_dev_t *dev, bool en)
|
||||
{
|
||||
dev->rx_cfg1.rx_timeout_en = en;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the threshold of RX timeout
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param thres Threshold of RX timeout
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_rx_set_timeout_thres(parl_io_dev_t *dev, uint32_t thres)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->rx_cfg1, rx_timeout_threshold, thres);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update the RX configuration, to make the new configuration take effect
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_rx_update_config(parl_io_dev_t *dev)
|
||||
{
|
||||
dev->rx_cfg1.rx_reg_update = 1;
|
||||
while (dev->rx_cfg1.rx_reg_update);
|
||||
}
|
||||
|
||||
///////////////////////////////////TX Unit///////////////////////////////////////
|
||||
|
||||
/**
|
||||
* @brief Set the clock source for the TX unit
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param src Clock source
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_tx_set_clock_source(parl_io_dev_t *dev, parlio_clock_source_t src)
|
||||
{
|
||||
(void)dev;
|
||||
uint32_t clk_sel = 0;
|
||||
switch (src) {
|
||||
case PARLIO_CLK_SRC_XTAL:
|
||||
clk_sel = 0;
|
||||
break;
|
||||
case PARLIO_CLK_SRC_PLL_F240M:
|
||||
clk_sel = 1;
|
||||
break;
|
||||
case PARLIO_CLK_SRC_RC_FAST:
|
||||
clk_sel = 2;
|
||||
break;
|
||||
case PARLIO_CLK_SRC_EXTERNAL:
|
||||
clk_sel = 3;
|
||||
break;
|
||||
|
||||
default: // unsupported clock source
|
||||
HAL_ASSERT(false);
|
||||
break;
|
||||
}
|
||||
PCR.parl_clk_tx_conf.parl_clk_tx_sel = clk_sel;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the clock divider for the TX unit
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param clk_div Clock division with integral part, no fractional part on C6
|
||||
*/
|
||||
static inline void parlio_ll_tx_set_clock_div(parl_io_dev_t *dev, const hal_utils_clk_div_t *clk_div)
|
||||
{
|
||||
(void)dev;
|
||||
HAL_ASSERT(clk_div->integer > 0 && clk_div->integer <= PARLIO_LL_RX_MAX_CLK_INT_DIV);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.parl_clk_tx_conf, parl_clk_tx_div_num, clk_div->integer - 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reset the TX unit Core clock domain
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_tx_reset_clock(parl_io_dev_t *dev)
|
||||
{
|
||||
(void)dev;
|
||||
PCR.parl_clk_tx_conf.parl_tx_rst_en = 1;
|
||||
PCR.parl_clk_tx_conf.parl_tx_rst_en = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the TX unit Core clock domain
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param en True to enable, False to disable
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_tx_enable_clock(parl_io_dev_t *dev, bool en)
|
||||
{
|
||||
(void)dev;
|
||||
PCR.parl_clk_tx_conf.parl_clk_tx_en = en;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the data length to be transmitted
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param bitlen Data length in bits, must be a multiple of 8
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_tx_set_trans_bit_len(parl_io_dev_t *dev, uint32_t bitlen)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->tx_cfg0, tx_bytelen, bitlen / 8);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the condition to generate the TX EOF event (this chip does not support)
|
||||
*
|
||||
* @param dev Parallel IO register base address (not used)
|
||||
* @param cond TX EOF condition (not used)
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_tx_set_eof_condition(parl_io_dev_t *dev, parlio_ll_tx_eof_cond_t cond)
|
||||
{
|
||||
(void) dev;
|
||||
HAL_ASSERT(cond == PARLIO_LL_TX_EOF_COND_DATA_LEN);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Whether to enable the TX clock gating
|
||||
*
|
||||
* @note The TXD[7] will be taken as the gating enable signal
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param en True to enable, False to disable
|
||||
*/
|
||||
static inline void parlio_ll_tx_enable_clock_gating(parl_io_dev_t *dev, bool en)
|
||||
{
|
||||
dev->tx_cfg0.tx_gating_en = en;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Start TX unit to transmit data
|
||||
*
|
||||
* @note The hardware monitors the rising edge of tx_start as the trigger signal.
|
||||
* Once the transmission starts, it cannot be stopped by clearing tx_start.
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param en True to start, False to reset the reg state (not meaning the TX unit will be stopped)
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_tx_start(parl_io_dev_t *dev, bool en)
|
||||
{
|
||||
dev->tx_cfg0.tx_start = en;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Whether to treat the MSB of TXD as the valid signal
|
||||
*
|
||||
* @note If enabled, TXD[15] will work as valid signal, which stay high during data transmission.
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param en True to enable, False to disable
|
||||
*/
|
||||
static inline void parlio_ll_tx_treat_msb_as_valid(parl_io_dev_t *dev, bool en)
|
||||
{
|
||||
dev->tx_cfg0.tx_hw_valid_en = en;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set TX valid signal delay
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param start_delay Number of clock cycles to delay
|
||||
* @param stop_delay Number of clock cycles to delay
|
||||
* @return true: success, false: valid delay is not supported
|
||||
*/
|
||||
static inline bool parlio_ll_tx_set_valid_delay(parl_io_dev_t *dev, uint32_t start_delay, uint32_t stop_delay)
|
||||
{
|
||||
(void)dev;
|
||||
if (start_delay == 0 && stop_delay == 0) {
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the sample clock edge
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param edge Sample clock edge
|
||||
*/
|
||||
static inline void parlio_ll_tx_set_sample_clock_edge(parl_io_dev_t *dev, parlio_sample_edge_t edge)
|
||||
{
|
||||
dev->tx_cfg0.tx_smp_edge_sel = edge;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the order to unpack bits from a byte
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param order Packing order
|
||||
*/
|
||||
static inline void parlio_ll_tx_set_bit_pack_order(parl_io_dev_t *dev, parlio_bit_pack_order_t order)
|
||||
{
|
||||
dev->tx_cfg0.tx_bit_unpack_order = order;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the bus width of the TX unit
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param width Bus width
|
||||
*/
|
||||
static inline void parlio_ll_tx_set_bus_width(parl_io_dev_t *dev, uint32_t width)
|
||||
{
|
||||
uint32_t width_sel = 0;
|
||||
switch (width) {
|
||||
case 16:
|
||||
width_sel = 0;
|
||||
break;
|
||||
case 8:
|
||||
width_sel = 1;
|
||||
break;
|
||||
case 4:
|
||||
width_sel = 2;
|
||||
break;
|
||||
case 2:
|
||||
width_sel = 3;
|
||||
break;
|
||||
case 1:
|
||||
width_sel = 4;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(false);
|
||||
}
|
||||
dev->tx_cfg0.tx_bus_wid_sel = width_sel;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reset TX Async FIFO
|
||||
*
|
||||
* @note During the reset of the asynchronous FIFO, it takes two clock cycles to synchronize within AHB clock domain (GDMA) and Core clock domain.
|
||||
* The reset synchronization must be performed two clock cycles in advance.
|
||||
* @note If the next frame transfer needs to be reset, you need to first switch to the internal free-running clock,
|
||||
* and then switch to the actual clock after the reset is completed.
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_tx_reset_fifo(parl_io_dev_t *dev)
|
||||
{
|
||||
dev->tx_cfg0.tx_fifo_srst = 1;
|
||||
dev->tx_cfg0.tx_fifo_srst = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the value to output on the TXD when the TX unit is in IDLE state
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param value Value to output
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_tx_set_idle_data_value(parl_io_dev_t *dev, uint32_t value)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->tx_cfg1, tx_idle_value, value);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check whether the TX unit is ready
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @return true: ready, false: busy
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool parlio_ll_tx_is_ready(parl_io_dev_t *dev)
|
||||
{
|
||||
return dev->st.tx_ready;
|
||||
}
|
||||
|
||||
////////////////////////////////////Interrupt////////////////////////////////////////////////
|
||||
|
||||
/**
|
||||
* @brief Enable Parallel IO interrupt for specific event mask
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param mask Event mask
|
||||
* @param enable True to enable, False to disable
|
||||
*/
|
||||
static inline void parlio_ll_enable_interrupt(parl_io_dev_t *dev, uint32_t mask, bool enable)
|
||||
{
|
||||
if (enable) {
|
||||
dev->int_ena.val |= mask;
|
||||
} else {
|
||||
dev->int_ena.val &= ~mask;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get interrupt status for TX unit
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @return Interrupt status
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t parlio_ll_tx_get_interrupt_status(parl_io_dev_t *dev)
|
||||
{
|
||||
return dev->int_st.val & PARLIO_LL_EVENT_TX_MASK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get interrupt status for RX unit
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @return Interrupt status
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t parlio_ll_rx_get_interrupt_status(parl_io_dev_t *dev)
|
||||
{
|
||||
return dev->int_st.val & PARLIO_LL_EVENT_RX_MASK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear Parallel IO interrupt status by mask
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param mask Interrupt status mask
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_clear_interrupt_status(parl_io_dev_t *dev, uint32_t mask)
|
||||
{
|
||||
dev->int_clr.val = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get interrupt status register address
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @return Register address
|
||||
*/
|
||||
static inline volatile void *parlio_ll_get_interrupt_status_reg(parl_io_dev_t *dev)
|
||||
{
|
||||
return &dev->int_st;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,95 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "hal/parlio_periph.h"
|
||||
#include "soc/gpio_sig_map.h"
|
||||
|
||||
const parlio_signal_conn_t parlio_periph_signals = {
|
||||
.groups = {
|
||||
[0] = {
|
||||
.module_name = "PARLIO0",
|
||||
.tx_irq_id = ETS_PARL_IO_INTR_SOURCE,
|
||||
.rx_irq_id = ETS_PARL_IO_INTR_SOURCE,
|
||||
.tx_units = {
|
||||
[0] = {
|
||||
.data_sigs = {
|
||||
PARL_TX_DATA0_IDX,
|
||||
PARL_TX_DATA1_IDX,
|
||||
PARL_TX_DATA2_IDX,
|
||||
PARL_TX_DATA3_IDX,
|
||||
PARL_TX_DATA4_IDX,
|
||||
PARL_TX_DATA5_IDX,
|
||||
PARL_TX_DATA6_IDX,
|
||||
PARL_TX_DATA7_IDX,
|
||||
PARL_TX_DATA8_IDX,
|
||||
PARL_TX_DATA9_IDX,
|
||||
PARL_TX_DATA10_IDX,
|
||||
PARL_TX_DATA11_IDX,
|
||||
PARL_TX_DATA12_IDX,
|
||||
PARL_TX_DATA13_IDX,
|
||||
PARL_TX_DATA14_IDX,
|
||||
PARL_TX_DATA15_IDX,
|
||||
},
|
||||
.clk_out_sig = PARL_TX_CLK_OUT_IDX,
|
||||
.clk_in_sig = PARL_TX_CLK_IN_IDX,
|
||||
.cs_sig = -1,
|
||||
}
|
||||
},
|
||||
.rx_units = {
|
||||
[0] = {
|
||||
.data_sigs = {
|
||||
PARL_RX_DATA0_IDX,
|
||||
PARL_RX_DATA1_IDX,
|
||||
PARL_RX_DATA2_IDX,
|
||||
PARL_RX_DATA3_IDX,
|
||||
PARL_RX_DATA4_IDX,
|
||||
PARL_RX_DATA5_IDX,
|
||||
PARL_RX_DATA6_IDX,
|
||||
PARL_RX_DATA7_IDX,
|
||||
PARL_RX_DATA8_IDX,
|
||||
PARL_RX_DATA9_IDX,
|
||||
PARL_RX_DATA10_IDX,
|
||||
PARL_RX_DATA11_IDX,
|
||||
PARL_RX_DATA12_IDX,
|
||||
PARL_RX_DATA13_IDX,
|
||||
PARL_RX_DATA14_IDX,
|
||||
PARL_RX_DATA15_IDX,
|
||||
},
|
||||
.clk_out_sig = -1,
|
||||
.clk_in_sig = PARL_RX_CLK_IN_IDX,
|
||||
}
|
||||
}
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/**
|
||||
* PARLIO Registers to be saved during sleep retention
|
||||
* - Configuration registers, e.g.: PARL_IO_RX_CFG0_REG, PARL_IO_RX_CFG1_REG, PARL_IO_TX_CFG0_REG, PARL_IO_TX_CFG1_REG, PARL_IO_CLK_REG
|
||||
* - Interrupt enable registers, e.g.: PARL_IO_INT_ENA_REG
|
||||
*/
|
||||
#define PARLIO_RETENTION_REGS_CNT 6
|
||||
#define PARLIO_RETENTION_REGS_BASE (DR_REG_PARL_IO_BASE + 0x0)
|
||||
static const uint32_t parlio_regs_map[4] = {0x2f, 0x0, 0x100, 0x0};
|
||||
static const regdma_entries_config_t parlio_regs_retention[] = {
|
||||
// backup stage: save configuration registers
|
||||
// restore stage: restore the configuration registers
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PARLIO_LINK(0x00), \
|
||||
PARLIO_RETENTION_REGS_BASE, PARLIO_RETENTION_REGS_BASE, \
|
||||
PARLIO_RETENTION_REGS_CNT, 0, 0, \
|
||||
parlio_regs_map[0], parlio_regs_map[1], \
|
||||
parlio_regs_map[2], parlio_regs_map[3]), \
|
||||
.owner = ENTRY(0) | ENTRY(2)
|
||||
}, \
|
||||
};
|
||||
const parlio_reg_retention_info_t parlio_reg_retention_info[SOC_PARLIO_GROUPS] = {
|
||||
[0] = {
|
||||
.regdma_entry_array = parlio_regs_retention,
|
||||
.array_size = ARRAY_SIZE(parlio_regs_retention),
|
||||
.retention_module = SLEEP_RETENTION_MODULE_PARLIO0
|
||||
},
|
||||
};
|
||||
@@ -0,0 +1,721 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// Note that most of the register operations in this layer are non-atomic operations.
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include "hal/assert.h"
|
||||
#include "hal/misc.h"
|
||||
#include "hal/hal_utils.h"
|
||||
#include "hal/efuse_hal.h"
|
||||
#include "soc/chip_revision.h"
|
||||
#include "soc/pcr_struct.h"
|
||||
#include "soc/parl_io_struct.h"
|
||||
#include "hal/parlio_types.h"
|
||||
|
||||
#define PARLIO_LL_RX_MAX_BYTES_PER_FRAME 0xFFFF
|
||||
#define PARLIO_LL_RX_MAX_CLK_INT_DIV 0x10000
|
||||
#define PARLIO_LL_RX_MAX_CLK_FRACT_DIV 0 // Not support fractional divider
|
||||
#define PARLIO_LL_RX_MAX_TIMEOUT 0xFFFF
|
||||
|
||||
#define PARLIO_LL_TX_MAX_BITS_PER_FRAME 0x7FFFF
|
||||
#define PARLIO_LL_TX_MAX_CLK_INT_DIV 0x10000
|
||||
#define PARLIO_LL_TX_MAX_CLK_FRACT_DIV 0 // Not support fractional divider
|
||||
|
||||
#define PARLIO_LL_EVENT_TX_FIFO_EMPTY (1 << 0)
|
||||
#define PARLIO_LL_EVENT_RX_FIFO_FULL (1 << 1)
|
||||
#define PARLIO_LL_EVENT_TX_EOF (1 << 2)
|
||||
#define PARLIO_LL_EVENT_TX_MASK (PARLIO_LL_EVENT_TX_FIFO_EMPTY | PARLIO_LL_EVENT_TX_EOF)
|
||||
#define PARLIO_LL_EVENT_RX_MASK (PARLIO_LL_EVENT_RX_FIFO_FULL)
|
||||
|
||||
#define PARLIO_LL_TX_DATA_LINE_AS_VALID_SIG 7 // TXD[7] can be used a valid signal
|
||||
#define PARLIO_LL_TX_DATA_LINE_AS_CLK_GATE 7 // TXD[7] can be used as clock gate signal
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
PARLIO_LL_RX_EOF_COND_RX_FULL, /*!< RX unit generates EOF event when it receives enough data */
|
||||
PARLIO_LL_RX_EOF_COND_EN_INACTIVE, /*!< RX unit generates EOF event when the external enable signal becomes inactive */
|
||||
} parlio_ll_rx_eof_cond_t;
|
||||
|
||||
typedef enum {
|
||||
PARLIO_LL_TX_EOF_COND_DATA_LEN, /*!< TX unit generates EOF event when it transmits particular data bit length that specified in `tx_bitlen`. */
|
||||
PARLIO_LL_TX_EOF_COND_DMA_EOF, /*!< TX unit generates EOF event when the DMA EOF takes place */
|
||||
} parlio_ll_tx_eof_cond_t;
|
||||
|
||||
/**
|
||||
* @brief Enable or disable the parlio peripheral APB clock
|
||||
*
|
||||
* @param group_id The group id of the parlio module
|
||||
* @param enable Set true to enable, false to disable
|
||||
*/
|
||||
static inline void parlio_ll_enable_bus_clock(int group_id, bool enable)
|
||||
{
|
||||
(void)group_id;
|
||||
PCR.parl_io_conf.parl_clk_en = enable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reset the parlio module
|
||||
*
|
||||
* @param group_id The group id of the parlio module
|
||||
*/
|
||||
static inline void parlio_ll_reset_register(int group_id)
|
||||
{
|
||||
(void)group_id;
|
||||
PCR.parl_io_conf.parl_rst_en = 1;
|
||||
PCR.parl_io_conf.parl_rst_en = 0;
|
||||
}
|
||||
|
||||
///////////////////////////////////////RX Unit///////////////////////////////////////
|
||||
|
||||
/**
|
||||
* @brief Set the clock source for the RX unit
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param src Clock source
|
||||
*/
|
||||
static inline void parlio_ll_rx_set_clock_source(parl_io_dev_t *dev, parlio_clock_source_t src)
|
||||
{
|
||||
(void)dev;
|
||||
uint32_t clk_sel = 0;
|
||||
switch (src) {
|
||||
case PARLIO_CLK_SRC_XTAL:
|
||||
clk_sel = 0;
|
||||
break;
|
||||
case PARLIO_CLK_SRC_PLL_F96M:
|
||||
clk_sel = 1;
|
||||
break;
|
||||
case PARLIO_CLK_SRC_RC_FAST:
|
||||
clk_sel = 2;
|
||||
break;
|
||||
case PARLIO_CLK_SRC_EXTERNAL:
|
||||
clk_sel = 3;
|
||||
break;
|
||||
|
||||
default: // unsupported clock source
|
||||
HAL_ASSERT(false);
|
||||
break;
|
||||
}
|
||||
PCR.parl_clk_rx_conf.parl_clk_rx_sel = clk_sel;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the clock divider for the RX unit
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param clk_div Clock division with integral part, no fractional part on H2
|
||||
*/
|
||||
static inline void parlio_ll_rx_set_clock_div(parl_io_dev_t *dev, const hal_utils_clk_div_t *clk_div)
|
||||
{
|
||||
(void)dev;
|
||||
HAL_ASSERT(clk_div->integer > 0 && clk_div->integer <= PARLIO_LL_RX_MAX_CLK_INT_DIV);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.parl_clk_rx_conf, parl_clk_rx_div_num, clk_div->integer - 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reset the RX unit Core clock domain
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
*/
|
||||
static inline void parlio_ll_rx_reset_clock(parl_io_dev_t *dev)
|
||||
{
|
||||
(void)dev;
|
||||
PCR.parl_clk_rx_conf.parl_rx_rst_en = 1;
|
||||
PCR.parl_clk_rx_conf.parl_rx_rst_en = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the RX unit Core clock domain
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param en True to enable, False to disable
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_rx_enable_clock(parl_io_dev_t *dev, bool en)
|
||||
{
|
||||
(void)dev;
|
||||
PCR.parl_clk_rx_conf.parl_clk_rx_en = en;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the condition to generate the RX EOF event
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param cond RX EOF condition
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_rx_set_eof_condition(parl_io_dev_t *dev, parlio_ll_rx_eof_cond_t cond)
|
||||
{
|
||||
dev->rx_genrl_cfg.rx_eof_gen_sel = cond;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Start RX unit to sample the input data
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param en True to start, False to stop
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_rx_start(parl_io_dev_t *dev, bool en)
|
||||
{
|
||||
dev->rx_start_cfg.rx_start = en;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the receive length
|
||||
*
|
||||
* @note The receive length can be used to generate DMA EOF signal, or to work as a frame end delimiter
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param bitlen Number of bits to receive in the next transaction, bitlen must be a multiple of 8
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_rx_set_recv_bit_len(parl_io_dev_t *dev, uint32_t bitlen)
|
||||
{
|
||||
dev->rx_data_cfg.rx_bitlen = bitlen;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the sub mode of the level controlled receive mode
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param active_low_en Level of the external enable signal, true for active low, false for active high
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_rx_set_level_recv_mode(parl_io_dev_t *dev, bool active_low_en)
|
||||
{
|
||||
dev->rx_mode_cfg.rx_smp_mode_sel = 0;
|
||||
dev->rx_mode_cfg.rx_ext_en_inv = active_low_en;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the sub mode of the pulse controlled receive mode
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param start_inc Whether the start pulse is counted
|
||||
* @param end_inc Whether the end pulse is counted
|
||||
* @param end_by_len Whether to use the frame length to determine the end of the frame
|
||||
* @param pulse_inv Whether the pulse is inverted
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_rx_set_pulse_recv_mode(parl_io_dev_t *dev, bool start_inc, bool end_inc, bool end_by_len, bool pulse_inv)
|
||||
{
|
||||
uint32_t submode = 0;
|
||||
uint32_t step = 1;
|
||||
if (end_by_len) {
|
||||
submode += 4;
|
||||
} else { // end by pulse
|
||||
step = 2;
|
||||
if (!end_inc) {
|
||||
submode += 1;
|
||||
}
|
||||
}
|
||||
if (!start_inc) {
|
||||
submode += step;
|
||||
}
|
||||
dev->rx_mode_cfg.rx_smp_mode_sel = 1;
|
||||
dev->rx_mode_cfg.rx_pulse_submode_sel = submode;
|
||||
dev->rx_mode_cfg.rx_ext_en_inv = pulse_inv;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the receive mode to software controlled receive mode
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_rx_set_soft_recv_mode(parl_io_dev_t *dev)
|
||||
{
|
||||
dev->rx_mode_cfg.rx_smp_mode_sel = 2;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Whether to start the software controlled receive mode
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param en True to enable, False to disable
|
||||
*/
|
||||
static inline void parlio_ll_rx_start_soft_recv(parl_io_dev_t *dev, bool en)
|
||||
{
|
||||
dev->rx_mode_cfg.rx_sw_en = en;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the sample clock edge
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param edge Sample clock edge
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_rx_set_sample_clock_edge(parl_io_dev_t *dev, parlio_sample_edge_t edge)
|
||||
{
|
||||
dev->rx_clk_cfg.rx_clk_i_inv = edge;
|
||||
dev->rx_clk_cfg.rx_clk_o_inv = edge;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the order to pack bits into one byte
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param order Packing order
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_rx_set_bit_pack_order(parl_io_dev_t *dev, parlio_bit_pack_order_t order)
|
||||
{
|
||||
dev->rx_data_cfg.rx_data_order_inv = order;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the bus width of the RX unit
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param width Bus width
|
||||
*/
|
||||
static inline void parlio_ll_rx_set_bus_width(parl_io_dev_t *dev, uint32_t width)
|
||||
{
|
||||
uint32_t width_sel = 0;
|
||||
switch (width) {
|
||||
case 8:
|
||||
width_sel = 3;
|
||||
break;
|
||||
case 4:
|
||||
width_sel = 2;
|
||||
break;
|
||||
case 2:
|
||||
width_sel = 1;
|
||||
break;
|
||||
case 1:
|
||||
width_sel = 0;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(false);
|
||||
}
|
||||
dev->rx_data_cfg.rx_bus_wid_sel = width_sel;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reset RX Async FIFO
|
||||
*
|
||||
* @note During the reset of the asynchronous FIFO, it takes two clock cycles to synchronize within AHB clock domain (GDMA) and Core clock domain.
|
||||
* The reset synchronization must be performed two clock cycles in advance.
|
||||
* @note If the next frame transfer needs to be reset, you need to first switch to the internal free-running clock,
|
||||
* and then switch to the actual clock after the reset is completed.
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
*/
|
||||
static inline void parlio_ll_rx_reset_fifo(parl_io_dev_t *dev)
|
||||
{
|
||||
dev->fifo_cfg.rx_fifo_srst = 1;
|
||||
dev->fifo_cfg.rx_fifo_srst = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set which data line as the enable signal
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param line_num Data line number (0-15)
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_rx_treat_data_line_as_en(parl_io_dev_t *dev, uint32_t line_num)
|
||||
{
|
||||
dev->rx_mode_cfg.rx_ext_en_sel = line_num;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Whether to enable the RX clock gating
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param en True to enable, False to disable
|
||||
*/
|
||||
static inline void parlio_ll_rx_enable_clock_gating(parl_io_dev_t *dev, bool en)
|
||||
{
|
||||
dev->rx_genrl_cfg.rx_gating_en = en;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable RX timeout feature
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param en True to enable, False to disable
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_rx_enable_timeout(parl_io_dev_t *dev, bool en)
|
||||
{
|
||||
dev->rx_genrl_cfg.rx_timeout_en = en;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the threshold of RX timeout
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param thres Threshold of RX timeout
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_rx_set_timeout_thres(parl_io_dev_t *dev, uint32_t thres)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->rx_genrl_cfg, rx_timeout_thres, thres);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update the RX configuration, to make the new configuration take effect
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_rx_update_config(parl_io_dev_t *dev)
|
||||
{
|
||||
dev->reg_update.rx_reg_update = 1;
|
||||
while (dev->reg_update.rx_reg_update);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the RX fifo cycle count
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @return
|
||||
* - RX fifo cycle count
|
||||
*/
|
||||
static inline uint32_t parlio_ll_rx_get_fifo_cycle_cnt(parl_io_dev_t *dev)
|
||||
{
|
||||
if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 102)) {
|
||||
return dev->rx_st0.rx_cnt;
|
||||
}
|
||||
/* For the H2 chip revision that smaller than v1.2, only the highest 4-bit are effective,
|
||||
* need to right shift 1 bit to get the actual count */
|
||||
return dev->rx_st0.rx_cnt >> 1;
|
||||
}
|
||||
///////////////////////////////////TX Unit///////////////////////////////////////
|
||||
|
||||
/**
|
||||
* @brief Set the clock source for the TX unit
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param src Clock source
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_tx_set_clock_source(parl_io_dev_t *dev, parlio_clock_source_t src)
|
||||
{
|
||||
(void)dev;
|
||||
uint32_t clk_sel = 0;
|
||||
switch (src) {
|
||||
case PARLIO_CLK_SRC_XTAL:
|
||||
clk_sel = 0;
|
||||
break;
|
||||
case PARLIO_CLK_SRC_PLL_F96M:
|
||||
clk_sel = 1;
|
||||
break;
|
||||
case PARLIO_CLK_SRC_RC_FAST:
|
||||
clk_sel = 2;
|
||||
break;
|
||||
case PARLIO_CLK_SRC_EXTERNAL:
|
||||
clk_sel = 3;
|
||||
break;
|
||||
|
||||
default: // unsupported clock source
|
||||
HAL_ASSERT(false);
|
||||
break;
|
||||
}
|
||||
PCR.parl_clk_tx_conf.parl_clk_tx_sel = clk_sel;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the clock divider for the TX unit
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param clk_div Clock division with integral part, no fractional part on H2
|
||||
*/
|
||||
static inline void parlio_ll_tx_set_clock_div(parl_io_dev_t *dev, const hal_utils_clk_div_t *clk_div)
|
||||
{
|
||||
(void)dev;
|
||||
HAL_ASSERT(clk_div->integer > 0 && clk_div->integer <= PARLIO_LL_RX_MAX_CLK_INT_DIV);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.parl_clk_tx_conf, parl_clk_tx_div_num, clk_div->integer - 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reset the TX unit Core clock domain
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_tx_reset_clock(parl_io_dev_t *dev)
|
||||
{
|
||||
(void)dev;
|
||||
PCR.parl_clk_tx_conf.parl_tx_rst_en = 1;
|
||||
PCR.parl_clk_tx_conf.parl_tx_rst_en = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the TX unit Core clock domain
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param en True to enable, False to disable
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_tx_enable_clock(parl_io_dev_t *dev, bool en)
|
||||
{
|
||||
(void)dev;
|
||||
PCR.parl_clk_tx_conf.parl_clk_tx_en = en;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the data length to be transmitted
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param bitlen Data length in bits, must be a multiple of 8
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_tx_set_trans_bit_len(parl_io_dev_t *dev, uint32_t bitlen)
|
||||
{
|
||||
dev->tx_data_cfg.tx_bitlen = bitlen;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if tx size can be determined by DMA
|
||||
*
|
||||
* @param dev Parallel IO register base address (not used)
|
||||
*/
|
||||
static inline bool parlio_ll_tx_support_dma_eof(parl_io_dev_t *dev)
|
||||
{
|
||||
(void)dev;
|
||||
return ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 102);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the condition to generate the TX EOF event
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param cond TX EOF condition
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_tx_set_eof_condition(parl_io_dev_t *dev, parlio_ll_tx_eof_cond_t cond)
|
||||
{
|
||||
dev->tx_genrl_cfg.tx_eof_gen_sel = cond;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Whether to enable the TX clock gating
|
||||
*
|
||||
* @note The MSB of TXD will be taken as the gating enable signal
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param en True to enable, False to disable
|
||||
*/
|
||||
static inline void parlio_ll_tx_enable_clock_gating(parl_io_dev_t *dev, bool en)
|
||||
{
|
||||
dev->tx_genrl_cfg.tx_gating_en = en;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Start TX unit to transmit data
|
||||
*
|
||||
* @note The hardware monitors the rising edge of tx_start as the trigger signal.
|
||||
* Once the transmission starts, it cannot be stopped by clearing tx_start.
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param en True to start, False to reset the reg state (not meaning the TX unit will be stopped)
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_tx_start(parl_io_dev_t *dev, bool en)
|
||||
{
|
||||
dev->tx_start_cfg.tx_start = en;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Whether to treat the MSB of TXD as the valid signal
|
||||
*
|
||||
* @note If enabled, TXD[7] will work as valid signal, which stay high during data transmission.
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param en True to enable, False to disable
|
||||
*/
|
||||
static inline void parlio_ll_tx_treat_msb_as_valid(parl_io_dev_t *dev, bool en)
|
||||
{
|
||||
dev->tx_genrl_cfg.tx_valid_output_en = en;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set TX valid signal delay
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param start_delay Number of clock cycles to delay
|
||||
* @param stop_delay Number of clock cycles to delay
|
||||
* @return true: success, false: valid delay is not supported
|
||||
*/
|
||||
static inline bool parlio_ll_tx_set_valid_delay(parl_io_dev_t *dev, uint32_t start_delay, uint32_t stop_delay)
|
||||
{
|
||||
(void)dev;
|
||||
if (start_delay == 0 && stop_delay == 0) {
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the sample clock edge
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param edge Sample clock edge
|
||||
*/
|
||||
static inline void parlio_ll_tx_set_sample_clock_edge(parl_io_dev_t *dev, parlio_sample_edge_t edge)
|
||||
{
|
||||
dev->tx_clk_cfg.tx_clk_i_inv = edge;
|
||||
dev->tx_clk_cfg.tx_clk_o_inv = edge;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the order to unpack bits from a byte
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param order Packing order
|
||||
*/
|
||||
static inline void parlio_ll_tx_set_bit_pack_order(parl_io_dev_t *dev, parlio_bit_pack_order_t order)
|
||||
{
|
||||
dev->tx_data_cfg.tx_data_order_inv = order;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the bus width of the TX unit
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param width Bus width
|
||||
*/
|
||||
static inline void parlio_ll_tx_set_bus_width(parl_io_dev_t *dev, uint32_t width)
|
||||
{
|
||||
uint32_t width_sel = 0;
|
||||
switch (width) {
|
||||
case 8:
|
||||
width_sel = 3;
|
||||
break;
|
||||
case 4:
|
||||
width_sel = 2;
|
||||
break;
|
||||
case 2:
|
||||
width_sel = 1;
|
||||
break;
|
||||
case 1:
|
||||
width_sel = 0;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(false);
|
||||
}
|
||||
dev->tx_data_cfg.tx_bus_wid_sel = width_sel;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reset TX Async FIFO
|
||||
*
|
||||
* @note During the reset of the asynchronous FIFO, it takes two clock cycles to synchronize within AHB clock domain (GDMA) and Core clock domain.
|
||||
* The reset synchronization must be performed two clock cycles in advance.
|
||||
* @note If the next frame transfer needs to be reset, you need to first switch to the internal free-running clock,
|
||||
* and then switch to the actual clock after the reset is completed.
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_tx_reset_fifo(parl_io_dev_t *dev)
|
||||
{
|
||||
dev->fifo_cfg.tx_fifo_srst = 1;
|
||||
dev->fifo_cfg.tx_fifo_srst = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the value to output on the TXD when the TX unit is in IDLE state
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param value Value to output
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_tx_set_idle_data_value(parl_io_dev_t *dev, uint32_t value)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->tx_genrl_cfg, tx_idle_value, value);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check whether the TX unit is ready
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @return true: ready, false: busy
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool parlio_ll_tx_is_ready(parl_io_dev_t *dev)
|
||||
{
|
||||
return dev->st.tx_ready;
|
||||
}
|
||||
|
||||
////////////////////////////////////Interrupt////////////////////////////////////////////////
|
||||
|
||||
/**
|
||||
* @brief Enable Parallel IO interrupt for specific event mask
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param mask Event mask
|
||||
* @param enable True to enable, False to disable
|
||||
*/
|
||||
static inline void parlio_ll_enable_interrupt(parl_io_dev_t *dev, uint32_t mask, bool enable)
|
||||
{
|
||||
if (enable) {
|
||||
dev->int_ena.val |= mask;
|
||||
} else {
|
||||
dev->int_ena.val &= ~mask;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get interrupt status for TX unit
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @return Interrupt status
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t parlio_ll_tx_get_interrupt_status(parl_io_dev_t *dev)
|
||||
{
|
||||
return dev->int_st.val & PARLIO_LL_EVENT_TX_MASK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get interrupt status for RX unit
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @return Interrupt status
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t parlio_ll_rx_get_interrupt_status(parl_io_dev_t *dev)
|
||||
{
|
||||
return dev->int_st.val & PARLIO_LL_EVENT_RX_MASK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear Parallel IO interrupt status by mask
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param mask Interrupt status mask
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_clear_interrupt_status(parl_io_dev_t *dev, uint32_t mask)
|
||||
{
|
||||
dev->int_clr.val = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get interrupt status register address
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @return Register address
|
||||
*/
|
||||
static inline volatile void *parlio_ll_get_interrupt_status_reg(parl_io_dev_t *dev)
|
||||
{
|
||||
return &dev->int_st;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,81 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "hal/parlio_periph.h"
|
||||
#include "soc/gpio_sig_map.h"
|
||||
|
||||
const parlio_signal_conn_t parlio_periph_signals = {
|
||||
.groups = {
|
||||
[0] = {
|
||||
.module_name = "PARLIO0",
|
||||
.tx_irq_id = ETS_PARL_IO_TX_INTR_SOURCE,
|
||||
.rx_irq_id = ETS_PARL_IO_RX_INTR_SOURCE,
|
||||
.tx_units = {
|
||||
[0] = {
|
||||
.data_sigs = {
|
||||
PARL_TX_DATA0_IDX,
|
||||
PARL_TX_DATA1_IDX,
|
||||
PARL_TX_DATA2_IDX,
|
||||
PARL_TX_DATA3_IDX,
|
||||
PARL_TX_DATA4_IDX,
|
||||
PARL_TX_DATA5_IDX,
|
||||
PARL_TX_DATA6_IDX,
|
||||
PARL_TX_DATA7_IDX,
|
||||
},
|
||||
.clk_out_sig = PARL_TX_CLK_OUT_IDX,
|
||||
.clk_in_sig = PARL_TX_CLK_IN_IDX,
|
||||
.cs_sig = -1,
|
||||
}
|
||||
},
|
||||
.rx_units = {
|
||||
[0] = {
|
||||
.data_sigs = {
|
||||
PARL_RX_DATA0_IDX,
|
||||
PARL_RX_DATA1_IDX,
|
||||
PARL_RX_DATA2_IDX,
|
||||
PARL_RX_DATA3_IDX,
|
||||
PARL_RX_DATA4_IDX,
|
||||
PARL_RX_DATA5_IDX,
|
||||
PARL_RX_DATA6_IDX,
|
||||
PARL_RX_DATA7_IDX,
|
||||
},
|
||||
.clk_out_sig = PARL_RX_CLK_OUT_IDX,
|
||||
.clk_in_sig = PARL_RX_CLK_IN_IDX,
|
||||
}
|
||||
}
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/**
|
||||
* PARLIO Registers to be saved during sleep retention
|
||||
* - Tx Configuration registers, e.g.: PARL_IO_TX_DATA_CFG_REG, PARL_IO_TX_GENRL_CFG_REG
|
||||
* - Rx Configuration registers, e.g.: PARL_IO_RX_MODE_CFG_REG, PARL_IO_RX_DATA_CFG_REG, PARL_IO_RX_GENRL_CFG_REG
|
||||
* - CLK Configuration registers, e.g.: PARL_IO_RX_CLK_CFG_REG, PARL_IO_TX_CLK_CFG_REG
|
||||
* - Interrupt enable registers, e.g.: PARL_IO_INT_ENA_REG
|
||||
*/
|
||||
#define PARLIO_RETENTION_REGS_CNT 8
|
||||
#define PARLIO_RETENTION_REGS_BASE (DR_REG_PARL_IO_BASE + 0x0)
|
||||
static const uint32_t parlio_regs_map[4] = {0x60457, 0x0, 0x0, 0x0};
|
||||
static const regdma_entries_config_t parlio_regs_retention[] = {
|
||||
// backup stage: save configuration registers
|
||||
// restore stage: restore the configuration registers
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PARLIO_LINK(0x00), \
|
||||
PARLIO_RETENTION_REGS_BASE, PARLIO_RETENTION_REGS_BASE, \
|
||||
PARLIO_RETENTION_REGS_CNT, 0, 0, \
|
||||
parlio_regs_map[0], parlio_regs_map[1], \
|
||||
parlio_regs_map[2], parlio_regs_map[3]), \
|
||||
.owner = ENTRY(0) | ENTRY(2)
|
||||
}, \
|
||||
};
|
||||
const parlio_reg_retention_info_t parlio_reg_retention_info[SOC_PARLIO_GROUPS] = {
|
||||
[0] = {
|
||||
.regdma_entry_array = parlio_regs_retention,
|
||||
.array_size = ARRAY_SIZE(parlio_regs_retention),
|
||||
.retention_module = SLEEP_RETENTION_MODULE_PARLIO0
|
||||
},
|
||||
};
|
||||
@@ -0,0 +1,834 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// Note that most of the register operations in this layer are non-atomic operations.
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include "hal/assert.h"
|
||||
#include "hal/misc.h"
|
||||
#include "hal/parlio_types.h"
|
||||
#include "hal/hal_utils.h"
|
||||
#include "hal/config.h"
|
||||
#include "soc/hp_sys_clkrst_struct.h"
|
||||
#include "soc/lp_clkrst_struct.h"
|
||||
#include "soc/parl_io_struct.h"
|
||||
|
||||
#define PARLIO_LL_RX_MAX_BYTES_PER_FRAME 0xFFFF
|
||||
#define PARLIO_LL_RX_MAX_CLK_INT_DIV 0x100
|
||||
#define PARLIO_LL_RX_MAX_CLK_FRACT_DIV 0x100
|
||||
#define PARLIO_LL_RX_MAX_TIMEOUT 0xFFFF
|
||||
|
||||
#define PARLIO_LL_TX_MAX_BITS_PER_FRAME 0x7FFFF
|
||||
#define PARLIO_LL_TX_MAX_CLK_INT_DIV 0x100
|
||||
#define PARLIO_LL_TX_MAX_CLK_FRACT_DIV 0x100
|
||||
|
||||
#define PARLIO_LL_EVENT_TX_FIFO_EMPTY (1 << 0)
|
||||
#define PARLIO_LL_EVENT_RX_FIFO_FULL (1 << 1)
|
||||
#define PARLIO_LL_EVENT_TX_EOF (1 << 2)
|
||||
#define PARLIO_LL_EVENT_TX_MASK (PARLIO_LL_EVENT_TX_FIFO_EMPTY | PARLIO_LL_EVENT_TX_EOF)
|
||||
#define PARLIO_LL_EVENT_RX_MASK (PARLIO_LL_EVENT_RX_FIFO_FULL)
|
||||
|
||||
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) < 300
|
||||
#define PARLIO_LL_TX_DATA_LINE_AS_VALID_SIG 15 // TXD[15] can be used a valid signal
|
||||
#endif
|
||||
|
||||
#define PARLIO_LL_TX_DATA_LINE_AS_CLK_GATE 15 // TXD[15] can be used as clock gate signal
|
||||
|
||||
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
|
||||
#define PARLIO_LL_TX_VALID_MAX_DELAY 32767
|
||||
#define PARLIO_LL_SUPPORT_TX_EOF_FROM_DMA 1 // Support to treat DMA EOF as TX unit EOF
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
PARLIO_LL_RX_EOF_COND_RX_FULL, /*!< RX unit generates EOF event when it receives enough data */
|
||||
PARLIO_LL_RX_EOF_COND_EN_INACTIVE, /*!< RX unit generates EOF event when the external enable signal becomes inactive */
|
||||
} parlio_ll_rx_eof_cond_t;
|
||||
|
||||
typedef enum {
|
||||
PARLIO_LL_TX_EOF_COND_DATA_LEN, /*!< TX unit generates EOF event when it transmits particular data bit length that specified in `tx_bitlen`. */
|
||||
PARLIO_LL_TX_EOF_COND_DMA_EOF, /*!< TX unit generates EOF event when the DMA EOF takes place */
|
||||
} parlio_ll_tx_eof_cond_t;
|
||||
|
||||
/**
|
||||
* @brief Enable or disable the parlio peripheral APB clock
|
||||
*
|
||||
* @param group_id The group id of the parlio module
|
||||
* @param enable Set true to enable, false to disable
|
||||
*/
|
||||
static inline void _parlio_ll_enable_bus_clock(int group_id, bool enable)
|
||||
{
|
||||
(void)group_id;
|
||||
HP_SYS_CLKRST.soc_clk_ctrl1.reg_parlio_sys_clk_en = enable;
|
||||
HP_SYS_CLKRST.soc_clk_ctrl2.reg_parlio_apb_clk_en = enable;
|
||||
}
|
||||
|
||||
/// use a macro to wrap the function, force the caller to use it in a critical section
|
||||
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
|
||||
#define parlio_ll_enable_bus_clock(...) do { \
|
||||
(void)__DECLARE_RCC_ATOMIC_ENV; \
|
||||
_parlio_ll_enable_bus_clock(__VA_ARGS__); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Reset the parlio module
|
||||
*
|
||||
* @param group_id The group id of the parlio module
|
||||
*/
|
||||
static inline void _parlio_ll_reset_register(int group_id)
|
||||
{
|
||||
(void)group_id;
|
||||
HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_parlio = 1;
|
||||
HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_parlio = 0;
|
||||
}
|
||||
|
||||
/// use a macro to wrap the function, force the caller to use it in a critical section
|
||||
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
|
||||
#define parlio_ll_reset_register(...) do { \
|
||||
(void)__DECLARE_RCC_ATOMIC_ENV; \
|
||||
_parlio_ll_reset_register(__VA_ARGS__); \
|
||||
} while(0)
|
||||
|
||||
///////////////////////////////////////RX Unit///////////////////////////////////////
|
||||
|
||||
/**
|
||||
* @brief Set the clock source for the RX unit
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param src Clock source
|
||||
*/
|
||||
static inline void _parlio_ll_rx_set_clock_source(parl_io_dev_t *dev, parlio_clock_source_t src)
|
||||
{
|
||||
(void)dev;
|
||||
uint32_t clk_sel = 0;
|
||||
switch (src) {
|
||||
case PARLIO_CLK_SRC_XTAL:
|
||||
clk_sel = 0;
|
||||
break;
|
||||
case PARLIO_CLK_SRC_RC_FAST:
|
||||
clk_sel = 1;
|
||||
break;
|
||||
case PARLIO_CLK_SRC_PLL_F160M:
|
||||
clk_sel = 2;
|
||||
break;
|
||||
case PARLIO_CLK_SRC_EXTERNAL:
|
||||
clk_sel = 3;
|
||||
break;
|
||||
|
||||
default: // unsupported clock source
|
||||
HAL_ASSERT(false);
|
||||
break;
|
||||
}
|
||||
HP_SYS_CLKRST.peri_clk_ctrl117.reg_parlio_rx_clk_src_sel = clk_sel;
|
||||
}
|
||||
|
||||
/// use a macro to wrap the function, force the caller to use it in a critical section
|
||||
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
|
||||
#define parlio_ll_rx_set_clock_source(...) do { \
|
||||
(void)__DECLARE_RCC_ATOMIC_ENV; \
|
||||
_parlio_ll_rx_set_clock_source(__VA_ARGS__); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Set the clock divider for the RX unit
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param clk_div Clock division with integral and decimal part
|
||||
*/
|
||||
static inline void _parlio_ll_rx_set_clock_div(parl_io_dev_t *dev, const hal_utils_clk_div_t *clk_div)
|
||||
{
|
||||
(void)dev;
|
||||
HAL_ASSERT(clk_div->integer > 0 && clk_div->integer <= PARLIO_LL_RX_MAX_CLK_INT_DIV);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl117, reg_parlio_rx_clk_div_num, clk_div->integer - 1);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl118, reg_parlio_rx_clk_div_denominator, clk_div->denominator);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl118, reg_parlio_rx_clk_div_numerator, clk_div->numerator);
|
||||
}
|
||||
|
||||
/// use a macro to wrap the function, force the caller to use it in a critical section
|
||||
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
|
||||
#define parlio_ll_rx_set_clock_div(...) do { \
|
||||
(void)__DECLARE_RCC_ATOMIC_ENV; \
|
||||
_parlio_ll_rx_set_clock_div(__VA_ARGS__); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Reset the RX unit Core clock domain
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
*/
|
||||
static inline void _parlio_ll_rx_reset_clock(parl_io_dev_t *dev)
|
||||
{
|
||||
(void)dev;
|
||||
HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_parlio_rx = 1;
|
||||
HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_parlio_rx = 0;
|
||||
}
|
||||
|
||||
/// use a macro to wrap the function, force the caller to use it in a critical section
|
||||
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
|
||||
#define parlio_ll_rx_reset_clock(...) do { \
|
||||
(void)__DECLARE_RCC_ATOMIC_ENV; \
|
||||
_parlio_ll_rx_reset_clock(__VA_ARGS__); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Enable the RX unit Core clock domain
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param en True to enable, False to disable
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void _parlio_ll_rx_enable_clock(parl_io_dev_t *dev, bool en)
|
||||
{
|
||||
(void)dev;
|
||||
LP_AON_CLKRST.hp_clk_ctrl.hp_pad_parlio_rx_clk_en = en;
|
||||
HP_SYS_CLKRST.peri_clk_ctrl117.reg_parlio_rx_clk_en = en;
|
||||
}
|
||||
|
||||
/// use a macro to wrap the function, force the caller to use it in a critical section
|
||||
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
|
||||
#define parlio_ll_rx_enable_clock(...) do { \
|
||||
(void)__DECLARE_RCC_ATOMIC_ENV; \
|
||||
_parlio_ll_rx_enable_clock(__VA_ARGS__); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Set the condition to generate the RX EOF event
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param cond RX EOF condition
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_rx_set_eof_condition(parl_io_dev_t *dev, parlio_ll_rx_eof_cond_t cond)
|
||||
{
|
||||
dev->rx_genrl_cfg.rx_eof_gen_sel = cond;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Start RX unit to sample the input data
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param en True to start, False to stop
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_rx_start(parl_io_dev_t *dev, bool en)
|
||||
{
|
||||
dev->rx_start_cfg.rx_start = en;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the receive length
|
||||
*
|
||||
* @note The receive length can be used to generate DMA EOF signal, or to work as a frame end delimiter
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param bitlen Number of bits to receive in the next transaction, bitlen must be a multiple of 8
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_rx_set_recv_bit_len(parl_io_dev_t *dev, uint32_t bitlen)
|
||||
{
|
||||
dev->rx_data_cfg.rx_bitlen = bitlen;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the sub mode of the level controlled receive mode
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param active_low_en Level of the external enable signal, true for active low, false for active high
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_rx_set_level_recv_mode(parl_io_dev_t *dev, bool active_low_en)
|
||||
{
|
||||
dev->rx_mode_cfg.rx_smp_mode_sel = 0;
|
||||
dev->rx_mode_cfg.rx_ext_en_inv = active_low_en;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the sub mode of the pulse controlled receive mode
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param start_inc Whether the start pulse is counted
|
||||
* @param end_inc Whether the end pulse is counted
|
||||
* @param end_by_len Whether to use the frame length to determine the end of the frame
|
||||
* @param pulse_inv Whether the pulse is inverted
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_rx_set_pulse_recv_mode(parl_io_dev_t *dev, bool start_inc, bool end_inc, bool end_by_len, bool pulse_inv)
|
||||
{
|
||||
uint32_t submode = 0;
|
||||
uint32_t step = 1;
|
||||
if (end_by_len) {
|
||||
submode += 4;
|
||||
} else { // end by pulse
|
||||
step = 2;
|
||||
if (!end_inc) {
|
||||
submode += 1;
|
||||
}
|
||||
}
|
||||
if (!start_inc) {
|
||||
submode += step;
|
||||
}
|
||||
dev->rx_mode_cfg.rx_smp_mode_sel = 1;
|
||||
dev->rx_mode_cfg.rx_pulse_submode_sel = submode;
|
||||
dev->rx_mode_cfg.rx_ext_en_inv = pulse_inv;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the receive mode to software controlled receive mode
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_rx_set_soft_recv_mode(parl_io_dev_t *dev)
|
||||
{
|
||||
dev->rx_mode_cfg.rx_smp_mode_sel = 2;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Whether to start the software controlled receive mode
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param en True to enable, False to disable
|
||||
*/
|
||||
static inline void parlio_ll_rx_start_soft_recv(parl_io_dev_t *dev, bool en)
|
||||
{
|
||||
dev->rx_mode_cfg.rx_sw_en = en;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the sample clock edge
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param edge Sample clock edge
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_rx_set_sample_clock_edge(parl_io_dev_t *dev, parlio_sample_edge_t edge)
|
||||
{
|
||||
dev->rx_clk_cfg.rx_clk_i_inv = edge;
|
||||
dev->rx_clk_cfg.rx_clk_o_inv = edge;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the order to pack bits into one byte
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param order Packing order
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_rx_set_bit_pack_order(parl_io_dev_t *dev, parlio_bit_pack_order_t order)
|
||||
{
|
||||
dev->rx_data_cfg.rx_data_order_inv = order;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the bus width of the RX unit
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param width Bus width
|
||||
*/
|
||||
static inline void parlio_ll_rx_set_bus_width(parl_io_dev_t *dev, uint32_t width)
|
||||
{
|
||||
uint32_t width_sel = 0;
|
||||
switch (width) {
|
||||
case 16:
|
||||
width_sel = 4;
|
||||
break;
|
||||
case 8:
|
||||
width_sel = 3;
|
||||
break;
|
||||
case 4:
|
||||
width_sel = 2;
|
||||
break;
|
||||
case 2:
|
||||
width_sel = 1;
|
||||
break;
|
||||
case 1:
|
||||
width_sel = 0;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(false);
|
||||
}
|
||||
dev->rx_data_cfg.rx_bus_wid_sel = width_sel;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reset RX Async FIFO
|
||||
*
|
||||
* @note During the reset of the asynchronous FIFO, it takes two clock cycles to synchronize within AHB clock domain (GDMA) and Core clock domain.
|
||||
* The reset synchronization must be performed two clock cycles in advance.
|
||||
* @note If the next frame transfer needs to be reset, you need to first switch to the internal free-running clock,
|
||||
* and then switch to the actual clock after the reset is completed.
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
*/
|
||||
static inline void parlio_ll_rx_reset_fifo(parl_io_dev_t *dev)
|
||||
{
|
||||
dev->fifo_cfg.rx_fifo_srst = 1;
|
||||
dev->fifo_cfg.rx_fifo_srst = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set which data line as the enable signal
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param line_num Data line number (0-15)
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_rx_treat_data_line_as_en(parl_io_dev_t *dev, uint32_t line_num)
|
||||
{
|
||||
dev->rx_mode_cfg.rx_ext_en_sel = line_num;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief whether to enable the RX clock gating
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param en True to enable, False to disable
|
||||
*/
|
||||
static inline void parlio_ll_rx_enable_clock_gating(parl_io_dev_t *dev, bool en)
|
||||
{
|
||||
dev->rx_genrl_cfg.rx_gating_en = en;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable RX timeout feature
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param en True to enable, False to disable
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_rx_enable_timeout(parl_io_dev_t *dev, bool en)
|
||||
{
|
||||
dev->rx_genrl_cfg.rx_timeout_en = en;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the threshold of RX timeout
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param thres Threshold of RX timeout
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_rx_set_timeout_thres(parl_io_dev_t *dev, uint32_t thres)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->rx_genrl_cfg, rx_timeout_thres, thres);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update the RX configuration, to make the new configuration take effect
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_rx_update_config(parl_io_dev_t *dev)
|
||||
{
|
||||
dev->reg_update.rx_reg_update = 1;
|
||||
while (dev->reg_update.rx_reg_update);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the RX fifo cycle count
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @return
|
||||
* - RX fifo cycle count
|
||||
*/
|
||||
static inline uint32_t parlio_ll_rx_get_fifo_cycle_cnt(parl_io_dev_t *dev)
|
||||
{
|
||||
return dev->rx_st0.rx_cnt;
|
||||
}
|
||||
|
||||
///////////////////////////////////TX Unit///////////////////////////////////////
|
||||
|
||||
/**
|
||||
* @brief Set the clock source for the TX unit
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param src Clock source
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void _parlio_ll_tx_set_clock_source(parl_io_dev_t *dev, parlio_clock_source_t src)
|
||||
{
|
||||
(void)dev;
|
||||
uint32_t clk_sel = 0;
|
||||
switch (src) {
|
||||
case PARLIO_CLK_SRC_XTAL:
|
||||
clk_sel = 0;
|
||||
break;
|
||||
case PARLIO_CLK_SRC_RC_FAST:
|
||||
clk_sel = 1;
|
||||
break;
|
||||
case PARLIO_CLK_SRC_PLL_F160M:
|
||||
clk_sel = 2;
|
||||
break;
|
||||
case PARLIO_CLK_SRC_EXTERNAL:
|
||||
clk_sel = 3;
|
||||
break;
|
||||
|
||||
default: // unsupported clock source
|
||||
HAL_ASSERT(false);
|
||||
break;
|
||||
}
|
||||
HP_SYS_CLKRST.peri_clk_ctrl118.reg_parlio_tx_clk_src_sel = clk_sel;
|
||||
}
|
||||
|
||||
/// use a macro to wrap the function, force the caller to use it in a critical section
|
||||
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
|
||||
#define parlio_ll_tx_set_clock_source(...) do { \
|
||||
(void)__DECLARE_RCC_ATOMIC_ENV; \
|
||||
_parlio_ll_tx_set_clock_source(__VA_ARGS__); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Set the clock divider for the TX unit
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param clk_div Clock division with integral and decimal part
|
||||
*/
|
||||
static inline void _parlio_ll_tx_set_clock_div(parl_io_dev_t *dev, const hal_utils_clk_div_t *clk_div)
|
||||
{
|
||||
(void)dev;
|
||||
HAL_ASSERT(clk_div->integer > 0 && clk_div->integer <= PARLIO_LL_RX_MAX_CLK_INT_DIV);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl118, reg_parlio_tx_clk_div_num, clk_div->integer - 1);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl119, reg_parlio_tx_clk_div_denominator, clk_div->denominator);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl119, reg_parlio_tx_clk_div_numerator, clk_div->numerator);
|
||||
}
|
||||
|
||||
/// use a macro to wrap the function, force the caller to use it in a critical section
|
||||
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
|
||||
#define parlio_ll_tx_set_clock_div(...) do { \
|
||||
(void)__DECLARE_RCC_ATOMIC_ENV; \
|
||||
_parlio_ll_tx_set_clock_div(__VA_ARGS__); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Reset the TX unit Core clock domain
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void _parlio_ll_tx_reset_clock(parl_io_dev_t *dev)
|
||||
{
|
||||
(void)dev;
|
||||
HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_parlio_tx = 1;
|
||||
HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_parlio_tx = 0;
|
||||
}
|
||||
|
||||
/// use a macro to wrap the function, force the caller to use it in a critical section
|
||||
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
|
||||
#define parlio_ll_tx_reset_clock(...) do { \
|
||||
(void)__DECLARE_RCC_ATOMIC_ENV; \
|
||||
_parlio_ll_tx_reset_clock(__VA_ARGS__); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Enable the TX unit Core clock domain
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param en True to enable, False to disable
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void _parlio_ll_tx_enable_clock(parl_io_dev_t *dev, bool en)
|
||||
{
|
||||
(void)dev;
|
||||
LP_AON_CLKRST.hp_clk_ctrl.hp_pad_parlio_tx_clk_en = en;
|
||||
HP_SYS_CLKRST.peri_clk_ctrl118.reg_parlio_tx_clk_en = en;
|
||||
}
|
||||
|
||||
/// use a macro to wrap the function, force the caller to use it in a critical section
|
||||
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
|
||||
#define parlio_ll_tx_enable_clock(...) do { \
|
||||
(void)__DECLARE_RCC_ATOMIC_ENV; \
|
||||
_parlio_ll_tx_enable_clock(__VA_ARGS__); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Set the data length to be transmitted
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param bitlen Data length in bits, must be a multiple of 8
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_tx_set_trans_bit_len(parl_io_dev_t *dev, uint32_t bitlen)
|
||||
{
|
||||
dev->tx_data_cfg.tx_bitlen = bitlen;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if tx size can be determined by DMA
|
||||
*
|
||||
* @param dev Parallel IO register base address (not used)
|
||||
*/
|
||||
static inline bool parlio_ll_tx_support_dma_eof(parl_io_dev_t *dev)
|
||||
{
|
||||
(void)dev;
|
||||
return true;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the condition to generate the TX EOF event
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param cond TX EOF condition
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_tx_set_eof_condition(parl_io_dev_t *dev, parlio_ll_tx_eof_cond_t cond)
|
||||
{
|
||||
dev->tx_genrl_cfg.tx_eof_gen_sel = cond;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief whether to enable the TX clock gating
|
||||
*
|
||||
* @note The MSB of TXD will be taken as the gating enable signal
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param en True to enable, False to disable
|
||||
*/
|
||||
static inline void parlio_ll_tx_enable_clock_gating(parl_io_dev_t *dev, bool en)
|
||||
{
|
||||
dev->tx_genrl_cfg.tx_gating_en = en;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Start TX unit to transmit data
|
||||
*
|
||||
* @note The hardware monitors the rising edge of tx_start as the trigger signal.
|
||||
* Once the transmission starts, it cannot be stopped by clearing tx_start.
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param en True to start, False to reset the reg state (not meaning the TX unit will be stopped)
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_tx_start(parl_io_dev_t *dev, bool en)
|
||||
{
|
||||
dev->tx_start_cfg.tx_start = en;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the sample clock edge
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param edge Sample clock edge
|
||||
*/
|
||||
static inline void parlio_ll_tx_set_sample_clock_edge(parl_io_dev_t *dev, parlio_sample_edge_t edge)
|
||||
{
|
||||
dev->tx_clk_cfg.tx_clk_i_inv = edge;
|
||||
dev->tx_clk_cfg.tx_clk_o_inv = edge;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the order to unpack bits from a byte
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param order Packing order
|
||||
*/
|
||||
static inline void parlio_ll_tx_set_bit_pack_order(parl_io_dev_t *dev, parlio_bit_pack_order_t order)
|
||||
{
|
||||
dev->tx_data_cfg.tx_data_order_inv = order;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the bus width of the TX unit
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param width Bus width
|
||||
*/
|
||||
static inline void parlio_ll_tx_set_bus_width(parl_io_dev_t *dev, uint32_t width)
|
||||
{
|
||||
uint32_t width_sel = 0;
|
||||
switch (width) {
|
||||
case 16:
|
||||
width_sel = 4;
|
||||
break;
|
||||
case 8:
|
||||
width_sel = 3;
|
||||
break;
|
||||
case 4:
|
||||
width_sel = 2;
|
||||
break;
|
||||
case 2:
|
||||
width_sel = 1;
|
||||
break;
|
||||
case 1:
|
||||
width_sel = 0;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(false);
|
||||
}
|
||||
dev->tx_data_cfg.tx_bus_wid_sel = width_sel;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reset TX Async FIFO
|
||||
*
|
||||
* @note During the reset of the asynchronous FIFO, it takes two clock cycles to synchronize within AHB clock domain (GDMA) and Core clock domain.
|
||||
* The reset synchronization must be performed two clock cycles in advance.
|
||||
* @note If the next frame transfer needs to be reset, you need to first switch to the internal free-running clock,
|
||||
* and then switch to the actual clock after the reset is completed.
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_tx_reset_fifo(parl_io_dev_t *dev)
|
||||
{
|
||||
dev->fifo_cfg.tx_fifo_srst = 1;
|
||||
dev->fifo_cfg.tx_fifo_srst = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the value to output on the TXD when the TX unit is in IDLE state
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param value Value to output
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_tx_set_idle_data_value(parl_io_dev_t *dev, uint32_t value)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->tx_genrl_cfg, tx_idle_value, value);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check whether the TX unit is ready
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @return true: ready, false: busy
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool parlio_ll_tx_is_ready(parl_io_dev_t *dev)
|
||||
{
|
||||
return dev->st.tx_ready;
|
||||
}
|
||||
|
||||
////////////////////////////////////Interrupt////////////////////////////////////////////////
|
||||
|
||||
/**
|
||||
* @brief Enable Parallel IO interrupt for specific event mask
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param mask Event mask
|
||||
* @param enable True to enable, False to disable
|
||||
*/
|
||||
static inline void parlio_ll_enable_interrupt(parl_io_dev_t *dev, uint32_t mask, bool enable)
|
||||
{
|
||||
if (enable) {
|
||||
dev->int_ena.val |= mask;
|
||||
} else {
|
||||
dev->int_ena.val &= ~mask;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get interrupt status for TX unit
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @return Interrupt status
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t parlio_ll_tx_get_interrupt_status(parl_io_dev_t *dev)
|
||||
{
|
||||
return dev->int_st.val & PARLIO_LL_EVENT_TX_MASK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get interrupt status for RX unit
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @return Interrupt status
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t parlio_ll_rx_get_interrupt_status(parl_io_dev_t *dev)
|
||||
{
|
||||
return dev->int_st.val & PARLIO_LL_EVENT_RX_MASK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear Parallel IO interrupt status by mask
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param mask Interrupt status mask
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void parlio_ll_clear_interrupt_status(parl_io_dev_t *dev, uint32_t mask)
|
||||
{
|
||||
dev->int_clr.val = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get interrupt status register address
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @return Register address
|
||||
*/
|
||||
static inline volatile void *parlio_ll_get_interrupt_status_reg(parl_io_dev_t *dev)
|
||||
{
|
||||
return &dev->int_st;
|
||||
}
|
||||
|
||||
/**********************************************************************************************************************/
|
||||
/************************ The following functions behave differently based on the chip revision ***********************/
|
||||
/**********************************************************************************************************************/
|
||||
|
||||
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
|
||||
/**
|
||||
* @brief Set the clock gating from the valid signal
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param en If set to true, the clock is gated by the valid signal, otherwise it is gated by the MSB of the data line.
|
||||
*/
|
||||
static inline void parlio_ll_tx_clock_gating_from_valid(parl_io_dev_t *dev, bool en)
|
||||
{
|
||||
dev->tx_genrl_cfg.tx_valid_output_en = en;
|
||||
}
|
||||
#else
|
||||
/**
|
||||
* @brief Whether to treat the MSB of TXD as the valid signal
|
||||
*
|
||||
* @note If enabled, TXD[15] will work as valid signal, which stay high during data transmission.
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param en True to enable, False to disable
|
||||
*/
|
||||
static inline void parlio_ll_tx_treat_msb_as_valid(parl_io_dev_t *dev, bool en)
|
||||
{
|
||||
dev->tx_genrl_cfg.tx_valid_output_en = en;
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Set TX valid signal delay
|
||||
*
|
||||
* @param dev Parallel IO register base address
|
||||
* @param start_delay Number of clock cycles to delay
|
||||
* @param stop_delay Number of clock cycles to delay
|
||||
* @return true: success, false: valid delay is not supported
|
||||
*/
|
||||
static inline bool parlio_ll_tx_set_valid_delay(parl_io_dev_t *dev, uint32_t start_delay, uint32_t stop_delay)
|
||||
{
|
||||
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
|
||||
if (start_delay > PARLIO_LL_TX_VALID_MAX_DELAY || stop_delay > PARLIO_LL_TX_VALID_MAX_DELAY) {
|
||||
return false;
|
||||
}
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->tx_cs_cfg, tx_cs_start_delay, start_delay);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->tx_cs_cfg, tx_cs_stop_delay, stop_delay);
|
||||
return true;
|
||||
#else
|
||||
(void)dev;
|
||||
if (start_delay == 0 && stop_delay == 0) {
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,97 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "hal/parlio_periph.h"
|
||||
#include "soc/gpio_sig_map.h"
|
||||
|
||||
const parlio_signal_conn_t parlio_periph_signals = {
|
||||
.groups = {
|
||||
[0] = {
|
||||
.module_name = "PARLIO0",
|
||||
.tx_irq_id = ETS_HP_PARLIO_TX_INTR_SOURCE,
|
||||
.rx_irq_id = ETS_HP_PARLIO_RX_INTR_SOURCE,
|
||||
.tx_units = {
|
||||
[0] = {
|
||||
.data_sigs = {
|
||||
PARLIO_TX_DATA0_PAD_OUT_IDX,
|
||||
PARLIO_TX_DATA1_PAD_OUT_IDX,
|
||||
PARLIO_TX_DATA2_PAD_OUT_IDX,
|
||||
PARLIO_TX_DATA3_PAD_OUT_IDX,
|
||||
PARLIO_TX_DATA4_PAD_OUT_IDX,
|
||||
PARLIO_TX_DATA5_PAD_OUT_IDX,
|
||||
PARLIO_TX_DATA6_PAD_OUT_IDX,
|
||||
PARLIO_TX_DATA7_PAD_OUT_IDX,
|
||||
PARLIO_TX_DATA8_PAD_OUT_IDX,
|
||||
PARLIO_TX_DATA9_PAD_OUT_IDX,
|
||||
PARLIO_TX_DATA10_PAD_OUT_IDX,
|
||||
PARLIO_TX_DATA11_PAD_OUT_IDX,
|
||||
PARLIO_TX_DATA12_PAD_OUT_IDX,
|
||||
PARLIO_TX_DATA13_PAD_OUT_IDX,
|
||||
PARLIO_TX_DATA14_PAD_OUT_IDX,
|
||||
PARLIO_TX_DATA15_PAD_OUT_IDX,
|
||||
},
|
||||
.clk_out_sig = PARLIO_TX_CLK_PAD_OUT_IDX,
|
||||
.clk_in_sig = PARLIO_TX_CLK_PAD_IN_IDX,
|
||||
.cs_sig = PARLIO_TX_CS_PAD_OUT_IDX,
|
||||
}
|
||||
},
|
||||
.rx_units = {
|
||||
[0] = {
|
||||
.data_sigs = {
|
||||
PARLIO_RX_DATA0_PAD_IN_IDX,
|
||||
PARLIO_RX_DATA1_PAD_IN_IDX,
|
||||
PARLIO_RX_DATA2_PAD_IN_IDX,
|
||||
PARLIO_RX_DATA3_PAD_IN_IDX,
|
||||
PARLIO_RX_DATA4_PAD_IN_IDX,
|
||||
PARLIO_RX_DATA5_PAD_IN_IDX,
|
||||
PARLIO_RX_DATA6_PAD_IN_IDX,
|
||||
PARLIO_RX_DATA7_PAD_IN_IDX,
|
||||
PARLIO_RX_DATA8_PAD_IN_IDX,
|
||||
PARLIO_RX_DATA9_PAD_IN_IDX,
|
||||
PARLIO_RX_DATA10_PAD_IN_IDX,
|
||||
PARLIO_RX_DATA11_PAD_IN_IDX,
|
||||
PARLIO_RX_DATA12_PAD_IN_IDX,
|
||||
PARLIO_RX_DATA13_PAD_IN_IDX,
|
||||
PARLIO_RX_DATA14_PAD_IN_IDX,
|
||||
PARLIO_RX_DATA15_PAD_IN_IDX,
|
||||
},
|
||||
.clk_out_sig = PARLIO_RX_CLK_PAD_OUT_IDX,
|
||||
.clk_in_sig = PARLIO_RX_CLK_PAD_IN_IDX,
|
||||
}
|
||||
}
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/**
|
||||
* PARLIO Registers to be saved during sleep retention
|
||||
* - Tx Configuration registers, e.g.: PARL_IO_TX_DATA_CFG_REG, PARL_IO_TX_GENRL_CFG_REG
|
||||
* - Rx Configuration registers, e.g.: PARL_IO_RX_MODE_CFG_REG, PARL_IO_RX_DATA_CFG_REG, PARL_IO_RX_GENRL_CFG_REG
|
||||
* - CLK Configuration registers, e.g.: PARL_IO_RX_CLK_CFG_REG, PARL_IO_TX_CLK_CFG_REG
|
||||
* - Interrupt enable registers, e.g.: PARL_IO_INT_ENA_REG
|
||||
*/
|
||||
#define PARLIO_RETENTION_REGS_CNT 8
|
||||
#define PARLIO_RETENTION_REGS_BASE (DR_REG_PARL_IO_BASE + 0x0)
|
||||
static const uint32_t parlio_regs_map[4] = {0x60457, 0x0, 0x0, 0x0};
|
||||
static const regdma_entries_config_t parlio_regs_retention[] = {
|
||||
// backup stage: save configuration registers
|
||||
// restore stage: restore the configuration registers
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PARLIO_LINK(0x00),
|
||||
PARLIO_RETENTION_REGS_BASE, PARLIO_RETENTION_REGS_BASE,
|
||||
PARLIO_RETENTION_REGS_CNT, 0, 0,
|
||||
parlio_regs_map[0], parlio_regs_map[1],
|
||||
parlio_regs_map[2], parlio_regs_map[3]),
|
||||
.owner = ENTRY(0)
|
||||
},
|
||||
};
|
||||
const parlio_reg_retention_info_t parlio_reg_retention_info[SOC_PARLIO_GROUPS] = {
|
||||
[0] = {
|
||||
.regdma_entry_array = parlio_regs_retention,
|
||||
.array_size = ARRAY_SIZE(parlio_regs_retention),
|
||||
.retention_module = SLEEP_RETENTION_MODULE_PARLIO0
|
||||
},
|
||||
};
|
||||
@@ -0,0 +1,47 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* NOTICE
|
||||
* The hal is not public api, don't use in application code.
|
||||
* See readme.md in hal/include/hal/readme.md
|
||||
******************************************************************************/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "hal/parlio_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef struct parl_io_dev_t *parlio_soc_handle_t; // Parallel IO SOC layer handle
|
||||
|
||||
/**
|
||||
* @brief HAL context type of Parallel IO driver
|
||||
*/
|
||||
typedef struct {
|
||||
parlio_soc_handle_t regs; /*!< Parallel IO Register base address */
|
||||
} parlio_hal_context_t;
|
||||
|
||||
/**
|
||||
* @brief Initialize the Parallel IO HAL driver
|
||||
*
|
||||
* @param hal: Parallel IO HAL context
|
||||
*/
|
||||
void parlio_hal_init(parlio_hal_context_t *hal);
|
||||
|
||||
/**
|
||||
* @brief Deinitialize the Parallel IO HAL driver
|
||||
*
|
||||
* @param hal: Parallel IO HAL context
|
||||
*/
|
||||
void parlio_hal_deinit(parlio_hal_context_t *hal);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,62 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/soc_caps.h"
|
||||
#include "soc/periph_defs.h"
|
||||
#if SOC_PARLIO_SUPPORTED
|
||||
#include "soc/parl_io_reg.h"
|
||||
#include "soc/parl_io_struct.h"
|
||||
#endif
|
||||
#include "soc/regdma.h"
|
||||
#if SOC_PARLIO_SUPPORT_SLEEP_RETENTION
|
||||
#include "soc/retention_periph_defs.h"
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if SOC_PARLIO_SUPPORTED
|
||||
typedef struct {
|
||||
struct {
|
||||
struct {
|
||||
const int data_sigs[SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH];
|
||||
const int clk_out_sig;
|
||||
const int clk_in_sig;
|
||||
const int cs_sig;
|
||||
} tx_units[SOC_PARLIO_TX_UNITS_PER_GROUP];
|
||||
struct {
|
||||
const int data_sigs[SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH];
|
||||
const int clk_out_sig;
|
||||
const int clk_in_sig;
|
||||
} rx_units[SOC_PARLIO_RX_UNITS_PER_GROUP];
|
||||
const int tx_irq_id;
|
||||
const int rx_irq_id;
|
||||
const shared_periph_module_t module;
|
||||
const char *module_name;
|
||||
} groups[SOC_PARLIO_GROUPS];
|
||||
} parlio_signal_conn_t;
|
||||
|
||||
extern const parlio_signal_conn_t parlio_periph_signals;
|
||||
|
||||
#if SOC_PARLIO_SUPPORT_SLEEP_RETENTION
|
||||
typedef struct {
|
||||
const periph_retention_module_t retention_module;
|
||||
const regdma_entries_config_t *regdma_entry_array;
|
||||
uint32_t array_size;
|
||||
} parlio_reg_retention_info_t;
|
||||
|
||||
extern const parlio_reg_retention_info_t parlio_reg_retention_info[SOC_PARLIO_GROUPS];
|
||||
#endif // SOC_PARLIO_SUPPORT_SLEEP_RETENTION
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,71 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "soc/soc_caps.h"
|
||||
#include "soc/clk_tree_defs.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Parallel IO sample edge
|
||||
*/
|
||||
typedef enum {
|
||||
PARLIO_SAMPLE_EDGE_NEG, /*!< Sample data on falling edge of clock */
|
||||
PARLIO_SAMPLE_EDGE_POS, /*!< Sample data on rising edge of clock */
|
||||
} parlio_sample_edge_t;
|
||||
|
||||
/**
|
||||
* @brief Parallel IO bit packing order
|
||||
*
|
||||
* Data in memory:
|
||||
* Byte 0: MSB < B0.7 B0.6 B0.5 B0.4 B0.3 B0.2 B0.1 B0.0 > LSB
|
||||
* Byte 1: MSB < B1.7 B1.6 B1.5 B1.4 B1.3 B1.2 B1.1 B1.0 > LSB
|
||||
*
|
||||
* Output on line (PARLIO_BIT_PACK_ORDER_LSB):
|
||||
* Cycle 0 Cycle 1 Cycle 2 ---> time
|
||||
* GPIO 0: B0.0 B0.4 B1.0
|
||||
* GPIO 1: B0.1 B0.5 B1.1
|
||||
* GPIO 2: B0.2 B0.6 B1.2
|
||||
* GPIO 3: B0.3 B0.7 B1.3
|
||||
*
|
||||
* Output on line (PARLIO_BIT_PACK_ORDER_MSB):
|
||||
* Cycle 0 Cycle 1 Cycle 2 ---> time
|
||||
* GPIO 0: B0.4 B0.0 B1.4
|
||||
* GPIO 1: B0.5 B0.1 B1.5
|
||||
* GPIO 2: B0.6 B0.2 B1.6
|
||||
* GPIO 3: B0.7 B0.3 B1.7
|
||||
*/
|
||||
typedef enum {
|
||||
PARLIO_BIT_PACK_ORDER_LSB, /*!< Bit pack order: LSB */
|
||||
PARLIO_BIT_PACK_ORDER_MSB, /*!< Bit pack order: MSB */
|
||||
} parlio_bit_pack_order_t;
|
||||
|
||||
#if SOC_PARLIO_SUPPORTED
|
||||
/**
|
||||
* @brief Parallel IO clock source
|
||||
* @note User should select the clock source based on the power and resolution requirement
|
||||
*/
|
||||
typedef soc_periph_parlio_clk_src_t parlio_clock_source_t;
|
||||
|
||||
/// Maximum data width of TX unit
|
||||
#define PARLIO_TX_UNIT_MAX_DATA_WIDTH SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH
|
||||
/// Maximum data width of RX unit
|
||||
#define PARLIO_RX_UNIT_MAX_DATA_WIDTH SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH
|
||||
#else
|
||||
typedef int parlio_clock_source_t;
|
||||
#define PARLIO_TX_UNIT_MAX_DATA_WIDTH 0
|
||||
#define PARLIO_RX_UNIT_MAX_DATA_WIDTH 0
|
||||
#endif // SOC_PARLIO_SUPPORTED
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,20 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <stddef.h>
|
||||
#include "hal/parlio_hal.h"
|
||||
#include "hal/parlio_ll.h"
|
||||
|
||||
void parlio_hal_init(parlio_hal_context_t *hal)
|
||||
{
|
||||
hal->regs = &PARL_IO;
|
||||
}
|
||||
|
||||
void parlio_hal_deinit(parlio_hal_context_t *hal)
|
||||
{
|
||||
hal->regs = NULL;
|
||||
}
|
||||
Reference in New Issue
Block a user