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feat(esp_system): Adds Kconfigs to place code in IRAM

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This commit is contained in:
Konstantin Kondrashov
2025-07-24 00:34:58 +08:00
committed by BOT
parent 9c4aa443b0
commit e72ea712e7
55 changed files with 215 additions and 131 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/esp_system/port/arch/riscv/debug_helpers.c
+2 -2
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@@ -11,7 +11,7 @@
#include "freertos/task.h"
#include "esp_private/freertos_debug.h"
#include "esp_err.h"
#include "esp_attr.h"
#include "esp_private/esp_system_attr.h"
#include "esp_private/esp_cpu_internal.h"
#include <string.h>
@@ -36,7 +36,7 @@ extern void panic_print_registers(const void *frame, int core);
* exit this handler as fast as possible, then we will simply print
* the interruptee's registers.
*/
esp_err_t IRAM_ATTR esp_backtrace_print(int depth)
esp_err_t ESP_SYSTEM_IRAM_ATTR esp_backtrace_print(int depth)
{
(void)depth;
components/esp_system/port/arch/riscv/esp_ipc_isr_port.c
+2 -2
View File
@@ -11,7 +11,7 @@
#include "riscv/interrupt.h"
#include "esp_rom_sys.h"
#include "esp_cpu.h"
#include "esp_attr.h"
#include "esp_private/esp_system_attr.h"
#include "sdkconfig.h"
void esp_ipc_isr_port_init(const int cpuid)
@@ -35,7 +35,7 @@ void esp_ipc_isr_port_init(const int cpuid)
esp_intr_enable_source(ETS_IPC_ISR_INUM);
}
IRAM_ATTR void esp_ipc_isr_port_int_trigger(const int cpuid)
ESP_SYSTEM_IRAM_ATTR void esp_ipc_isr_port_int_trigger(const int cpuid)
{
if (cpuid == 0) {
// it runs an interrupt on cpu0
components/esp_system/port/arch/riscv/esp_ipc_isr_routines.c
+2 -2
View File
@@ -5,9 +5,9 @@
*/
#include "stdint.h"
#include "esp_attr.h"
#include "esp_private/esp_system_attr.h"
void IRAM_ATTR esp_ipc_isr_waiting_for_finish_cmd(void* ipc_isr_finish_cmd)
void ESP_SYSTEM_IRAM_ATTR esp_ipc_isr_waiting_for_finish_cmd(void* ipc_isr_finish_cmd)
{
while (*(volatile uint32_t *)ipc_isr_finish_cmd == 0) { };
}
components/esp_system/port/arch/xtensa/debug_helpers.c
+8 -8
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -9,7 +9,7 @@
#include <sys/param.h>
#include "soc/soc_memory_layout.h"
#include "esp_types.h"
#include "esp_attr.h"
#include "esp_private/esp_system_attr.h"
#include "esp_err.h"
#include "esp_check.h"
#include "esp_ipc.h"
@@ -24,7 +24,7 @@
const char *DEBUG_HELPER_TAG = "DBG HLPR";
bool IRAM_ATTR esp_backtrace_get_next_frame(esp_backtrace_frame_t *frame)
bool ESP_SYSTEM_IRAM_ATTR esp_backtrace_get_next_frame(esp_backtrace_frame_t *frame)
{
//Use frame(i-1)'s BS area located below frame(i)'s sp to get frame(i-1)'s sp and frame(i-2)'s pc
void *base_save = (void *)frame->sp; //Base save area consists of 4 words under SP
@@ -36,7 +36,7 @@ bool IRAM_ATTR esp_backtrace_get_next_frame(esp_backtrace_frame_t *frame)
return (esp_stack_ptr_is_sane(frame->sp) && esp_ptr_executable((void*)esp_cpu_process_stack_pc(frame->pc)));
}
static void IRAM_ATTR print_entry(uint32_t pc, uint32_t sp, bool panic)
static void ESP_SYSTEM_IRAM_ATTR print_entry(uint32_t pc, uint32_t sp, bool panic)
{
if (panic) {
panic_print_str(" 0x");
@@ -48,7 +48,7 @@ static void IRAM_ATTR print_entry(uint32_t pc, uint32_t sp, bool panic)
}
}
static void IRAM_ATTR print_str(const char* str, bool panic)
static void ESP_SYSTEM_IRAM_ATTR print_str(const char* str, bool panic)
{
if (panic) {
panic_print_str(str);
@@ -57,7 +57,7 @@ static void IRAM_ATTR print_str(const char* str, bool panic)
}
}
esp_err_t IRAM_ATTR esp_backtrace_print_from_frame(int depth, const esp_backtrace_frame_t* frame, bool panic)
esp_err_t ESP_SYSTEM_IRAM_ATTR esp_backtrace_print_from_frame(int depth, const esp_backtrace_frame_t* frame, bool panic)
{
//Check arguments
if (depth <= 0) {
@@ -97,7 +97,7 @@ esp_err_t IRAM_ATTR esp_backtrace_print_from_frame(int depth, const esp_backtrac
return ret;
}
esp_err_t IRAM_ATTR esp_backtrace_print(int depth)
esp_err_t ESP_SYSTEM_IRAM_ATTR esp_backtrace_print(int depth)
{
//Initialize stk_frame with first frame of stack
esp_backtrace_frame_t start = { 0 };
@@ -149,7 +149,7 @@ static void backtrace_other_cores_ipc_func(void *arg)
}
#endif // !CONFIG_FREERTOS_UNICORE
esp_err_t IRAM_ATTR esp_backtrace_print_all_tasks(int depth)
esp_err_t ESP_SYSTEM_IRAM_ATTR esp_backtrace_print_all_tasks(int depth)
{
esp_err_t ret = ESP_OK;
TaskSnapshot_t *task_snapshots;
components/esp_system/port/arch/xtensa/esp_ipc_isr_port.c
+2 -2
View File
@@ -12,7 +12,7 @@
#endif
#include "esp_rom_sys.h"
#include "esp_intr_alloc.h"
#include "esp_attr.h"
#include "esp_private/esp_system_attr.h"
#include "sdkconfig.h"
void esp_ipc_isr_port_init(const int cpuid)
@@ -23,7 +23,7 @@ void esp_ipc_isr_port_init(const int cpuid)
ESP_INTR_ENABLE(ETS_IPC_ISR_INUM);
}
IRAM_ATTR void esp_ipc_isr_port_int_trigger(const int cpuid)
ESP_SYSTEM_IRAM_ATTR void esp_ipc_isr_port_int_trigger(const int cpuid)
{
if (cpuid == 0) {
// it runs an interrupt on cpu0
components/esp_system/port/arch/xtensa/esp_ipc_isr_routines.S
+3
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@@ -8,13 +8,16 @@
#include <xtensa/corebits.h>
#include <xtensa/config/system.h>
#include <xtensa/hal.h>
#include "sdkconfig.h"
/* esp_ipc_isr_waiting_for_finish_cmd(void* finish_cmd)
*
* It should be called by the CALLX0 command from the handler of High-priority interrupt.
* Only these registers [a2, a3, a4] can be used here.
*/
#if CONFIG_ESP_SYSTEM_IN_IRAM
.section .iram1, "ax"
#endif
.align 4
.global esp_ipc_isr_waiting_for_finish_cmd
.type esp_ipc_isr_waiting_for_finish_cmd, @function
components/esp_system/port/cpu_start.c
+3 -3
View File
@@ -8,7 +8,7 @@
#include <string.h>
#include <stdbool.h>
#include "esp_attr.h"
#include "esp_private/esp_system_attr.h"
#include "esp_err.h"
#include "esp_log.h"
@@ -193,7 +193,7 @@ void startup_resume_other_cores(void)
s_resume_cores = true;
}
void IRAM_ATTR call_start_cpu1(void)
void ESP_SYSTEM_IRAM_ATTR call_start_cpu1(void)
{
#ifdef __riscv
// Configure the global pointer register
@@ -323,7 +323,7 @@ static void restore_app_mmu_from_pro_mmu(void)
}
#endif
// This function is needed to make the multicore app runnable on a unicore bootloader (built with FREERTOS UNICORE).
// It does some cache settings for other CPUs.
// It does some cache settings for other CPUs, so it must be in IRAM.
void IRAM_ATTR do_multicore_settings(void)
{
// We intentionally do not check the cache settings before changing them,
components/esp_system/port/esp_ipc_isr.c
+10 -10
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -9,7 +9,7 @@
#include <string.h>
#include <assert.h>
#include "esp_err.h"
#include "esp_attr.h"
#include "esp_private/esp_system_attr.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/portmacro.h"
@@ -63,14 +63,14 @@ void esp_ipc_isr_init(void)
/* Public API functions */
void IRAM_ATTR esp_ipc_isr_call(esp_ipc_isr_func_t func, void* arg)
void ESP_SYSTEM_IRAM_ATTR esp_ipc_isr_call(esp_ipc_isr_func_t func, void* arg)
{
IPC_ISR_ENTER_CRITICAL();
esp_ipc_isr_call_and_wait(func, arg, IPC_ISR_WAIT_FOR_START);
IPC_ISR_EXIT_CRITICAL();
}
void IRAM_ATTR esp_ipc_isr_call_blocking(esp_ipc_isr_func_t func, void* arg)
void ESP_SYSTEM_IRAM_ATTR esp_ipc_isr_call_blocking(esp_ipc_isr_func_t func, void* arg)
{
IPC_ISR_ENTER_CRITICAL();
esp_ipc_isr_call_and_wait(func, arg, IPC_ISR_WAIT_FOR_END);
@@ -90,7 +90,7 @@ void esp_ipc_isr_waiting_for_finish_cmd(void* finish_cmd);
* When cpu1 already in high-priority interrupt, cpu0 can access DPORT register.
* Currently, cpu1 will wait for cpu0 finish access and exit high-priority interrupt.
*/
void IRAM_ATTR esp_ipc_isr_stall_other_cpu(void)
void ESP_SYSTEM_IRAM_ATTR esp_ipc_isr_stall_other_cpu(void)
{
#if CONFIG_FREERTOS_SMP
/*
@@ -123,7 +123,7 @@ void IRAM_ATTR esp_ipc_isr_stall_other_cpu(void)
}
}
void IRAM_ATTR esp_ipc_isr_release_other_cpu(void)
void ESP_SYSTEM_IRAM_ATTR esp_ipc_isr_release_other_cpu(void)
{
if (s_stall_state == STALL_STATE_RUNNING) {
const uint32_t cpu_id = xPortGetCoreID();
@@ -150,20 +150,20 @@ void IRAM_ATTR esp_ipc_isr_release_other_cpu(void)
#endif
}
void IRAM_ATTR esp_ipc_isr_stall_pause(void)
void ESP_SYSTEM_IRAM_ATTR esp_ipc_isr_stall_pause(void)
{
IPC_ISR_ENTER_CRITICAL();
s_stall_state = STALL_STATE_IDLE;
IPC_ISR_EXIT_CRITICAL();
}
void IRAM_ATTR esp_ipc_isr_stall_abort(void)
void ESP_SYSTEM_IRAM_ATTR esp_ipc_isr_stall_abort(void)
{
//Note: We don't enter a critical section here as we are calling this from a panic.
s_stall_state = STALL_STATE_IDLE;
}
void IRAM_ATTR esp_ipc_isr_stall_resume(void)
void ESP_SYSTEM_IRAM_ATTR esp_ipc_isr_stall_resume(void)
{
IPC_ISR_ENTER_CRITICAL();
s_stall_state = STALL_STATE_RUNNING;
@@ -174,7 +174,7 @@ void IRAM_ATTR esp_ipc_isr_stall_resume(void)
/* Private functions*/
static void IRAM_ATTR esp_ipc_isr_call_and_wait(esp_ipc_isr_func_t func, void* arg, esp_ipc_isr_wait_t wait_for)
static void ESP_SYSTEM_IRAM_ATTR esp_ipc_isr_call_and_wait(esp_ipc_isr_func_t func, void* arg, esp_ipc_isr_wait_t wait_for)
{
const uint32_t cpu_id = xPortGetCoreID();
components/esp_system/port/esp_system_chip.c
+1 -1
View File
@@ -21,7 +21,7 @@
// used only by ESP32 panic handler
#ifdef CONFIG_IDF_TARGET_ESP32
void IRAM_ATTR esp_restart_noos_dig(void)
void esp_restart_noos_dig(void)
{
// In case any of the calls below results in re-enabling of interrupts
// (for example, by entering a critical section), disable all the
components/esp_system/port/panic_handler.c
+2
View File
@@ -287,6 +287,7 @@ static void IRAM_ATTR panic_enable_cache(void)
}
#endif
// This function must always be in IRAM as it is required to re-enable the flash cache.
void IRAM_ATTR panicHandler(void *frame)
{
#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
@@ -299,6 +300,7 @@ void IRAM_ATTR panicHandler(void *frame)
panic_handler(frame, true);
}
// This function must always be in IRAM as it is required to re-enable the flash cache.
void IRAM_ATTR xt_unhandled_exception(void *frame)
{
#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
components/esp_system/port/soc/esp32/reset_reason.c
+1 -1
View File
@@ -87,7 +87,7 @@ esp_reset_reason_t esp_reset_reason(void)
#define RST_REASON_SHIFT 16
/* in IRAM, can be called from panic handler */
void IRAM_ATTR esp_reset_reason_set_hint(esp_reset_reason_t hint)
void esp_reset_reason_set_hint(esp_reset_reason_t hint)
{
assert((hint & (~RST_REASON_MASK)) == 0);
uint32_t val = hint | (hint << RST_REASON_SHIFT) | RST_REASON_BIT;
components/esp_system/port/soc/esp32/system_internal.c
+2 -2
View File
@@ -28,7 +28,7 @@
#include "esp32/rom/cache.h"
#include "esp32/rom/rtc.h"
void IRAM_ATTR esp_system_reset_modules_on_exit(void)
void esp_system_reset_modules_on_exit(void)
{
// Flush any data left in UART FIFOs before reset the UART peripheral
for (int i = 0; i < SOC_UART_HP_NUM; ++i) {
@@ -63,7 +63,7 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void)
* core are already stopped. Stalls other core, resets hardware,
* triggers restart.
*/
void IRAM_ATTR esp_restart_noos(void)
void esp_restart_noos(void)
{
// Disable interrupts
esp_cpu_intr_disable(0xFFFFFFFF);
components/esp_system/port/soc/esp32c2/clk.c
+1 -1
View File
@@ -281,7 +281,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)
}
// Workaround for bootloader not calibrated well issue.
// Placed in IRAM because disabling BBPLL may influence the cache
// Placed in IRAM because disabling BBPLL may influence the cache.
static void IRAM_ATTR NOINLINE_ATTR recalib_bbpll(void)
{
rtc_cpu_freq_config_t old_config;
components/esp_system/port/soc/esp32c2/reset_reason.c
+1 -1
View File
@@ -76,7 +76,7 @@ esp_reset_reason_t esp_reset_reason(void)
#define RST_REASON_SHIFT 16
/* in IRAM, can be called from panic handler */
void IRAM_ATTR esp_reset_reason_set_hint(esp_reset_reason_t hint)
void esp_reset_reason_set_hint(esp_reset_reason_t hint)
{
assert((hint & (~RST_REASON_MASK)) == 0);
uint32_t val = hint | (hint << RST_REASON_SHIFT) | RST_REASON_BIT;
components/esp_system/port/soc/esp32c2/system_internal.c
+2 -2
View File
@@ -27,7 +27,7 @@
#include "esp32c2/rom/cache.h"
#include "esp32c2/rom/rtc.h"
void IRAM_ATTR esp_system_reset_modules_on_exit(void)
void esp_system_reset_modules_on_exit(void)
{
// Flush any data left in UART FIFOs before reset the UART peripheral
for (int i = 0; i < SOC_UART_HP_NUM; ++i) {
@@ -55,7 +55,7 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void)
* core are already stopped. Stalls other core, resets hardware,
* triggers restart.
*/
void IRAM_ATTR esp_restart_noos(void)
void esp_restart_noos(void)
{
// Disable interrupts
rv_utils_intr_global_disable();
components/esp_system/port/soc/esp32c3/apb_backup_dma.c
+5 -4
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -7,14 +7,15 @@
#include "soc/soc_caps.h"
#if SOC_APB_BACKUP_DMA
#include "esp_attr.h"
#include "esp_private/esp_system_attr.h"
#include "freertos/FreeRTOS.h"
#include "freertos/portmacro.h"
#include "esp32c3/rom/apb_backup_dma.h"
#include "sdkconfig.h"
static portMUX_TYPE s_apb_backup_dma_mutex = portMUX_INITIALIZER_UNLOCKED;
static void IRAM_ATTR apb_backup_dma_lock(void)
static void ESP_SYSTEM_IRAM_ATTR apb_backup_dma_lock(void)
{
if (xPortInIsrContext()) {
portENTER_CRITICAL_ISR(&s_apb_backup_dma_mutex);
@@ -23,7 +24,7 @@ static void IRAM_ATTR apb_backup_dma_lock(void)
}
}
static void IRAM_ATTR apb_backup_dma_unlock(void)
static void ESP_SYSTEM_IRAM_ATTR apb_backup_dma_unlock(void)
{
if (xPortInIsrContext()) {
portEXIT_CRITICAL_ISR(&s_apb_backup_dma_mutex);
components/esp_system/port/soc/esp32c3/reset_reason.c
+1 -1
View File
@@ -93,7 +93,7 @@ esp_reset_reason_t esp_reset_reason(void)
#define RST_REASON_SHIFT 16
/* in IRAM, can be called from panic handler */
void IRAM_ATTR esp_reset_reason_set_hint(esp_reset_reason_t hint)
void esp_reset_reason_set_hint(esp_reset_reason_t hint)
{
assert((hint & (~RST_REASON_MASK)) == 0);
uint32_t val = hint | (hint << RST_REASON_SHIFT) | RST_REASON_BIT;
components/esp_system/port/soc/esp32c3/system_internal.c
+2 -2
View File
@@ -28,7 +28,7 @@
#include "esp32c3/rom/cache.h"
#include "esp32c3/rom/rtc.h"
void IRAM_ATTR esp_system_reset_modules_on_exit(void)
void esp_system_reset_modules_on_exit(void)
{
// Flush any data left in UART FIFOs before reset the UART peripheral
for (int i = 0; i < SOC_UART_HP_NUM; ++i) {
@@ -64,7 +64,7 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void)
* core are already stopped. Stalls other core, resets hardware,
* triggers restart.
*/
void IRAM_ATTR esp_restart_noos(void)
void esp_restart_noos(void)
{
// Disable interrupts
rv_utils_intr_global_disable();
components/esp_system/port/soc/esp32c5/reset_reason.c
+1 -1
View File
@@ -102,7 +102,7 @@ esp_reset_reason_t esp_reset_reason(void)
#define RST_REASON_SHIFT 16
/* in IRAM, can be called from panic handler */
void IRAM_ATTR esp_reset_reason_set_hint(esp_reset_reason_t hint)
void esp_reset_reason_set_hint(esp_reset_reason_t hint)
{
assert((hint & (~RST_REASON_MASK)) == 0);
uint32_t val = hint | (hint << RST_REASON_SHIFT) | RST_REASON_BIT;
components/esp_system/port/soc/esp32c5/system_internal.c
+2 -2
View File
@@ -33,7 +33,7 @@
#include "esp32c5/rom/rtc.h"
#include "soc/pcr_reg.h"
void IRAM_ATTR esp_system_reset_modules_on_exit(void)
void esp_system_reset_modules_on_exit(void)
{
// Flush any data left in UART FIFOs before reset the UART peripheral
esp_rom_output_tx_wait_idle(0);
@@ -93,7 +93,7 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void)
* core are already stopped. Stalls other core, resets hardware,
* triggers restart.
*/
void IRAM_ATTR esp_restart_noos(void)
void esp_restart_noos(void)
{
// Disable interrupts
rv_utils_intr_global_disable();
components/esp_system/port/soc/esp32c6/clk.c
+1 -1
View File
@@ -328,7 +328,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)
}
// Workaround for bootloader not calibrated well issue.
// Placed in IRAM because disabling BBPLL may influence the cache
// Placed in IRAM because disabling BBPLL may influence the cache.
static void IRAM_ATTR NOINLINE_ATTR recalib_bbpll(void)
{
rtc_cpu_freq_config_t old_config;
components/esp_system/port/soc/esp32c6/reset_reason.c
+1 -1
View File
@@ -99,7 +99,7 @@ esp_reset_reason_t esp_reset_reason(void)
#define RST_REASON_SHIFT 16
/* in IRAM, can be called from panic handler */
void IRAM_ATTR esp_reset_reason_set_hint(esp_reset_reason_t hint)
void esp_reset_reason_set_hint(esp_reset_reason_t hint)
{
assert((hint & (~RST_REASON_MASK)) == 0);
uint32_t val = hint | (hint << RST_REASON_SHIFT) | RST_REASON_BIT;
components/esp_system/port/soc/esp32c6/system_internal.c
+2 -2
View File
@@ -30,7 +30,7 @@
#include "esp32c6/rom/rtc.h"
#include "soc/pcr_reg.h"
void IRAM_ATTR esp_system_reset_modules_on_exit(void)
void esp_system_reset_modules_on_exit(void)
{
// Flush any data left in UART FIFOs before reset the UART peripheral
for (int i = 0; i < SOC_UART_HP_NUM; ++i) {
@@ -86,7 +86,7 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void)
* core are already stopped. Stalls other core, resets hardware,
* triggers restart.
*/
void IRAM_ATTR esp_restart_noos(void)
void esp_restart_noos(void)
{
// Disable interrupts
rv_utils_intr_global_disable();
components/esp_system/port/soc/esp32c61/reset_reason.c
+1 -1
View File
@@ -102,7 +102,7 @@ esp_reset_reason_t esp_reset_reason(void)
#define RST_REASON_SHIFT 16
/* in IRAM, can be called from panic handler */
void IRAM_ATTR esp_reset_reason_set_hint(esp_reset_reason_t hint)
void esp_reset_reason_set_hint(esp_reset_reason_t hint)
{
assert((hint & (~RST_REASON_MASK)) == 0);
uint32_t val = hint | (hint << RST_REASON_SHIFT) | RST_REASON_BIT;
components/esp_system/port/soc/esp32c61/system_internal.c
+2 -2
View File
@@ -33,7 +33,7 @@
#include "esp32c61/rom/rtc.h"
#include "soc/pcr_reg.h"
void IRAM_ATTR esp_system_reset_modules_on_exit(void)
void esp_system_reset_modules_on_exit(void)
{
// Flush any data left in UART FIFOs before reset the UART peripheral
for (int i = 0; i < SOC_UART_HP_NUM; ++i) {
@@ -93,7 +93,7 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void)
* core are already stopped. Stalls other core, resets hardware,
* triggers restart.
*/
void IRAM_ATTR esp_restart_noos(void)
void esp_restart_noos(void)
{
// Disable interrupts
rv_utils_intr_global_disable();
components/esp_system/port/soc/esp32h2/clk.c
+1 -1
View File
@@ -313,7 +313,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)
}
// Workaround for bootloader not calibrated well issue.
// Placed in IRAM because disabling BBPLL may influence the cache
// Placed in IRAM because disabling BBPLL may influence the cache.
static void IRAM_ATTR NOINLINE_ATTR recalib_bbpll(void)
{
rtc_cpu_freq_config_t old_config;
components/esp_system/port/soc/esp32h2/reset_reason.c
+1 -1
View File
@@ -99,7 +99,7 @@ esp_reset_reason_t esp_reset_reason(void)
#define RST_REASON_SHIFT 16
/* in IRAM, can be called from panic handler */
void IRAM_ATTR esp_reset_reason_set_hint(esp_reset_reason_t hint)
void esp_reset_reason_set_hint(esp_reset_reason_t hint)
{
assert((hint & (~RST_REASON_MASK)) == 0);
uint32_t val = hint | (hint << RST_REASON_SHIFT) | RST_REASON_BIT;
components/esp_system/port/soc/esp32h2/system_internal.c
+2 -2
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@@ -31,7 +31,7 @@
#include "esp32h2/rom/rtc.h"
#include "soc/pcr_reg.h"
void IRAM_ATTR esp_system_reset_modules_on_exit(void)
void esp_system_reset_modules_on_exit(void)
{
// Flush any data left in UART FIFOs before reset the UART peripheral
for (int i = 0; i < SOC_UART_HP_NUM; ++i) {
@@ -84,7 +84,7 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void)
* core are already stopped. Stalls other core, resets hardware,
* triggers restart.
*/
void IRAM_ATTR esp_restart_noos(void)
void esp_restart_noos(void)
{
// Disable interrupts
rv_utils_intr_global_disable();
components/esp_system/port/soc/esp32h21/reset_reason.c
+1 -1
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@@ -98,7 +98,7 @@ esp_reset_reason_t esp_reset_reason(void)
#define RST_REASON_SHIFT 16
/* in IRAM, can be called from panic handler */
void IRAM_ATTR esp_reset_reason_set_hint(esp_reset_reason_t hint)
void esp_reset_reason_set_hint(esp_reset_reason_t hint)
{
assert((hint & (~RST_REASON_MASK)) == 0);
uint32_t val = hint | (hint << RST_REASON_SHIFT) | RST_REASON_BIT;
components/esp_system/port/soc/esp32h21/system_internal.c
+2 -2
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@@ -31,7 +31,7 @@
// TODO: [ESP32H21] IDF-11900, IDF-11911
void IRAM_ATTR esp_system_reset_modules_on_exit(void)
void esp_system_reset_modules_on_exit(void)
{
// Flush any data left in UART FIFOs before reset the UART peripheral
for (int i = 0; i < SOC_UART_HP_NUM; ++i) {
@@ -88,7 +88,7 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void)
* core are already stopped. Stalls other core, resets hardware,
* triggers restart.
*/
void IRAM_ATTR esp_restart_noos(void)
void esp_restart_noos(void)
{
// Disable interrupts
rv_utils_intr_global_disable();
components/esp_system/port/soc/esp32h4/reset_reason.c
+1 -1
View File
@@ -93,7 +93,7 @@ esp_reset_reason_t esp_reset_reason(void)
#define RST_REASON_SHIFT 16
/* in IRAM, can be called from panic handler */
void IRAM_ATTR esp_reset_reason_set_hint(esp_reset_reason_t hint)
void esp_reset_reason_set_hint(esp_reset_reason_t hint)
{
assert((hint & (~RST_REASON_MASK)) == 0);
uint32_t val = hint | (hint << RST_REASON_SHIFT) | RST_REASON_BIT;
components/esp_system/port/soc/esp32h4/system_internal.c
+2 -2
View File
@@ -25,7 +25,7 @@
#include "esp32h4/rom/cache.h"
// TODO: IDF-11911 need refactor
void IRAM_ATTR esp_system_reset_modules_on_exit(void)
void esp_system_reset_modules_on_exit(void)
{
// Flush any data left in UART FIFOs before reset the UART peripheral
for (int i = 0; i < SOC_UART_HP_NUM; ++i) {
@@ -80,7 +80,7 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void)
* core are already stopped. Stalls other core, resets hardware,
* triggers restart.
*/
void IRAM_ATTR esp_restart_noos(void)
void esp_restart_noos(void)
{
// Disable interrupts
rv_utils_intr_global_disable();
components/esp_system/port/soc/esp32p4/clk.c
+1
View File
@@ -78,6 +78,7 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src);
static const char *TAG = "clk";
// This function must be allocated in IRAM.
void IRAM_ATTR esp_rtc_init(void)
{
#if SOC_PMU_SUPPORTED
components/esp_system/port/soc/esp32p4/reset_reason.c
+1 -1
View File
@@ -104,7 +104,7 @@ esp_reset_reason_t esp_reset_reason(void)
#define RST_REASON_SHIFT 16
/* in IRAM, can be called from panic handler */
void IRAM_ATTR esp_reset_reason_set_hint(esp_reset_reason_t hint)
void esp_reset_reason_set_hint(esp_reset_reason_t hint)
{
assert((hint & (~RST_REASON_MASK)) == 0);
uint32_t val = hint | (hint << RST_REASON_SHIFT) | RST_REASON_BIT;
components/esp_system/port/soc/esp32p4/system_internal.c
+2 -2
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@@ -33,7 +33,7 @@
#include "hal/dw_gdma_ll.h"
#include "hal/dma2d_ll.h"
void IRAM_ATTR esp_system_reset_modules_on_exit(void)
void esp_system_reset_modules_on_exit(void)
{
// Flush any data left in UART FIFOs
for (int i = 0; i < SOC_UART_HP_NUM; ++i) {
@@ -140,7 +140,7 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void)
* core are already stopped. Stalls other core, resets hardware,
* triggers restart.
*/
void IRAM_ATTR esp_restart_noos(void)
void esp_restart_noos(void)
{
// Disable interrupts
rv_utils_intr_global_disable();
components/esp_system/port/soc/esp32s2/reset_reason.c
+1 -1
View File
@@ -86,7 +86,7 @@ esp_reset_reason_t esp_reset_reason(void)
#define RST_REASON_SHIFT 16
/* in IRAM, can be called from panic handler */
void IRAM_ATTR esp_reset_reason_set_hint(esp_reset_reason_t hint)
void esp_reset_reason_set_hint(esp_reset_reason_t hint)
{
assert((hint & (~RST_REASON_MASK)) == 0);
uint32_t val = hint | (hint << RST_REASON_SHIFT) | RST_REASON_BIT;
components/esp_system/port/soc/esp32s2/system_internal.c
+2 -2
View File
@@ -30,7 +30,7 @@
extern int _bss_end;
void IRAM_ATTR esp_system_reset_modules_on_exit(void)
void esp_system_reset_modules_on_exit(void)
{
// Flush any data left in UART FIFOs before reset the UART peripheral
for (int i = 0; i < SOC_UART_HP_NUM; ++i) {
@@ -64,7 +64,7 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void)
* core are already stopped. Stalls other core, resets hardware,
* triggers restart.
*/
void IRAM_ATTR esp_restart_noos(void)
void esp_restart_noos(void)
{
// Disable interrupts
esp_cpu_intr_disable(0xFFFFFFFF);
components/esp_system/port/soc/esp32s3/apb_backup_dma.c
+5 -4
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@@ -1,18 +1,19 @@
/*
* SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2019-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/soc_caps.h"
#include "esp_attr.h"
#include "esp_private/esp_system_attr.h"
#include "freertos/FreeRTOS.h"
#include "freertos/portmacro.h"
#include "esp32s3/rom/apb_backup_dma.h"
#include "sdkconfig.h"
static portMUX_TYPE s_apb_backup_dma_mutex = portMUX_INITIALIZER_UNLOCKED;
static void IRAM_ATTR apb_backup_dma_lock(void)
static void ESP_SYSTEM_IRAM_ATTR apb_backup_dma_lock(void)
{
if (xPortInIsrContext()) {
portENTER_CRITICAL_ISR(&s_apb_backup_dma_mutex);
@@ -21,7 +22,7 @@ static void IRAM_ATTR apb_backup_dma_lock(void)
}
}
static void IRAM_ATTR apb_backup_dma_unlock(void)
static void ESP_SYSTEM_IRAM_ATTR apb_backup_dma_unlock(void)
{
if (xPortInIsrContext()) {
portEXIT_CRITICAL_ISR(&s_apb_backup_dma_mutex);
components/esp_system/port/soc/esp32s3/clk.c
+1 -1
View File
@@ -340,7 +340,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)
}
// Workaround for bootloader not calibrated well issue.
// Placed in IRAM because disabling BBPLL may influence the cache
// Placed in IRAM because disabling BBPLL may influence the cache.
static void IRAM_ATTR NOINLINE_ATTR recalib_bbpll(void)
{
rtc_cpu_freq_config_t old_config;
components/esp_system/port/soc/esp32s3/reset_reason.c
+1 -1
View File
@@ -88,7 +88,7 @@ esp_reset_reason_t esp_reset_reason(void)
#define RST_REASON_SHIFT 16
/* in IRAM, can be called from panic handler */
void IRAM_ATTR esp_reset_reason_set_hint(esp_reset_reason_t hint)
void esp_reset_reason_set_hint(esp_reset_reason_t hint)
{
assert((hint & (~RST_REASON_MASK)) == 0);
uint32_t val = hint | (hint << RST_REASON_SHIFT) | RST_REASON_BIT;
components/esp_system/port/soc/esp32s3/system_internal.c
+2 -2
View File
@@ -31,7 +31,7 @@
extern int _bss_end;
void IRAM_ATTR esp_system_reset_modules_on_exit(void)
void esp_system_reset_modules_on_exit(void)
{
// Flush any data left in UART FIFOs before reset the UART peripheral
for (int i = 0; i < SOC_UART_HP_NUM; ++i) {
@@ -67,7 +67,7 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void)
* core are already stopped. Stalls other core, resets hardware,
* triggers restart.
*/
void IRAM_ATTR esp_restart_noos(void)
void esp_restart_noos(void)
{
// Disable interrupts
esp_cpu_intr_disable(0xFFFFFFFF);