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Merge branch 'fix/for_cache_after_p4_wb_loss_issue_v5.4' into 'release/v5.4'

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fix(esp_rom): avoid critical issue in writeback v5.4

See merge request espressif/esp-idf!48816
This commit is contained in:
Jiang Jiang Jian
2026-05-28 19:27:21 +08:00
parent 105f2de109 592d09f219
commit e5c34b1e8b
17 changed files with 424 additions and 120 deletions
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components/esp_rom/esp32c61/Kconfig.soc_caps.in
+4
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@@ -106,3 +106,7 @@ config ESP_ROM_HAS_OUTPUT_PUTC_FUNC
config ESP_ROM_CACHE_WB_INVLD_LOW_RANGE
bool
default y
config ESP_ROM_CACHE_WRITEBACK_NEEDS_SYNC_TWICE_NO_MAP
bool
default y
components/esp_rom/esp32c61/esp_rom_caps.h
+1
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@@ -32,3 +32,4 @@
#define ESP_ROM_USB_OTG_NUM (-1) // No USB_OTG CDC in the ROM, set -1 for Kconfig usage.
#define ESP_ROM_HAS_OUTPUT_PUTC_FUNC (1) // ROM has esp_rom_output_putc (or ets_write_char_uart)
#define ESP_ROM_CACHE_WB_INVLD_LOW_RANGE (1) // ROM `Cache_WriteBack_Addr` and `Cache_Invalidate_Addr` can only access low vaddr parts
#define ESP_ROM_CACHE_WRITEBACK_NEEDS_SYNC_TWICE_NO_MAP (1) // ROM cache writeback related needs patch to avoid sync loss, no map parameter
components/esp_rom/esp32c61/include/esp32c61/rom/cache.h
+2
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@@ -49,6 +49,8 @@ typedef enum {
CACHE_SYNC_WRITEBACK_INVALIDATE = BIT(3),
} cache_sync_t;
#define CACHE_MAP_FLASH_CACHE BIT(4)
typedef enum {
CACHE_SIZE_HALF = 0, /*!< 8KB for icache and dcache */
CACHE_SIZE_FULL = 1, /*!< 16KB for icache and dcache */
components/esp_rom/esp32c61/ld/esp32c61.rom.ld
+4 -4
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -195,11 +195,11 @@ Cache_Op_Addr = 0x40000630;
/*Cache_Invalidate_Addr = 0x40000634; rom version API has issue that unable to access higher vaddr range, use IDF patch */
Cache_Clean_Addr = 0x40000638;
/*Cache_WriteBack_Addr = 0x4000063c; rom version API has issue that unable to access higher vaddr range, use IDF patch */
Cache_WriteBack_Invalidate_Addr = 0x40000640;
PROVIDE( Cache_WriteBack_Invalidate_Addr = 0x40000640 );
Cache_Invalidate_All = 0x40000644;
Cache_Clean_All = 0x40000648;
Cache_WriteBack_All = 0x4000064c;
Cache_WriteBack_Invalidate_All = 0x40000650;
PROVIDE( Cache_WriteBack_All = 0x4000064c );
PROVIDE( Cache_WriteBack_Invalidate_All = 0x40000650 );
Cache_Mask_All = 0x40000654;
Cache_UnMask_Dram0 = 0x40000658;
Cache_Suspend_Autoload = 0x4000065c;