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Merge branch 'bugfix/idf_13957_v6.0' into 'release/v6.0'

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bugfix: fix wifi loss packet and missing interrupt issues when switching root clock source

See merge request espressif/esp-idf!48432
This commit is contained in:
Jiang Jiang Jian
2026-05-15 12:32:25 +08:00
parent 36f3329a23 51775582e6
commit e5191e1612
8 changed files with 40 additions and 32 deletions
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components/esp_hw_support/lowpower/port/esp32c5/sleep_clock.c
+2 -16
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -53,6 +53,7 @@ esp_err_t sleep_clock_system_retention_init(void *arg)
#if SOC_PM_SUPPORT_PMU_MODEM_STATE && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP && CONFIG_XTAL_FREQ_AUTO
uint32_t xtal_freq_mhz = (uint32_t)rtc_clk_xtal_freq_get();
if (xtal_freq_mhz == SOC_XTAL_FREQ_48M) {
/* For the 48 MHz main XTAL, we need regdma to configured BBPLL by exec
* the PHY_I2C_MST_CMD_TYPE_BBPLL_CFG command from PHY i2c master
* command memory */
@@ -69,21 +70,6 @@ esp_err_t sleep_clock_system_retention_init(void *arg)
}
#endif
#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
/* On ESP32-C5 ECO1, clearing BIT(31) of PCR_FPGA_DEBUG_REG (it's
* located in TOP domain) is used to fix the issue where the modem
* module fails to transmit and receive packets due to the loss of The
* modem root clock caused by automatic clock gating during soc root
* clock source switching. For detailed information, refer to IDF-11064 */
if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 1)) {
const static sleep_retention_entries_config_t rootclk_workaround[] = {
[0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(9), PCR_FPGA_DEBUG_REG, PCR_FPGA_DEBUG_REG, 1, 0, 0), .owner = ENTRY(0) | ENTRY(1) }
};
err = sleep_retention_entries_create(rootclk_workaround, ARRAY_SIZE(rootclk_workaround), 1, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);
ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for modem root clock workaround, 1 level priority");
}
#endif
ESP_LOGI(TAG, "System Power, Clock and Reset sleep retention initialization");
return ESP_OK;
}
components/esp_hw_support/port/esp32c5/include/soc/rtc.h
+10
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@@ -338,6 +338,16 @@ void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config);
*/
void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config);
#if SOC_CLK_ROOT_CLK_SWITCH_PROTECT
/**
* @brief Enable/disable root clock auto gating bypass for 240M/160M PLL switch
* @param new_config Target cpu frequency config
* @param old_config Current cpu frequency config
* @param enable true to enable, false to disable
*/
void rtc_clk_root_clk_switch_protect(const rtc_cpu_freq_config_t *new_config, const rtc_cpu_freq_config_t *old_config, bool enable);
#endif
/**
* @brief Get the currently used CPU frequency configuration
* @param[out] out_config Output, CPU frequency configuration structure
components/esp_hw_support/port/esp32c5/rtc_clk.c
+10
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@@ -350,6 +350,16 @@ static void rtc_clk_update_pll_state_on_cpu_src_switching_end(soc_cpu_clk_src_t
}
}
#if SOC_CLK_ROOT_CLK_SWITCH_PROTECT
void rtc_clk_root_clk_switch_protect(const rtc_cpu_freq_config_t *new_config, const rtc_cpu_freq_config_t *old_config, bool enable)
{
if ((new_config->source == SOC_CPU_CLK_SRC_PLL_F160M && old_config->source == SOC_CPU_CLK_SRC_PLL_F240M) ||
(new_config->source == SOC_CPU_CLK_SRC_PLL_F240M && old_config->source == SOC_CPU_CLK_SRC_PLL_F160M)) {
clk_ll_soc_root_clk_auto_gating_bypass(enable);
}
}
#endif
void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config)
{
soc_cpu_clk_src_t old_cpu_clk_src = clk_ll_cpu_get_src();
components/esp_hw_support/sleep_modes.c
-6
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@@ -679,9 +679,6 @@ static SLEEP_FN_ATTR void misc_modules_sleep_prepare(uint32_t sleep_flags, bool
}
#endif
#if CONFIG_MAC_BB_PD
# if CONFIG_IDF_TARGET_ESP32C5
clk_ll_soc_root_clk_auto_gating_bypass(false);
# endif
mac_bb_power_down_cb_execute();
#endif
#if CONFIG_IDF_TARGET_ESP32
@@ -757,9 +754,6 @@ static SLEEP_FN_ATTR void misc_modules_wake_prepare(uint32_t sleep_flags)
#endif
#if CONFIG_MAC_BB_PD
mac_bb_power_up_cb_execute();
# if CONFIG_IDF_TARGET_ESP32C5
clk_ll_soc_root_clk_auto_gating_bypass(true);
# endif
#endif
#if REGI2C_LL_ANA_CALI_PD_WORKAROUND
regi2c_analog_cali_reg_write();