Merge branch 'debug/idf-15875-fix_v5.5' into 'release/v5.5'

fix(psram): suspend external cache during CPU freq switch on esp32p4 (v5.5)

See merge request espressif/esp-idf!51686

components/esp_system/port/soc/esp32p4/clk.c

@@ -64,6 +64,7 @@
 #include "esp_private/periph_ctrl.h"
 #include "esp_private/esp_clk.h"
 #include "esp_private/esp_pmu.h"
+#include "esp_private/esp_cache_private.h"
 #include "esp_rom_uart.h"
 #include "esp_rom_sys.h"
 
@@ -87,6 +88,27 @@ void IRAM_ATTR esp_rtc_init(void)
 #endif  //SOC_PMU_SUPPORTED
 }
 
+/*
+ * Perform the CPU frequency switch with the external memory (PSRAM) cache
+ * suspended. The frequency switch stalls the HP_ROOT clock and toggles PLL /
+ * clock gating; when the switch code runs from PSRAM-XIP, a cache-coherency
+ * transient during the switch can corrupt the external .bss region. Suspending
+ * the external-memory cache for the duration of the switch keeps the CPU off
+ * the XIP path, isolating the two.
+ * Must be IRAM-resident because it runs while the external cache is suspended.
+ */
+static void IRAM_ATTR esp_clk_cpu_freq_set_config_isolated(const rtc_cpu_freq_config_t *config)
+{
+    /* esp_cache_utils.c is not built for pure-ram apps. */
+#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
+    esp_cache_suspend_ext_mem_cache();
+#endif
+    rtc_clk_cpu_freq_set_config(config);
+#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
+    esp_cache_resume_ext_mem_cache();
+#endif
+}
+
 __attribute__((weak)) void esp_clk_init(void)
 {
     assert(rtc_clk_xtal_freq_get() == SOC_XTAL_FREQ_40M);
@@ -148,7 +170,7 @@ __attribute__((weak)) void esp_clk_init(void)
     }
 
     if (res)  {
-        rtc_clk_cpu_freq_set_config(&new_config);
+        esp_clk_cpu_freq_set_config_isolated(&new_config);
     }
 
     // Re calculate the ccount to make time calculation correct.