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Merge branch 'feature/efuse_s3_adds_psram_cap_bit_v5.3' into 'release/v5.3'

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feat(efuse): Adds 3 bit for PSRAM_CAP efuse field (v5.3)

See merge request espressif/esp-idf!35121
This commit is contained in:
morris
2024-12-09 10:20:57 +08:00
parent c7529d7c94 524dbd1fee
commit e3a628e1db
5 changed files with 44 additions and 19 deletions
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components/soc/esp32s3/include/soc/efuse_reg.h
+20 -6
View File
@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -553,7 +553,7 @@ extern "C" {
#define EFUSE_DIS_DIRECT_BOOT_V 0x00000001U
#define EFUSE_DIS_DIRECT_BOOT_S 1
/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO; bitpos: [2]; default: 0;
* Selectes the default UART print channel. 0: UART0. 1: UART1.
* Selects the default UART print channel. 0: UART0. 1: UART1.
*/
#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT (BIT(2))
#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S)
@@ -917,13 +917,27 @@ extern "C" {
#define EFUSE_DIG_DBIAS_HVT_M (EFUSE_DIG_DBIAS_HVT_V << EFUSE_DIG_DBIAS_HVT_S)
#define EFUSE_DIG_DBIAS_HVT_V 0x0000001FU
#define EFUSE_DIG_DBIAS_HVT_S 11
/** EFUSE_RESERVED_1_176 : R; bitpos: [22:16]; default: 0;
/** EFUSE_RESERVED_1_176 : R; bitpos: [18:16]; default: 0;
* reserved
*/
#define EFUSE_RESERVED_1_176 0x0000007FU
#define EFUSE_RESERVED_1_176 0x00000007U
#define EFUSE_RESERVED_1_176_M (EFUSE_RESERVED_1_176_V << EFUSE_RESERVED_1_176_S)
#define EFUSE_RESERVED_1_176_V 0x0000007FU
#define EFUSE_RESERVED_1_176_V 0x00000007U
#define EFUSE_RESERVED_1_176_S 16
/** EFUSE_PSRAM_CAP_3 : R; bitpos: [19]; default: 0;
* PSRAM capacity bit 3
*/
#define EFUSE_PSRAM_CAP_3 (BIT(19))
#define EFUSE_PSRAM_CAP_3_M (EFUSE_PSRAM_CAP_3_V << EFUSE_PSRAM_CAP_3_S)
#define EFUSE_PSRAM_CAP_3_V 0x00000001U
#define EFUSE_PSRAM_CAP_3_S 19
/** EFUSE_RESERVED_1_180 : R; bitpos: [22:20]; default: 0;
* reserved
*/
#define EFUSE_RESERVED_1_180 0x00000007U
#define EFUSE_RESERVED_1_180_M (EFUSE_RESERVED_1_180_V << EFUSE_RESERVED_1_180_S)
#define EFUSE_RESERVED_1_180_V 0x00000007U
#define EFUSE_RESERVED_1_180_S 20
/** EFUSE_WAFER_VERSION_MINOR_HI : R; bitpos: [23]; default: 0;
* WAFER_VERSION_MINOR most significant bit
*/
@@ -2638,7 +2652,7 @@ extern "C" {
#define EFUSE_CLK_EN_S 16
/** EFUSE_CONF_REG register
* eFuse operation mode configuraiton register
* eFuse operation mode configuration register
*/
#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc)
/** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0;
components/soc/esp32s3/include/soc/efuse_struct.h
+13 -5
View File
@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -423,7 +423,7 @@ typedef union {
*/
uint32_t dis_direct_boot:1;
/** dis_usb_serial_jtag_rom_print : RO; bitpos: [2]; default: 0;
* Selectes the default UART print channel. 0: UART0. 1: UART1.
* Selects the default UART print channel. 0: UART0. 1: UART1.
*/
uint32_t dis_usb_serial_jtag_rom_print:1;
/** flash_ecc_mode : RO; bitpos: [3]; default: 0;
@@ -672,10 +672,18 @@ typedef union {
* BLOCK1 digital dbias when hvt
*/
uint32_t dig_dbias_hvt:5;
/** reserved_1_176 : R; bitpos: [22:16]; default: 0;
/** reserved_1_176 : R; bitpos: [18:16]; default: 0;
* reserved
*/
uint32_t reserved_1_176:7;
uint32_t reserved_1_176:3;
/** psram_cap_3 : R; bitpos: [19]; default: 0;
* PSRAM capacity bit 3
*/
uint32_t psram_cap_3:1;
/** reserved_1_180 : R; bitpos: [22:20]; default: 0;
* reserved
*/
uint32_t reserved_1_180:3;
/** wafer_version_minor_hi : R; bitpos: [23]; default: 0;
* WAFER_VERSION_MINOR most significant bit
*/
@@ -2163,7 +2171,7 @@ typedef union {
} efuse_clk_reg_t;
/** Type of conf register
* eFuse operation mode configuraiton register
* eFuse operation mode configuration register
*/
typedef union {
struct {