feat(esp_hw_support): use non-lock regi2c fast-up cpll/mpll enable process after sleep wakeup

components/esp_hw_support/clk_ctrl_os.c

@@ -193,7 +193,7 @@ esp_err_t IRAM_ATTR periph_rtc_mpll_freq_set(uint32_t expt_freq_hz, uint32_t *re
      * But when more than one peripheral refers MPLL, its frequency is not allowed to change once it is set */
     if (s_cur_mpll_freq_hz == 0 || s_mpll_ref_cnt < 2) {
         uint32_t xtal_freq_mhz = clk_ll_xtal_load_freq_mhz();
-        rtc_clk_mpll_configure(xtal_freq_mhz, expt_freq_hz / MHZ);
+        rtc_clk_mpll_configure(xtal_freq_mhz, expt_freq_hz / MHZ, false);
         s_cur_mpll_freq_hz = clk_ll_mpll_get_freq_mhz(xtal_freq_mhz) * MHZ;
     } else {
         ret = ESP_ERR_INVALID_STATE;

components/esp_hw_support/include/esp_private/regi2c_ctrl.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -70,7 +70,8 @@ extern "C" {
 #define regi2c_ctrl_read_reg_mask    regi2c_read_reg_mask_raw
 #define regi2c_ctrl_write_reg        regi2c_write_reg_raw
 #define regi2c_ctrl_write_reg_mask   regi2c_write_reg_mask_raw
-
+#define REGI2C_ENTER_CRITICAL()
+#define REGI2C_EXIT_CRITICAL()
 #else
 
 /* Access internal registers, don't use in application */
@@ -82,7 +83,8 @@ void regi2c_ctrl_write_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add,
 /* enter the critical section that protects internal registers. Don't use it in SDK. Use the functions above. */
 void regi2c_enter_critical(void);
 void regi2c_exit_critical(void);
-
+#define REGI2C_ENTER_CRITICAL()  regi2c_enter_critical()
+#define REGI2C_EXIT_CRITICAL()   regi2c_exit_critical()
 #endif // NON_OS_BUILD
 
 /* Convenience macros for the above functions, these use register definitions

components/esp_hw_support/include/esp_private/rtc_clk.h

@@ -58,8 +58,9 @@ void rtc_clk_mpll_disable(void);
  *
  * @param[in] xtal_freq  XTAL frequency
  * @param[in] mpll_freq  MPLL frequency
+ * @param[in] thread_safe Set true if called from thread safe context, which will save the time of taking spin lock.
  */
-void rtc_clk_mpll_configure(uint32_t xtal_freq, uint32_t mpll_freq);
+void rtc_clk_mpll_configure(uint32_t xtal_freq, uint32_t mpll_freq, bool thread_safe);
 
 /**
  * Get the MPLL frequency

components/esp_hw_support/port/esp32p4/pmu_sleep.c

@@ -466,7 +466,7 @@ TCM_IRAM_ATTR bool pmu_sleep_finish(bool dslp)
 
     if (s_mpll_freq_mhz_before_sleep && !dslp) {
         rtc_clk_mpll_enable();
-        rtc_clk_mpll_configure(clk_hal_xtal_get_freq_mhz(), s_mpll_freq_mhz_before_sleep);
+        rtc_clk_mpll_configure(clk_hal_xtal_get_freq_mhz(), s_mpll_freq_mhz_before_sleep, true);
 #if CONFIG_SPIRAM
         if (!s_pmu_sleep_regdma_backup_enabled) {
             // MSPI2 and MSPI3 share the register for core clock. So we only set MSPI2 here.

components/esp_hw_support/port/esp32p4/rtc_clk.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -585,10 +585,17 @@ TCM_IRAM_ATTR void rtc_clk_mpll_enable(void)
     clk_ll_mpll_enable();
 }
 
-void rtc_clk_mpll_configure(uint32_t xtal_freq, uint32_t mpll_freq)
+void rtc_clk_mpll_configure(uint32_t xtal_freq, uint32_t mpll_freq, bool thread_safe)
 {
     /* Analog part */
-    ANALOG_CLOCK_ENABLE();
+    if (thread_safe) {
+        _regi2c_ctrl_ll_master_enable_clock(true);
+    } else {
+        ANALOG_CLOCK_ENABLE();
+#if !BOOTLOADER_BUILD
+        regi2c_enter_critical();
+#endif
+    }
     /* MPLL calibration start */
     regi2c_ctrl_ll_mpll_calibration_start();
     clk_ll_mpll_set_config(mpll_freq, xtal_freq);
@@ -596,8 +603,15 @@ void rtc_clk_mpll_configure(uint32_t xtal_freq, uint32_t mpll_freq)
     while(!regi2c_ctrl_ll_mpll_calibration_is_done());
     /* MPLL calibration stop */
     regi2c_ctrl_ll_mpll_calibration_stop();
-    ANALOG_CLOCK_DISABLE();
 
+    if (thread_safe) {
+        _regi2c_ctrl_ll_master_enable_clock(false);
+    } else {
+#if !BOOTLOADER_BUILD
+        regi2c_exit_critical();
+#endif
+        ANALOG_CLOCK_DISABLE();
+    }
     s_cur_mpll_freq = mpll_freq;
 }