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feat(gpio): add IO hold support for Deep-sleep for ESP32-P4 ECO5

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This commit is contained in:
Song Ruo Jing
2025-11-12 22:28:03 +08:00
parent c4f9d7177c
commit e28ff72154
37 changed files with 117 additions and 147 deletions
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components/soc/esp32/include/soc/Kconfig.soc_caps.in
-4
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@@ -355,10 +355,6 @@ config SOC_GPIO_CLOCKOUT_CHANNEL_NUM
int
default 3
config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
bool
default y
config SOC_I2C_NUM
int
default 2
components/soc/esp32/include/soc/soc_caps.h
-3
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@@ -199,9 +199,6 @@
#define SOC_GPIO_CLOCKOUT_BY_IO_MUX (1)
#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3)
// RTC_IOs and DIG_IOs can be hold during deep sleep and after waking up
#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1)
/*-------------------------- I2C CAPS ----------------------------------------*/
// ESP32 has 2 I2C
#define SOC_I2C_NUM (2U)
components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
-4
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@@ -323,10 +323,6 @@ config SOC_GPIO_CLOCKOUT_CHANNEL_NUM
int
default 3
config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
bool
default y
config SOC_I2C_NUM
int
default 1
components/soc/esp32c2/include/soc/soc_caps.h
-3
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@@ -149,9 +149,6 @@
#define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX (1)
#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3)
// "RTC"_IOs and DIG_IOs can be hold during deep sleep and after waking up
#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1)
/*-------------------------- I2C CAPS ----------------------------------------*/
// ESP32-C2 has 1 I2C
#define SOC_I2C_NUM (1U)
components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
-4
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@@ -419,10 +419,6 @@ config SOC_GPIO_CLOCKOUT_CHANNEL_NUM
int
default 3
config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
bool
default y
config SOC_I2C_NUM
int
default 1
components/soc/esp32c3/include/soc/soc_caps.h
-3
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@@ -188,9 +188,6 @@
#define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX (1)
#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3)
// "RTC"_IOs and DIG_IOs can be hold during deep sleep and after waking up
#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1)
/*-------------------------- I2C CAPS ----------------------------------------*/
// ESP32-C3 has 1 I2C
#define SOC_I2C_NUM (1U)
components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
-4
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@@ -579,10 +579,6 @@ config SOC_GPIO_SUPPORT_FORCE_HOLD
bool
default y
config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
bool
default y
config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
bool
default y
components/soc/esp32c5/include/soc/soc_caps.h
-2
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@@ -237,8 +237,6 @@
// Support to force hold all IOs
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
// LP_IOs and DIG_IOs can be hold during deep sleep and after waking up
#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1)
// Support to hold a single digital I/O when the digital domain is powered off
#define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1)
components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
-4
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@@ -511,10 +511,6 @@ config SOC_GPIO_SUPPORT_FORCE_HOLD
bool
default y
config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
bool
default y
config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
bool
default y
components/soc/esp32c6/include/soc/soc_caps.h
-2
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@@ -215,8 +215,6 @@
// Support to force hold all IOs
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
// LP_IOs and DIG_IOs can be hold during deep sleep and after waking up
#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1)
// Support to hold a single digital I/O when the digital domain is powered off
#define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1)
components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
-4
View File
@@ -455,10 +455,6 @@ config SOC_GPIO_SUPPORT_FORCE_HOLD
bool
default y
config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
bool
default y
config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
bool
default y
components/soc/esp32c61/include/soc/soc_caps.h
-2
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@@ -196,8 +196,6 @@
// Support to force hold all IOs
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
// "LP"_IOs and DIG_IOs can be hold during deep sleep and after waking up
#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1)
// Support to hold a single digital I/O when the digital domain is powered off
#define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1)
components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
-4
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@@ -531,10 +531,6 @@ config SOC_GPIO_SUPPORT_FORCE_HOLD
bool
default y
config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
bool
default y
config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
bool
default y
components/soc/esp32h2/include/soc/soc_caps.h
-2
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@@ -240,8 +240,6 @@
// Support to force hold all IOs
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
// LP_IOs and DIG_IOs can be hold during deep sleep and after waking up
#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1)
// Support to hold a single digital I/O when the digital domain is powered off
#define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1)
components/soc/esp32h21/include/soc/Kconfig.soc_caps.in
-4
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@@ -387,10 +387,6 @@ config SOC_GPIO_SUPPORT_FORCE_HOLD
bool
default y
config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
bool
default y
config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
bool
default y
components/soc/esp32h21/include/soc/soc_caps.h
-2
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@@ -220,8 +220,6 @@
// Support to force hold all IOs
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
// LP_IOs and DIG_IOs can be hold during deep sleep and after waking up
#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1)
// Support to hold a single digital I/O when the digital domain is powered off
#define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1)
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
+8 -4
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@@ -695,6 +695,14 @@ config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
hex
default 0x007FFFFFFFFF0000
config SOC_GPIO_SUPPORT_FORCE_HOLD
bool
default y
config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
bool
default y
config SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX
bool
default y
@@ -715,10 +723,6 @@ config SOC_DEBUG_PROBE_MAX_OUTPUT_WIDTH
int
default 16
config SOC_GPIO_SUPPORT_FORCE_HOLD
bool
default y
config SOC_RTCIO_PIN_COUNT
int
default 16
components/soc/esp32p4/include/soc/soc_caps.h
+5 -3
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@@ -265,6 +265,11 @@
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_16~GPIO_NUM_54)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x007FFFFFFFFF0000ULL
// Support to force hold all IOs
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
// Support to hold a single digital I/O when the digital domain is powered off
#define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1) // Supported only on ESP32P4 rev >= 3.0 (see DIG-399)
// The Clock Out signal is route to the pin by GPIO matrix
#define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX (1)
#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (2)
@@ -273,9 +278,6 @@
#define SOC_DEBUG_PROBE_NUM_UNIT (1U) // Number of debug probe units
#define SOC_DEBUG_PROBE_MAX_OUTPUT_WIDTH (16) // Maximum width of the debug probe output in each unit
// Support to force hold all IOs
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
/*-------------------------- RTCIO CAPS --------------------------------------*/
#define SOC_RTCIO_PIN_COUNT 16
#define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1 /* This macro indicates that the target has separate RTC IOMUX hardware feature,
components/soc/esp32p4/register/hw_ver3/soc/hp_system_struct.h
+1 -33
View File
@@ -413,37 +413,6 @@ typedef union {
} hp_crypto_ctrl_reg_t;
/** Group: HP GPIO O HOLD CTRL0 REG */
/** Type of gpio_o_hold_ctrl0 register
* NA
*/
typedef union {
struct {
/** reg_gpio_0_hold_low : R/W; bitpos: [31:0]; default: 0;
* hold control for gpio47~16
*/
uint32_t reg_gpio_0_hold_low:32;
};
uint32_t val;
} hp_gpio_o_hold_ctrl0_reg_t;
/** Group: HP GPIO O HOLD CTRL1 REG */
/** Type of gpio_o_hold_ctrl1 register
* NA
*/
typedef union {
struct {
/** reg_gpio_0_hold_high : R/W; bitpos: [8:0]; default: 0;
* hold control for gpio56~48
*/
uint32_t reg_gpio_0_hold_high:9;
uint32_t reserved_9:23;
};
uint32_t val;
} hp_gpio_o_hold_ctrl1_reg_t;
/** Group: HP SYS RDN ECO CS REG */
/** Type of sys_rdn_eco_cs register
* NA
@@ -2149,8 +2118,7 @@ typedef struct hp_system_dev_t {
volatile hp_cpu_corestalled_st_reg_t cpu_corestalled_st;
uint32_t reserved_068[2];
volatile hp_crypto_ctrl_reg_t crypto_ctrl;
volatile hp_gpio_o_hold_ctrl0_reg_t gpio_o_hold_ctrl0;
volatile hp_gpio_o_hold_ctrl1_reg_t gpio_o_hold_ctrl1;
uint32_t reserved_074[2];
volatile hp_sys_rdn_eco_cs_reg_t sys_rdn_eco_cs;
volatile hp_cache_apb_postw_en_reg_t cache_apb_postw_en;
volatile hp_l2_mem_subsize_reg_t l2_mem_subsize;
components/soc/esp32p4/register/hw_ver3/soc/lp_iomux_struct.h
+1 -17
View File
@@ -114,22 +114,6 @@ typedef union {
} lp_iomux_ext_wakeup0_sel_reg_t;
/** Group: lp_pad_hold */
/** Type of lp_pad_hold register
* Reserved
*/
typedef union {
struct {
/** reg_lp_gpio_hold : R/W; bitpos: [15:0]; default: 0;
* Reserved
*/
uint32_t reg_lp_gpio_hold:16;
uint32_t reserved_16:16;
};
uint32_t val;
} lp_iomux_lp_pad_hold_reg_t;
/** Group: lp_pad_hys */
/** Type of lp_pad_hys register
* Reserved
@@ -151,7 +135,7 @@ typedef struct lp_iomux_dev_t {
volatile lp_iomux_ver_date_reg_t ver_date;
volatile lp_iomux_pad_reg_t pad[16];
volatile lp_iomux_ext_wakeup0_sel_reg_t ext_wakeup0_sel;
volatile lp_iomux_lp_pad_hold_reg_t lp_pad_hold;
uint32_t reserved_04c;
volatile lp_iomux_lp_pad_hys_reg_t lp_pad_hys;
} lp_iomux_dev_t;
components/soc/esp32s2/include/soc/Kconfig.soc_caps.in
-4
View File
@@ -415,10 +415,6 @@ config SOC_GPIO_CLOCKOUT_CHANNEL_NUM
int
default 3
config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
bool
default y
config SOC_DEDIC_GPIO_HAS_INTERRUPT
bool
default y
components/soc/esp32s2/include/soc/soc_caps.h
-3
View File
@@ -190,9 +190,6 @@
#define SOC_GPIO_CLOCKOUT_BY_IO_MUX (1)
#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3)
// RTC_IOs and DIG_IOs can be hold during deep sleep and after waking up
#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1)
/*-------------------------- Dedicated GPIO CAPS ---------------------------------------*/
#define SOC_DEDIC_GPIO_HAS_INTERRUPT (1) /*!< Dedicated GPIO has its own interrupt source */
components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
-4
View File
@@ -479,10 +479,6 @@ config SOC_GPIO_CLOCKOUT_CHANNEL_NUM
int
default 3
config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
bool
default y
config SOC_I2C_NUM
int
default 2
components/soc/esp32s3/include/soc/soc_caps.h
-3
View File
@@ -201,9 +201,6 @@
#define SOC_GPIO_CLOCKOUT_BY_IO_MUX (1)
#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3)
// RTC_IOs and DIG_IOs can be hold during deep sleep and after waking up
#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1)
/*-------------------------- I2C CAPS ----------------------------------------*/
// ESP32-S3 has 2 I2C
#define SOC_I2C_NUM (2U)