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Merge branch 'feat/support_aes_pseudo_round_func_in_esp32h2_eco5_v5.3' into 'release/v5.3'

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Support AES and XTS-AES's pseudo round function in ESP32H2-ECO5 (v5.3)

See merge request espressif/esp-idf!36464
This commit is contained in:
Mahavir Jain
2025-01-24 14:40:00 +08:00
parent 8f20eac2df db588e04dd
commit e1a023e13d
35 changed files with 711 additions and 77 deletions
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components/hal/esp32h2/include/hal/aes_ll.h
+36 -1
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -12,6 +12,9 @@
#include "soc/pcr_struct.h"
#include "hal/aes_types.h"
#include "hal/efuse_hal.h"
#include "soc/chip_revision.h"
#ifdef __cplusplus
extern "C" {
#endif
@@ -241,6 +244,38 @@ static inline void aes_ll_interrupt_clear(void)
REG_WRITE(AES_INT_CLEAR_REG, 1);
}
/**
* @brief Enable the pseudo-round function during AES operations
*
* @param enable true to enable, false to disable
* @param base basic number of pseudo rounds, zero if disable
* @param increment increment number of pseudo rounds, zero if disable
* @param key_rng_cnt update frequency of the pseudo-key, zero if disable
*/
static inline void aes_ll_enable_pseudo_rounds(bool enable, uint8_t base, uint8_t increment, uint8_t key_rng_cnt)
{
REG_SET_FIELD(AES_PSEUDO_REG, AES_PSEUDO_EN, enable);
if (enable) {
REG_SET_FIELD(AES_PSEUDO_REG, AES_PSEUDO_BASE, base);
REG_SET_FIELD(AES_PSEUDO_REG, AES_PSEUDO_INC, increment);
REG_SET_FIELD(AES_PSEUDO_REG, AES_PSEUDO_RNG_CNT, key_rng_cnt);
} else {
REG_SET_FIELD(AES_PSEUDO_REG, AES_PSEUDO_BASE, 0);
REG_SET_FIELD(AES_PSEUDO_REG, AES_PSEUDO_INC, 0);
REG_SET_FIELD(AES_PSEUDO_REG, AES_PSEUDO_RNG_CNT, 0);
}
}
/**
* @brief Check if the pseudo round function is supported
* The AES pseudo round function is only avliable in chip version
* above 1.2 in ESP32-H2
*/
static inline bool aes_ll_is_pseudo_rounds_function_supported(void)
{
return ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 102);
}
#ifdef __cplusplus
}
components/hal/esp32h2/include/hal/spi_flash_encrypted_ll.h
+40 -3
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -11,6 +11,7 @@
******************************************************************************/
// The Lowlevel layer for SPI Flash Encryption.
#pragma once
#include <stdbool.h>
#include <string.h>
@@ -20,11 +21,14 @@
#include "soc/soc_caps.h"
#include "hal/assert.h"
#include "hal/efuse_hal.h"
#include "soc/chip_revision.h"
#ifdef __cplusplus
extern "C" {
#endif
/// Choose type of chip you want to encrypt manully
/// Choose type of chip you want to encrypt manually
typedef enum
{
FLASH_ENCRYPTION_MANU = 0, ///!< Manually encrypt the flash chip.
@@ -51,7 +55,7 @@ static inline void spi_flash_encrypt_ll_disable(void)
}
/**
* Choose type of chip you want to encrypt manully
* Choose type of chip you want to encrypt manually
*
* @param type The type of chip to be encrypted
*
@@ -146,6 +150,39 @@ static inline bool spi_flash_encrypt_ll_check(uint32_t address, uint32_t length)
return ((address % length) == 0) ? true : false;
}
/**
* @brief Enable the pseudo-round function during XTS-AES operations
*
* @param mode set the mode for pseudo rounds, zero to disable, with increasing security upto three.
* @param base basic number of pseudo rounds, zero if disable
* @param increment increment number of pseudo rounds, zero if disable
* @param key_rng_cnt update frequency of the pseudo-key, zero if disable
*/
static inline void spi_flash_encrypt_ll_enable_pseudo_rounds(uint8_t mode, uint8_t base, uint8_t increment, uint8_t key_rng_cnt)
{
REG_SET_FIELD(XTS_AES_PSEUDO_ROUND_CONF_REG(0), XTS_AES_MODE_PSEUDO, mode);
if (mode) {
REG_SET_FIELD(XTS_AES_PSEUDO_ROUND_CONF_REG(0), XTS_AES_PSEUDO_BASE, base);
REG_SET_FIELD(XTS_AES_PSEUDO_ROUND_CONF_REG(0), XTS_AES_PSEUDO_INC, increment);
REG_SET_FIELD(XTS_AES_PSEUDO_ROUND_CONF_REG(0), XTS_AES_PSEUDO_RNG_CNT, key_rng_cnt);
} else {
REG_SET_FIELD(XTS_AES_PSEUDO_ROUND_CONF_REG(0), XTS_AES_PSEUDO_BASE, 0);
REG_SET_FIELD(XTS_AES_PSEUDO_ROUND_CONF_REG(0), XTS_AES_PSEUDO_INC, 0);
REG_SET_FIELD(XTS_AES_PSEUDO_ROUND_CONF_REG(0), XTS_AES_PSEUDO_RNG_CNT, 0);
}
}
/**
* @brief Check if the pseudo round function is supported
* The XTS-AES pseudo round function is only avliable in chip version
* above 1.2 in ESP32-H2
*/
static inline bool spi_flash_encrypt_ll_is_pseudo_rounds_function_supported(void)
{
return ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 102);
}
#ifdef __cplusplus
}
#endif