Mirrors/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2026-10-02 11:10:54 +03:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'feature/adds_efuses_to_table' into 'master'

Browse Source 
efuse: Adds ERR_RST_ENABLE efuse for C3 and S3

See merge request espressif/esp-idf!17294
This commit is contained in:
Konstantin Kondrashov
2022-03-07 13:05:55 +08:00
parent 6f52bd178e 6d11c57b2a
commit e17b0df8ec
11 changed files with 93 additions and 59 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/soc/esp32c3/include/soc/efuse_reg.h
+30 -12
View File
@@ -256,11 +256,17 @@ extern "C" {
#define EFUSE_KEY_PURPOSE_2_S 0
#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x010)
/* EFUSE_RPT4_RESERVED1 : RO ;bitpos:[31:30] ;default: 2'h0 ; */
/* EFUSE_ERR_RST_ENABLE : RO ;bitpos:[31] ;default: 1'h0 ; */
/*description: Use BLOCK0 to check error record registers, 0 - without check.*/
#define EFUSE_ERR_RST_ENABLE (BIT(31))
#define EFUSE_ERR_RST_ENABLE_M (BIT(31))
#define EFUSE_ERR_RST_ENABLE_V 0x1
#define EFUSE_ERR_RST_ENABLE_S 31
/* EFUSE_RPT4_RESERVED1 : RO ;bitpos:[30] ;default: 1'h0 ; */
/*description: Reserved (used for four backups method).*/
#define EFUSE_RPT4_RESERVED1 0x00000003
#define EFUSE_RPT4_RESERVED1_M ((EFUSE_RPT4_RESERVED1_V)<<(EFUSE_RPT4_RESERVED1_S))
#define EFUSE_RPT4_RESERVED1_V 0x3
#define EFUSE_RPT4_RESERVED1 (BIT(30))
#define EFUSE_RPT4_RESERVED1_M (BIT(30))
#define EFUSE_RPT4_RESERVED1_V 0x1
#define EFUSE_RPT4_RESERVED1_S 30
/* EFUSE_SECURE_VERSION : R/W ;bitpos:[29:14] ;default: 16'h0 ; */
/*description: Secure version (used by ESP-IDF anti-rollback feature).*/
@@ -609,11 +615,17 @@ extern "C" {
#define EFUSE_KEY_PURPOSE_2_S 0
#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x03C)
/* EFUSE_RPT4_RESERVED1 : RO ;bitpos:[31:30] ;default: 2'h0 ; */
/* EFUSE_ERR_RST_ENABLE : RO ;bitpos:[31] ;default: 1'h0 ; */
/*description: Use BLOCK0 to check error record registers, 0 - without check.*/
#define EFUSE_ERR_RST_ENABLE (BIT(31))
#define EFUSE_ERR_RST_ENABLE_M (BIT(31))
#define EFUSE_ERR_RST_ENABLE_V 0x1
#define EFUSE_ERR_RST_ENABLE_S 31
/* EFUSE_RPT4_RESERVED1 : RO ;bitpos:[30] ;default: 1'h0 ; */
/*description: Reserved.*/
#define EFUSE_RPT4_RESERVED1 0x00000003
#define EFUSE_RPT4_RESERVED1_M ((EFUSE_RPT4_RESERVED1_V)<<(EFUSE_RPT4_RESERVED1_S))
#define EFUSE_RPT4_RESERVED1_V 0x3
#define EFUSE_RPT4_RESERVED1 (BIT(30))
#define EFUSE_RPT4_RESERVED1_M (BIT(30))
#define EFUSE_RPT4_RESERVED1_V 0x1
#define EFUSE_RPT4_RESERVED1_S 30
/* EFUSE_SECURE_VERSION : RO ;bitpos:[29:14] ;default: 16'h0 ; */
/*description: The value of SECURE_VERSION.*/
@@ -1561,11 +1573,17 @@ extern "C" {
#define EFUSE_KEY_PURPOSE_2_ERR_S 0
#define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188)
/* EFUSE_RPT4_RESERVED1_ERR : RO ;bitpos:[31:30] ;default: 2'h0 ; */
/* EFUSE_ERR_RST_ENABLE_ERR : RO ;bitpos:[31] ;default: 1'h0 ; */
/*description: Use BLOCK0 to check error record registers, 0 - without check.*/
#define EFUSE_ERR_RST_ENABLE_ERR (BIT(31))
#define EFUSE_ERR_RST_ENABLE_ERR_M (BIT(31))
#define EFUSE_ERR_RST_ENABLE_ERR_V 0x1
#define EFUSE_ERR_RST_ENABLE_ERR_S 31
/* EFUSE_RPT4_RESERVED1_ERR : RO ;bitpos:[30] ;default: 1'h0 ; */
/*description: Reserved.*/
#define EFUSE_RPT4_RESERVED1_ERR 0x00000003
#define EFUSE_RPT4_RESERVED1_ERR_M ((EFUSE_RPT4_RESERVED1_ERR_V)<<(EFUSE_RPT4_RESERVED1_ERR_S))
#define EFUSE_RPT4_RESERVED1_ERR_V 0x3
#define EFUSE_RPT4_RESERVED1_ERR (BIT(30))
#define EFUSE_RPT4_RESERVED1_ERR_M (BIT(30))
#define EFUSE_RPT4_RESERVED1_ERR_V 0x1
#define EFUSE_RPT4_RESERVED1_ERR_S 30
/* EFUSE_SECURE_VERSION_ERR : RO ;bitpos:[29:14] ;default: 16'h0 ; */
/*description: If any bit in SECURE_VERSION is 1 then it indicates a programming error.*/
components/soc/esp32c3/include/soc/efuse_struct.h
+6 -3
View File
@@ -75,7 +75,8 @@ typedef volatile struct efuse_dev_s {
uint32_t rpt4_reserved7: 5; /*Reserved (used for four backups method).*/
uint32_t force_send_resume: 1; /*Set this bit to force ROM code to send a resume command during SPI boot.*/
uint32_t secure_version: 16; /*Secure version (used by ESP-IDF anti-rollback feature).*/
uint32_t rpt4_reserved1: 2; /*Reserved (used for four backups method).*/
uint32_t rpt4_reserved1: 1; /*Reserved (used for four backups method).*/
uint32_t err_rst_enable: 1; /*Use BLOCK0 to check error record registers, 0 - without check.*/
};
uint32_t val;
} pgm_data4;
@@ -156,7 +157,8 @@ typedef volatile struct efuse_dev_s {
uint32_t rpt4_reserved7: 5; /*Reserved.*/
uint32_t force_send_resume: 1; /*The value of FORCE_SEND_RESUME.*/
uint32_t secure_version: 16; /*The value of SECURE_VERSION.*/
uint32_t rpt4_reserved1: 2; /*Reserved.*/
uint32_t rpt4_reserved1: 1; /*Reserved.*/
uint32_t err_rst_enable: 1; /*Use BLOCK0 to check error record registers, 0 - without check.*/
};
uint32_t val;
} rd_repeat_data3;
@@ -323,7 +325,8 @@ typedef volatile struct efuse_dev_s {
uint32_t rpt4_reserved7_err: 5; /*Reserved*/
uint32_t force_send_resume_err: 1; /*If FORCE_SEND_RESUME is 1 then it indicates a programming error.*/
uint32_t secure_version_err: 16; /*If any bit in SECURE_VERSION is 1 then it indicates a programming error.*/
uint32_t rpt4_reserved1_err: 2; /*Reserved.*/
uint32_t rpt4_reserved1_err: 1; /*Reserved.*/
uint32_t err_rst_enable_err: 1; /*Use BLOCK0 to check error record registers, 0 - without check.*/
};
uint32_t val;
} rd_repeat_err3;
components/soc/esp32s3/include/soc/efuse_reg.h
+22 -22
View File
@@ -429,18 +429,18 @@ apping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0..*/
#define EFUSE_KEY_PURPOSE_2_S 0
#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3C)
/* EFUSE_RPT4_RESERVED1 : RO ;bitpos:[31] ;default: 1'h0 ; */
/*description: Reserved (used for four backups method)..*/
#define EFUSE_RPT4_RESERVED1 (BIT(31))
#define EFUSE_RPT4_RESERVED1_M (BIT(31))
/* EFUSE_ERR_RST_ENABLE : RO ;bitpos:[31] ;default: 1'h0 ; */
/*description: Use BLOCK0 to check error record registers, 0 - without check.*/
#define EFUSE_ERR_RST_ENABLE (BIT(31))
#define EFUSE_ERR_RST_ENABLE_M (BIT(31))
#define EFUSE_ERR_RST_ENABLE_V 0x1
#define EFUSE_ERR_RST_ENABLE_S 31
/* EFUSE_RPT4_RESERVED1 : RO ;bitpos:[30] ;default: 1'h0 ; */
/*description: Reserved (used for four backups method).*/
#define EFUSE_RPT4_RESERVED1 (BIT(30))
#define EFUSE_RPT4_RESERVED1_M (BIT(30))
#define EFUSE_RPT4_RESERVED1_V 0x1
#define EFUSE_RPT4_RESERVED1_S 31
/* EFUSE_POWERGLITCH_EN : RO ;bitpos:[30] ;default: 1'b0 ; */
/*description: Set this bit to enable power glitch function..*/
#define EFUSE_POWERGLITCH_EN (BIT(30))
#define EFUSE_POWERGLITCH_EN_M (BIT(30))
#define EFUSE_POWERGLITCH_EN_V 0x1
#define EFUSE_POWERGLITCH_EN_S 30
#define EFUSE_RPT4_RESERVED1_S 30
/* EFUSE_SECURE_VERSION : RO ;bitpos:[29:14] ;default: 16'h0 ; */
/*description: Secure version (used by ESP-IDF anti-rollback feature)..*/
#define EFUSE_SECURE_VERSION 0x0000FFFF
@@ -1473,18 +1473,18 @@ apping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0..*/
#define EFUSE_KEY_PURPOSE_2_ERR_S 0
#define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188)
/* EFUSE_RPT4_RESERVED1_ERR : RO ;bitpos:[31] ;default: 1'h0 ; */
/*description: Reserved..*/
#define EFUSE_RPT4_RESERVED1_ERR (BIT(31))
#define EFUSE_RPT4_RESERVED1_ERR_M (BIT(31))
/* EFUSE_ERR_RST_ENABLE_ERR : RO ;bitpos:[31] ;default: 1'h0 ; */
/*description: Use BLOCK0 to check error record registers, 0 - without check.*/
#define EFUSE_ERR_RST_ENABLE_ERR (BIT(31))
#define EFUSE_ERR_RST_ENABLE_ERR_M (BIT(31))
#define EFUSE_ERR_RST_ENABLE_ERR_V 0x1
#define EFUSE_ERR_RST_ENABLE_ERR_S 31
/* EFUSE_RPT4_RESERVED1_ERR : RO ;bitpos:[30] ;default: 1'h0 ; */
/*description: Reserved.*/
#define EFUSE_RPT4_RESERVED1_ERR (BIT(30))
#define EFUSE_RPT4_RESERVED1_ERR_M (BIT(30))
#define EFUSE_RPT4_RESERVED1_ERR_V 0x1
#define EFUSE_RPT4_RESERVED1_ERR_S 31
/* EFUSE_POWERGLITCH_EN_ERR : RO ;bitpos:[30] ;default: 1'b0 ; */
/*description: .*/
#define EFUSE_POWERGLITCH_EN_ERR (BIT(30))
#define EFUSE_POWERGLITCH_EN_ERR_M (BIT(30))
#define EFUSE_POWERGLITCH_EN_ERR_V 0x1
#define EFUSE_POWERGLITCH_EN_ERR_S 30
#define EFUSE_RPT4_RESERVED1_ERR_S 30
/* EFUSE_SECURE_VERSION_ERR : RO ;bitpos:[29:14] ;default: 16'h0 ; */
/*description: If any bits in this filed are 1, then it indicates a programming error..*/
#define EFUSE_SECURE_VERSION_ERR 0x0000FFFF
components/soc/esp32s3/include/soc/efuse_struct.h
+7 -15
View File
@@ -1,16 +1,8 @@
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_EFUSE_STRUCT_H_
#define _SOC_EFUSE_STRUCT_H_
@@ -113,8 +105,8 @@ typedef volatile struct efuse_dev_s {
uint32_t reg_flash_ecc_en : 1; /*Set 1 to enable ECC for flash boot.*/
uint32_t reg_force_send_resume : 1; /*Set this bit to force ROM code to send a resume command during SPI boot.*/
uint32_t reg_secure_version : 16; /*Secure version (used by ESP-IDF anti-rollback feature).*/
uint32_t reg_powerglitch_en : 1; /*Set this bit to enable power glitch function.*/
uint32_t reg_rpt4_reserved1 : 1; /*Reserved (used for four backups method).*/
uint32_t reg_err_rst_enable : 1; /*Use BLOCK0 to check error record registers, 0 - without check.*/
};
uint32_t val;
} rd_repeat_data3;
@@ -295,8 +287,8 @@ typedef volatile struct efuse_dev_s {
uint32_t reg_flash_ecc_en_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_force_send_resume_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_secure_version_err : 16; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_powerglitch_en_err : 1;
uint32_t reg_rpt4_reserved1_err : 1; /*Reserved.*/
uint32_t reg_err_rst_enable_err : 1; /*Use BLOCK0 to check error record registers, 0 - without check.*/
};
uint32_t val;
} rd_repeat_err3;