diff --git a/components/esp_psram/esp32/esp_psram_extram_cache.c b/components/esp_psram/esp32/esp_psram_extram_cache.c
index 1ee185e1ed2..7cfc1047376 100644
--- a/components/esp_psram/esp32/esp_psram_extram_cache.c
+++ b/components/esp_psram/esp32/esp_psram_extram_cache.c
@@ -24,7 +24,6 @@
 void IRAM_ATTR esp_psram_extram_writeback_cache(void)
 {
     int x;
-    volatile int i = 0;
     volatile uint8_t *psram = (volatile uint8_t*)SOC_EXTRAM_DATA_LOW;
     int cache_was_disabled = 0;
 
@@ -51,7 +50,7 @@ void IRAM_ATTR esp_psram_extram_writeback_cache(void)
     the cache by just reading 64K worth of cache lines.
     */
     for (x = 0; x < 1024 * 64; x += 32) {
-        i += psram[x];
+        (void)psram[x];
     }
 #else
     /*
@@ -61,8 +60,8 @@ void IRAM_ATTR esp_psram_extram_writeback_cache(void)
     we ever support external RAM chips of 2M or smaller, this may need adjusting.
     */
     for (x = 0; x < 1024 * 64; x += 32) {
-        i += psram[x];
-        i += psram[x + (1024 * 1024 * 2)];
+        (void)psram[x];
+        (void)psram[x + (1024 * 1024 * 2)];
     }
 #endif