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Merge branch 'feature/glitch_filter_h2' into 'master'

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gpio: support glitch filter on esp32h2

Closes IDF-6286

See merge request espressif/esp-idf!22273
This commit is contained in:
morris
2023-02-14 13:07:44 +08:00
parent 18295bb2f5 a3f887a1fe
commit e0c98da169
14 changed files with 200 additions and 82 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
-8
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@@ -359,14 +359,6 @@ config SOC_GPIO_FLEX_GLITCH_FILTER_NUM
int
default 8
config SOC_GPIO_FILTER_CLK_SUPPORT_XTAL
bool
default y
config SOC_GPIO_FILTER_CLK_SUPPORT_PLL_F80M
bool
default y
config SOC_GPIO_SUPPORT_ETM
bool
default y
components/soc/esp32c6/include/soc/soc_caps.h
-2
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@@ -161,8 +161,6 @@
#define SOC_GPIO_PIN_COUNT 31
#define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1
#define SOC_GPIO_FLEX_GLITCH_FILTER_NUM 8
#define SOC_GPIO_FILTER_CLK_SUPPORT_XTAL 1
#define SOC_GPIO_FILTER_CLK_SUPPORT_PLL_F80M 1
// GPIO peripheral has the ETM extension
#define SOC_GPIO_SUPPORT_ETM 1
components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
+12
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@@ -3,6 +3,10 @@
# using gen_soc_caps_kconfig.py, do not edit manually
#####################################################
config SOC_DEDICATED_GPIO_SUPPORTED
bool
default y
config SOC_UART_SUPPORTED
bool
default y
@@ -291,6 +295,14 @@ config SOC_GPIO_PIN_COUNT
int
default 28
config SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER
bool
default y
config SOC_GPIO_FLEX_GLITCH_FILTER_NUM
int
default 8
config SOC_GPIO_SUPPORT_ETM
bool
default y
components/soc/esp32h2/include/soc/clk_tree_defs.h
+4
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@@ -371,7 +371,11 @@ typedef enum {
typedef enum {
GLITCH_FILTER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL clock as the source clock */
GLITCH_FILTER_CLK_SRC_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M clock as the source clock */
#if CONFIG_IDF_ENV_FPGA
GLITCH_FILTER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */
#else
GLITCH_FILTER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M clock as the default clock choice */
#endif
} soc_periph_glitch_filter_clk_src_t;
//////////////////////////////////////////////////TWAI/////////////////////////////////////////////////////////////////
components/soc/esp32h2/include/soc/gpio_ext_struct.h
+8 -8
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@@ -112,22 +112,22 @@ typedef union {
*/
typedef union {
struct {
/** filter_ch0_en : R/W; bitpos: [0]; default: 0;
/** filter_chn_en : R/W; bitpos: [0]; default: 0;
* Glitch Filter channel enable bit.
*/
uint32_t filter_ch0_en:1;
/** filter_ch0_input_io_num : R/W; bitpos: [6:1]; default: 0;
uint32_t filter_chn_en:1;
/** filter_chn_input_io_num : R/W; bitpos: [6:1]; default: 0;
* Glitch Filter input io number.
*/
uint32_t filter_ch0_input_io_num:6;
/** filter_ch0_window_thres : R/W; bitpos: [12:7]; default: 0;
uint32_t filter_chn_input_io_num:6;
/** filter_chn_window_thres : R/W; bitpos: [12:7]; default: 0;
* Glitch Filter window threshold.
*/
uint32_t filter_ch0_window_thres:6;
/** filter_ch0_window_width : R/W; bitpos: [18:13]; default: 0;
uint32_t filter_chn_window_thres:6;
/** filter_chn_window_width : R/W; bitpos: [18:13]; default: 0;
* Glitch Filter window width.
*/
uint32_t filter_ch0_window_width:6;
uint32_t filter_chn_window_width:6;
uint32_t reserved_19:13;
};
uint32_t val;
components/soc/esp32h2/include/soc/soc_caps.h
+5 -4
View File
@@ -26,7 +26,7 @@
/*-------------------------- COMMON CAPS ---------------------------------------*/
// #define SOC_ADC_SUPPORTED 1 // TODO: IDF-6214
// #define SOC_DEDICATED_GPIO_SUPPORTED 1 // TODO: IDF-6241
#define SOC_DEDICATED_GPIO_SUPPORTED 1
#define SOC_UART_SUPPORTED 1
#define SOC_GDMA_SUPPORTED 1
#define SOC_ASYNC_MEMCPY_SUPPORTED 1
@@ -153,8 +153,10 @@
/*-------------------------- GPIO CAPS ---------------------------------------*/
// ESP32-H2 has 1 GPIO peripheral
#define SOC_GPIO_PORT (1U)
#define SOC_GPIO_PIN_COUNT (28)
#define SOC_GPIO_PORT 1U
#define SOC_GPIO_PIN_COUNT 28
#define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1
#define SOC_GPIO_FLEX_GLITCH_FILTER_NUM 8
// GPIO peripheral has the ETM extension
#define SOC_GPIO_SUPPORT_ETM 1
@@ -173,7 +175,6 @@
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_0~6. GPIO_NUM_15~27)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x000000000FFF807FULL
// TODO: IDF-6241
/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */