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https://github.com/espressif/esp-idf.git
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feat(ulp/lp_spi): bring up LP SPI on ESP32-S31
Add LP SPI HAL LL layer for ESP32-S31 and ESP32-P4, enable the peripheral in soc_caps, and port the HP-side and LP-core-side SPI drivers to use the new LL abstraction.
This commit is contained in:
Marius Vikhammer
@@ -0,0 +1,375 @@
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/*
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* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*******************************************************************************
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* NOTICE
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* The hal is not public api, don't use it in application code.
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******************************************************************************/
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#pragma once
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#include <stdint.h>
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#include <stdbool.h>
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#include "soc/lp_spi_struct.h"
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#include "soc/lp_peri_clkrst_struct.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef lp_dev_t lp_spi_ll_dev_t;
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#define LP_SPI_LL_GET_HW() (&LP_SPI)
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#define LP_SPI_LL_MAX_BUFFER_SIZE 64
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/**
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* @brief Enable the LP SPI peripheral clock gate
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*/
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static inline void lp_spi_ll_enable_clock(lp_spi_ll_dev_t *hw)
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{
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LP_PERI_CLKRST.spi_ctrl.lp_spi_clk_en = 1;
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hw->spi_clk_gate.reg_clk_en = 1;
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hw->spi_clk_gate.reg_mst_clk_active = 1;
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}
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/**
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* @brief Write a 32-bit word to data buffer register at index n
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*/
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static inline void lp_spi_ll_write_buffer_word(lp_spi_ll_dev_t *hw, int n, uint32_t val)
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{
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hw->data_buf[n].val = val;
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}
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/**
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* @brief Read a 32-bit word from data buffer register at index n
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*/
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static inline uint32_t lp_spi_ll_read_buffer_word(lp_spi_ll_dev_t *hw, int n)
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{
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return hw->data_buf[n].val;
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}
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/**
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* @brief Reset RX and TX AFIFOs
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*/
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static inline void lp_spi_ll_reset_fifos(lp_spi_ll_dev_t *hw)
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{
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hw->spi_dma_conf.reg_rx_afifo_rst = 1;
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hw->spi_dma_conf.reg_rx_afifo_rst = 0;
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hw->spi_dma_conf.reg_buf_afifo_rst = 1;
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hw->spi_dma_conf.reg_buf_afifo_rst = 0;
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}
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/**
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* @brief Clear the transaction-done interrupt
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*/
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static inline void lp_spi_ll_clear_int_trans_done(lp_spi_ll_dev_t *hw)
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{
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hw->spi_dma_int_clr.reg_trans_done_int_clr = 1;
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}
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/**
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* @brief Return true if a transaction is currently in progress
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*/
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static inline bool lp_spi_ll_is_busy(lp_spi_ll_dev_t *hw)
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{
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return hw->spi_cmd.reg_usr != 0;
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}
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/**
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* @brief Return true if the transaction-done interrupt raw bit is set
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*/
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static inline bool lp_spi_ll_get_int_trans_done(lp_spi_ll_dev_t *hw)
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{
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return hw->spi_dma_int_raw.reg_trans_done_int_raw != 0;
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}
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/**
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* @brief Enable or disable the dummy phase
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*/
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static inline void lp_spi_ll_set_dummy_en(lp_spi_ll_dev_t *hw, bool enable)
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{
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hw->spi_user.reg_usr_dummy = enable ? 1 : 0;
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}
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/**
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* @brief Set the number of dummy cycles (value = cycles - 1)
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*/
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static inline void lp_spi_ll_set_dummy_cyclelen(lp_spi_ll_dev_t *hw, uint32_t cyclelen)
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{
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hw->spi_user1.reg_usr_dummy_cyclelen = cyclelen - 1;
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}
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/**
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* @brief Enable or disable the command phase
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*/
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static inline void lp_spi_ll_set_command_en(lp_spi_ll_dev_t *hw, bool enable)
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{
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hw->spi_user.reg_usr_command = enable ? 1 : 0;
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}
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/**
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* @brief Set the command bit length (value = bits - 1)
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*/
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static inline void lp_spi_ll_set_command_bitlen(lp_spi_ll_dev_t *hw, uint32_t bitlen)
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{
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hw->spi_user2.reg_usr_command_bitlen = bitlen - 1;
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}
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/**
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* @brief Set the command value
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*/
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static inline void lp_spi_ll_set_command_value(lp_spi_ll_dev_t *hw, uint32_t value)
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{
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hw->spi_user2.reg_usr_command_value = value;
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}
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/**
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* @brief Enable or disable the address phase
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*/
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static inline void lp_spi_ll_set_address_en(lp_spi_ll_dev_t *hw, bool enable)
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{
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hw->spi_user.reg_usr_addr = enable ? 1 : 0;
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}
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/**
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* @brief Set the address bit length (value = bits - 1)
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*/
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static inline void lp_spi_ll_set_address_bitlen(lp_spi_ll_dev_t *hw, uint32_t bitlen)
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{
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hw->spi_user1.reg_usr_addr_bitlen = bitlen;
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}
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/**
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* @brief Set the address value
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*/
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static inline void lp_spi_ll_set_address_value(lp_spi_ll_dev_t *hw, uint32_t value)
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{
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hw->spi_addr.reg_usr_addr_value = value;
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}
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/**
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* @brief Enable or disable the MOSI (write-data) phase
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*/
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static inline void lp_spi_ll_set_mosi_en(lp_spi_ll_dev_t *hw, bool enable)
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{
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hw->spi_user.reg_usr_mosi = enable ? 1 : 0;
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}
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/**
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* @brief Enable or disable the MISO (read-data) phase
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*/
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static inline void lp_spi_ll_set_miso_en(lp_spi_ll_dev_t *hw, bool enable)
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{
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hw->spi_user.reg_usr_miso = enable ? 1 : 0;
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}
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/**
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* @brief Set the data bit length for master/slave transfers (value = bits - 1)
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*/
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static inline void lp_spi_ll_set_data_bitlen(lp_spi_ll_dev_t *hw, uint32_t bitlen)
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{
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hw->spi_ms_dlen.reg_ms_data_bitlen = bitlen;
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}
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/**
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* @brief Trigger a configuration update (master mode, synchronises APB->SPI domain)
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*/
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static inline void lp_spi_ll_apply_config(lp_spi_ll_dev_t *hw)
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{
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hw->spi_cmd.reg_update = 1;
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while (hw->spi_cmd.reg_update) {
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;
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}
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}
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/**
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* @brief Start a user-defined SPI transaction
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*/
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static inline void lp_spi_ll_start_user_transaction(lp_spi_ll_dev_t *hw)
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{
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hw->spi_cmd.reg_usr = 1;
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}
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/**
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* @brief Get the number of bits received during the last slave transfer
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*/
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static inline uint32_t lp_spi_ll_get_slave_rcv_bitlen(lp_spi_ll_dev_t *hw)
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{
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return hw->spi_slave1.reg_slv_data_bitlen;
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}
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/**
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* @brief Return true if wr_bit_order (MOSI LSB-first) is set
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*/
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static inline bool lp_spi_ll_get_wr_bit_order(lp_spi_ll_dev_t *hw)
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{
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return hw->spi_ctrl.reg_wr_bit_order != 0;
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}
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/**
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* @brief Set MOSI/MISO bit order (0 = MSB first, 1 = LSB first)
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*/
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static inline void lp_spi_ll_set_bit_order(lp_spi_ll_dev_t *hw, bool rd_lsb_first, bool wr_lsb_first)
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{
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hw->spi_ctrl.reg_rd_bit_order = rd_lsb_first ? 1 : 0;
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hw->spi_ctrl.reg_wr_bit_order = wr_lsb_first ? 1 : 0;
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}
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/**
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* @brief Set SPI clock polarity (CPOL) idle edge
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*/
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static inline void lp_spi_ll_set_ck_idle_edge(lp_spi_ll_dev_t *hw, bool idle_high)
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{
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hw->spi_misc.reg_ck_idle_edge = idle_high ? 1 : 0;
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}
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/**
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* @brief Set clock-out edge (used with CPOL/CPHA in master mode)
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*/
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static inline void lp_spi_ll_set_ck_out_edge(lp_spi_ll_dev_t *hw, bool edge)
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{
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hw->spi_user.reg_ck_out_edge = edge ? 1 : 0;
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}
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/**
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* @brief Set slave mode rising/falling clock edge for Rx and Tx sampling
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*/
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static inline void lp_spi_ll_set_slave_clk_edges(lp_spi_ll_dev_t *hw, bool rsck_i_edge, bool tsck_i_edge)
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{
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hw->spi_user.reg_rsck_i_edge = rsck_i_edge ? 1 : 0;
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hw->spi_user.reg_tsck_i_edge = tsck_i_edge ? 1 : 0;
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}
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/**
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* @brief Set slave clock mode 1/3 support bit
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*/
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static inline void lp_spi_ll_set_slave_clk_mode_13(lp_spi_ll_dev_t *hw, bool enable)
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{
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hw->spi_slave.reg_clk_mode_13 = enable ? 1 : 0;
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}
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/**
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* @brief Set master CS polarity (active high / active low)
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*/
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static inline void lp_spi_ll_set_master_cs_pol(lp_spi_ll_dev_t *hw, bool active_high)
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{
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hw->spi_misc.reg_master_cs_pol = active_high ? 1 : 0;
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}
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/**
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* @brief Set slave CS polarity (0 = active low, 1 = inverted)
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*/
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static inline void lp_spi_ll_set_slave_cs_pol(lp_spi_ll_dev_t *hw, bool inverted)
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{
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hw->spi_misc.reg_slave_cs_pol = inverted ? 1 : 0;
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}
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/**
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* @brief Enable or disable full-duplex mode (doutdin)
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*/
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static inline void lp_spi_ll_set_full_duplex(lp_spi_ll_dev_t *hw, bool enable)
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{
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hw->spi_user.reg_doutdin = enable ? 1 : 0;
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}
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/**
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* @brief Enable or disable 3-wire half-duplex (SIO) mode
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*/
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static inline void lp_spi_ll_set_sio_mode(lp_spi_ll_dev_t *hw, bool enable)
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{
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hw->spi_user.reg_sio = enable ? 1 : 0;
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}
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/**
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* @brief Configure CS setup (pre-transaction) timing
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*/
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static inline void lp_spi_ll_set_cs_setup(lp_spi_ll_dev_t *hw, bool enable, uint32_t setup_time)
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{
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hw->spi_user.reg_cs_setup = enable ? 1 : 0;
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hw->spi_user1.reg_cs_setup_time = setup_time;
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}
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/**
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* @brief Configure CS hold (post-transaction) timing
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*/
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static inline void lp_spi_ll_set_cs_hold(lp_spi_ll_dev_t *hw, bool enable, uint32_t hold_time)
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{
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hw->spi_user.reg_cs_hold = enable ? 1 : 0;
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hw->spi_user1.reg_cs_hold_time = hold_time;
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}
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/**
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* @brief Enable CS0 (disable the CS0_DIS bit)
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*/
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static inline void lp_spi_ll_enable_cs0(lp_spi_ll_dev_t *hw)
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{
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hw->spi_misc.reg_cs0_dis = 0;
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}
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/**
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* @brief Disable MOSI/MISO high-part buffer access
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*/
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static inline void lp_spi_ll_disable_highpart(lp_spi_ll_dev_t *hw)
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{
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hw->spi_user.reg_usr_mosi_highpart = 0;
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hw->spi_user.reg_usr_miso_highpart = 0;
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}
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/**
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* @brief Set slave mode enable bit
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*/
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static inline void lp_spi_ll_set_slave_mode(lp_spi_ll_dev_t *hw, bool slave)
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{
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hw->spi_slave.reg_slave_mode = slave ? 1 : 0;
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}
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/**
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* @brief Set slave clock mode (clk_mode field)
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*/
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static inline void lp_spi_ll_set_slave_clk_mode(lp_spi_ll_dev_t *hw, uint32_t clk_mode)
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{
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hw->spi_slave.reg_clk_mode = clk_mode;
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}
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/**
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* @brief Issue a software reset of the SPI peripheral
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*/
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static inline void lp_spi_ll_soft_reset(lp_spi_ll_dev_t *hw)
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{
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hw->spi_slave.reg_soft_reset = 1;
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hw->spi_slave.reg_soft_reset = 0;
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}
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/**
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* @brief Write the raw clock register value (used with spi_ll_master_cal_clock output)
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*/
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static inline void lp_spi_ll_set_clock_val(lp_spi_ll_dev_t *hw, uint32_t clock_val)
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{
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hw->spi_clock.val = clock_val;
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}
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/**
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* @brief Zero out the clock, user, and ctrl registers (slave init)
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*/
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static inline void lp_spi_ll_reset_slave_regs(lp_spi_ll_dev_t *hw)
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{
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hw->spi_clock.val = 0;
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hw->spi_user.val = 0;
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hw->spi_ctrl.val = 0;
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}
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/**
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* @brief Reset CS timing registers in master mode
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*/
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static inline void lp_spi_ll_reset_cs_timing(lp_spi_ll_dev_t *hw)
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{
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hw->spi_user1.reg_cs_setup_time = 0;
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hw->spi_user1.reg_cs_hold_time = 0;
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}
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#ifdef __cplusplus
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}
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#endif
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