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https://github.com/espressif/esp-idf.git
synced 2026-10-02 03:00:34 +03:00
fix(i2s): fix test issue on esp32s31 & esp32h4
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@@ -3,10 +3,6 @@
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components/esp_driver_i2s/test_apps/i2s:
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disable:
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- if: SOC_I2S_SUPPORTED != 1
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disable_test:
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- if: IDF_TARGET in ["esp32h4"]
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temporary: true
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reason: cannot pass # TODO: IDF-15609
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depends_components:
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- esp_driver_i2s
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- esp_driver_pcnt
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@@ -21,7 +21,6 @@ from pytest_embedded_idf.utils import soc_filtered_targets
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indirect=['target'],
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)
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@pytest.mark.temp_skip_ci(targets=['esp32h21'], reason='lack of runners')
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@pytest.mark.temp_skip_ci(targets=['esp32h4'], reason='cannot pass') # TODO: IDF-15609
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def test_i2s(dut: Dut) -> None:
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dut.run_all_single_board_cases()
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@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Unlicense OR CC0-1.0
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*/
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@@ -80,6 +80,9 @@ static void test_i2s_tdm_master(uint32_t sample_rate, i2s_data_bit_width_t bit_w
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.gpio_cfg = TEST_I2S_DEFAULT_GPIO(I2S_GPIO_UNUSED, true),
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};
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i2s_tdm_config.clk_cfg.mclk_multiple = I2S_MCLK_MULTIPLE_512;
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#if CONFIG_IDF_TARGET_ESP32S31
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i2s_tdm_config.clk_cfg.clk_src = I2S_CLK_SRC_APLL;
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#endif
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TEST_ESP_OK(i2s_channel_init_tdm_mode(i2s_tdm_tx_handle, &i2s_tdm_config));
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TEST_ESP_OK(i2s_channel_init_tdm_mode(i2s_tdm_rx_handle, &i2s_tdm_config));
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@@ -293,7 +296,7 @@ TEST_CASE_MULTIPLE_DEVICES("I2S_TDM_full_duplex_test_in_48k_8bits_4slots", "[I2S
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/* The I2S source clock can only reach 96Mhz on ESP32H2,
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and the max clock source APLL on P4 is 125M,
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which can't satisfy the following configurations in slave mode */
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#if !CONFIG_IDF_TARGET_ESP32H2 && !CONFIG_IDF_TARGET_ESP32P4
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#if !CONFIG_IDF_TARGET_ESP32H2 && !CONFIG_IDF_TARGET_ESP32H4 && !CONFIG_IDF_TARGET_ESP32P4
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static void test_i2s_tdm_master_48k_16bits_8slots(void)
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{
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test_i2s_tdm_master(48000, I2S_DATA_BIT_WIDTH_16BIT, I2S_TDM_SLOT0 | I2S_TDM_SLOT1 | I2S_TDM_SLOT2 | I2S_TDM_SLOT3 |
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@@ -339,7 +342,7 @@ static void test_i2s_external_clk_src(bool is_master, bool is_external)
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std_cfg.clk_cfg.clk_src = I2S_CLK_SRC_EXTERNAL;
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std_cfg.clk_cfg.ext_clk_freq_hz = 22579200;
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}
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#if CONFIG_IDF_TARGET_ESP32P4
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#if CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32S31
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else {
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// Use APLL instead.
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// Because the default clock source is not sufficient for 22.58M MCLK
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