mirror of
https://github.com/espressif/esp-idf.git
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feat(esp_hal_pmu): graduate pmu/rtc_cntl hal driver into a new component: esp_hal_pmu
This commit is contained in:
wuzhenghui
@@ -0,0 +1,22 @@
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idf_build_get_property(target IDF_TARGET)
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if(${target} STREQUAL "linux")
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return() # This component is not supported by the POSIX/Linux simulator
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endif()
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set(srcs)
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set(public_include "include" "${target}/include")
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# New chips with PMU peripheral
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if(CONFIG_SOC_PMU_SUPPORTED)
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list(APPEND srcs "${target}/pmu_hal.c")
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endif()
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# Legacy chips with RTC_CNTL peripheral
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if(EXISTS "${CMAKE_CURRENT_LIST_DIR}/${target}/rtc_cntl_hal.c")
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list(APPEND srcs "${target}/rtc_cntl_hal.c")
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endif()
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idf_component_register(SRCS ${srcs}
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INCLUDE_DIRS ${public_include}
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REQUIRES soc hal esp_rom
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LDFRAGMENTS linker.lf)
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@@ -0,0 +1,68 @@
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# ESP Hardware Abstraction Layer for PMU and RTC Control Peripherals
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> [!NOTE]
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> This component is currently in beta. Its API, behavior, and compatibility may change at any time and without notice; backward compatibility is not guaranteed. Use caution when integrating into production systems.
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## Overview
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The `esp_hal_pmu` component provides a **Hardware Abstraction Layer** for Power Management Unit (PMU) and legacy RTC Control (RTC_CNTL) peripherals across ESP-IDF supported targets. This HAL enables unified power management operations including sleep mode control, power domain management, wakeup configuration, and retention control across different ESP chip families.
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The component consolidates power management functionality from two different peripheral implementations:
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- **PMU**: Modern power management unit in newer ESP chips
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- **RTC_CNTL**: Legacy RTC control peripheral in older ESP chips
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## Architecture
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The HAL architecture consists of two primary layers:
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1. **HAL Layer (Upper)**: Defines the operational sequences and data structures required to interact with PMU/RTC_CNTL peripherals, including:
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- Power domain configuration and control
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- Sleep mode management
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- Wakeup source configuration
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- Retention control (CPU, tagmem)
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- Power-up/down wait cycle configuration
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- Backup enable/disable operations
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2. **Low-Level Layer (Bottom)**: Acts as a translation layer between the HAL and the register definitions in the `soc` component, handling:
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- Register access abstractions
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- Chip-specific register configurations
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- Hardware feature compatibility
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- Power domain and clock control
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## Features
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### Power Management
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- Power domain control (HP/LP system power domains)
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- Digital power supply and power-up wait cycle configuration
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- Control ready wait cycle configuration (isolate/reset)
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- Power mode transitions (active, sleep, modem)
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### Sleep and Wakeup
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- Sleep mode configuration
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- Wakeup source management
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- Sleep rejection handling
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- Wakeup cause detection
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### Retention Control
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- CPU retention enable/disable
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- Tagmem retention support (on supported chips)
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- DMA link buffer configuration for retention
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### Backup Operations
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- Sleep-to-active backup enable/disable
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- Sleep-to-modem backup enable/disable
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- Modem-to-active backup enable/disable
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## Usage
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This component is primarily used by ESP-IDF system services such as:
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- **esp_pm**: Power management framework
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- **esp_hw_support**: Hardware support layer for sleep modes and power management
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- **ulp**: Ultra-low-power coprocessor support
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For advanced developers implementing custom power management solutions, the HAL functions can be used directly. However, please note that the interfaces provided by this component are internal to ESP-IDF and are subject to change.
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## Dependencies
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- `soc`: Provides chip-specific register definitions and peripheral capabilities
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- `hal`: Core hardware abstraction utilities and macros
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- `esp_rom`: ROM function interfaces (where applicable)
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@@ -0,0 +1,115 @@
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/*
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* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include "soc/soc.h"
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#include "esp_attr.h"
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#include "hal/clk_tree_ll.h"
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#include "esp_rom_sys.h"
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#include "hal/assert.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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FORCE_INLINE_ATTR void rtc_cntl_ll_set_wakeup_timer(uint64_t t)
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{
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WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX);
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WRITE_PERI_REG(RTC_CNTL_SLP_TIMER1_REG, t >> 32);
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}
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FORCE_INLINE_ATTR void rtc_cntl_ll_ext1_clear_wakeup_status(void)
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{
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REG_SET_BIT(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_STATUS_CLR);
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}
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FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_ext1_get_wakeup_status(void)
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{
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return REG_GET_FIELD(RTC_CNTL_EXT_WAKEUP1_STATUS_REG, RTC_CNTL_EXT_WAKEUP1_STATUS);
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}
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FORCE_INLINE_ATTR void rtc_cntl_ll_ext1_set_wakeup_pins(uint32_t io_mask, uint32_t mode_mask)
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{
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// The target only supports a unified trigger mode among all EXT1 wakeup IOs
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HAL_ASSERT((io_mask & mode_mask) == io_mask || (io_mask & mode_mask) == 0);
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REG_SET_FIELD(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_SEL, io_mask);
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if ((io_mask & mode_mask) == io_mask) {
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SET_PERI_REG_BITS(RTC_CNTL_EXT_WAKEUP_CONF_REG, 0x1,
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1, RTC_CNTL_EXT_WAKEUP1_LV_S);
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} else {
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SET_PERI_REG_BITS(RTC_CNTL_EXT_WAKEUP_CONF_REG, 0x1,
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0, RTC_CNTL_EXT_WAKEUP1_LV_S);
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}
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}
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FORCE_INLINE_ATTR void rtc_cntl_ll_ext1_clear_wakeup_pins(void)
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{
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CLEAR_PERI_REG_MASK(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_SEL_M);
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}
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FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_ext1_get_wakeup_pins(void)
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{
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return REG_GET_FIELD(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_SEL);
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}
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FORCE_INLINE_ATTR void rtc_cntl_ll_ulp_wakeup_enable(void)
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{
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SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN);
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}
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FORCE_INLINE_ATTR void rtc_cntl_ll_ulp_int_clear(void)
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{
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REG_SET_BIT(RTC_CNTL_INT_CLR_REG, RTC_CNTL_SAR_INT_CLR);
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}
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FORCE_INLINE_ATTR void rtc_cntl_ll_timer2_set_touch_wait_cycle(uint32_t wait_cycle)
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{
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REG_SET_FIELD(RTC_CNTL_TIMER2_REG, RTC_CNTL_ULPCP_TOUCH_START_WAIT, wait_cycle);
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}
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FORCE_INLINE_ATTR void rtc_cntl_ll_reset_system(void)
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{
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REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST);
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}
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FORCE_INLINE_ATTR void rtc_cntl_ll_reset_cpu(int cpu_no)
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{
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uint32_t rtc_cntl_rst = (cpu_no == 0) ? RTC_CNTL_SW_PROCPU_RST : RTC_CNTL_SW_APPCPU_RST;
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REG_WRITE(RTC_CNTL_OPTIONS0_REG, rtc_cntl_rst);
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}
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FORCE_INLINE_ATTR void rtc_cntl_ll_sleep_enable(void)
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{
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SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_SLEEP_EN);
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}
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FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_get_rtc_time(void)
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{
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SET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_UPDATE);
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int attempts = 1000;
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while (GET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_VALID) == 0) {
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esp_rom_delay_us(1);
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if (attempts) {
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if (--attempts == 0 && clk_ll_xtal32k_digi_is_enabled()) {
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esp_rom_printf("32KHz xtal has been stopped\n");
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}
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}
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}
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SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG, RTC_CNTL_TIME_VALID_INT_CLR);
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uint64_t t = READ_PERI_REG(RTC_CNTL_TIME0_REG);
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t |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME1_REG)) << 32;
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return t;
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}
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FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_get_wakeup_cause(void)
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{
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return REG_GET_FIELD(RTC_CNTL_WAKEUP_STATE_REG, RTC_CNTL_WAKEUP_CAUSE);
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}
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#ifdef __cplusplus
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}
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#endif
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@@ -0,0 +1,83 @@
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/*
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* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include "soc/soc.h"
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#include "soc/rtc_cntl_reg.h"
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#include "soc/syscon_reg.h"
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#include "esp_attr.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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FORCE_INLINE_ATTR void rtc_cntl_ll_set_wakeup_timer(uint64_t t)
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{
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WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX);
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WRITE_PERI_REG(RTC_CNTL_SLP_TIMER1_REG, t >> 32);
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SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG, RTC_CNTL_MAIN_TIMER_INT_CLR_M);
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SET_PERI_REG_MASK(RTC_CNTL_SLP_TIMER1_REG, RTC_CNTL_MAIN_TIMER_ALARM_EN_M);
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}
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FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_gpio_get_wakeup_status(void)
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{
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return GET_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_WAKEUP_STATUS);
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}
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FORCE_INLINE_ATTR void rtc_cntl_ll_gpio_clear_wakeup_status(void)
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{
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REG_SET_BIT(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_WAKEUP_STATUS_CLR);
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REG_CLR_BIT(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_WAKEUP_STATUS_CLR);
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}
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FORCE_INLINE_ATTR void rtc_cntl_ll_enable_cpu_retention(uint32_t addr)
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{
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/* write memory address to register */
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REG_SET_FIELD(SYSCON_RETENTION_CTRL_REG, SYSCON_RETENTION_LINK_ADDR, (uint32_t)addr);
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/* Enable clock */
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REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN);
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/* Enable retention when cpu sleep enable */
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REG_SET_BIT(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_EN);
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}
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FORCE_INLINE_ATTR void rtc_cntl_ll_disable_cpu_retention(void)
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{
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REG_CLR_BIT(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_EN);
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}
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FORCE_INLINE_ATTR void rtc_cntl_ll_reset_system(void)
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{
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REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST);
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}
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FORCE_INLINE_ATTR void rtc_cntl_ll_reset_cpu(int cpu_no)
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{
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REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_PROCPU_RST);
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}
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FORCE_INLINE_ATTR void rtc_cntl_ll_sleep_enable(void)
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{
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SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_SLEEP_EN);
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}
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FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_get_rtc_time(void)
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{
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SET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_UPDATE);
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uint64_t t = READ_PERI_REG(RTC_CNTL_TIME0_REG);
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t |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME1_REG)) << 32;
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return t;
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}
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FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_get_wakeup_cause(void)
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{
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return REG_GET_FIELD(RTC_CNTL_SLP_WAKEUP_CAUSE_REG, RTC_CNTL_WAKEUP_CAUSE);
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}
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#ifdef __cplusplus
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}
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#endif
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@@ -0,0 +1,68 @@
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/*
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* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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// The HAL layer for RTC CNTL (common part)
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#include "soc/soc_caps.h"
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#include "soc/lldesc.h"
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#include "hal/rtc_hal.h"
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#include "hal/assert.h"
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#include "esp_attr.h"
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#define RTC_CNTL_HAL_LINK_BUF_SIZE_MIN (SOC_RTC_CNTL_CPU_PD_DMA_BLOCK_SIZE) /* The minimum size of dma link buffer */
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typedef struct rtc_cntl_link_buf_conf {
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uint32_t cfg[4]; /* 4 word for dma link buffer configuration */
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} rtc_cntl_link_buf_conf_t;
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void * rtc_cntl_hal_dma_link_init(void *elem, void *buff, int size, void *next)
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{
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HAL_ASSERT(elem != NULL);
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HAL_ASSERT(buff != NULL);
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HAL_ASSERT(size >= RTC_CNTL_HAL_LINK_BUF_SIZE_MIN);
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lldesc_t *plink = (lldesc_t *)elem;
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plink->eof = next ? 0 : 1;
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plink->owner = 1;
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plink->size = size >> 4; /* in unit of 16 bytes */
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plink->length = size >> 4;
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plink->buf = buff;
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plink->offset = 0;
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plink->sosf = 0;
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STAILQ_NEXT(plink, qe) = next;
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return (void *)plink;
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}
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#if SOC_PM_SUPPORT_CPU_PD
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void rtc_cntl_hal_enable_cpu_retention(void *addr)
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{
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if (addr) {
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lldesc_t *plink = (lldesc_t *)addr;
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/* dma link buffer configure */
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rtc_cntl_link_buf_conf_t *pbuf = (rtc_cntl_link_buf_conf_t *)plink->buf;
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pbuf->cfg[0] = 0;
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pbuf->cfg[1] = 0;
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pbuf->cfg[2] = 0;
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pbuf->cfg[3] = (uint32_t) -1;
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rtc_cntl_ll_enable_cpu_retention((uint32_t)addr);
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}
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}
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void IRAM_ATTR rtc_cntl_hal_disable_cpu_retention(void *addr)
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{
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rtc_cntl_sleep_retent_t *retent = (rtc_cntl_sleep_retent_t *)addr;
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if (addr) {
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if (retent->cpu_pd_mem) {
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rtc_cntl_ll_disable_cpu_retention();
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}
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}
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}
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#endif // SOC_PM_SUPPORT_CPU_PD
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@@ -0,0 +1,89 @@
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/*
|
||||
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
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*/
|
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#pragma once
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#include "soc/soc.h"
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#include "soc/rtc_cntl_reg.h"
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#include "soc/syscon_reg.h"
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#include "esp_attr.h"
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|
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#ifdef __cplusplus
|
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extern "C" {
|
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#endif
|
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|
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FORCE_INLINE_ATTR void rtc_cntl_ll_set_wakeup_timer(uint64_t t)
|
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{
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WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX);
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WRITE_PERI_REG(RTC_CNTL_SLP_TIMER1_REG, t >> 32);
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|
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SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG, RTC_CNTL_MAIN_TIMER_INT_CLR_M);
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SET_PERI_REG_MASK(RTC_CNTL_SLP_TIMER1_REG, RTC_CNTL_MAIN_TIMER_ALARM_EN_M);
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}
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FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_gpio_get_wakeup_status(void)
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{
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return GET_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_WAKEUP_STATUS);
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}
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FORCE_INLINE_ATTR void rtc_cntl_ll_gpio_clear_wakeup_status(void)
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{
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REG_SET_BIT(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_WAKEUP_STATUS_CLR);
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REG_CLR_BIT(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_WAKEUP_STATUS_CLR);
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}
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FORCE_INLINE_ATTR void rtc_cntl_ll_set_cpu_retention_link_addr(uint32_t addr)
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{
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REG_SET_FIELD(SYSCON_RETENTION_CTRL_REG, SYSCON_RETENTION_LINK_ADDR, (uint32_t)addr);
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}
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FORCE_INLINE_ATTR void rtc_cntl_ll_enable_cpu_retention_clock(void)
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{
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REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN);
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}
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FORCE_INLINE_ATTR void rtc_cntl_ll_enable_cpu_retention(void)
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{
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/* Enable retention when cpu sleep enable */
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REG_SET_BIT(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_EN);
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}
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|
||||
FORCE_INLINE_ATTR void rtc_cntl_ll_disable_cpu_retention(void)
|
||||
{
|
||||
REG_CLR_BIT(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_EN);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void rtc_cntl_ll_reset_system(void)
|
||||
{
|
||||
REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void rtc_cntl_ll_reset_cpu(int cpu_no)
|
||||
{
|
||||
REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_PROCPU_RST);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void rtc_cntl_ll_sleep_enable(void)
|
||||
{
|
||||
SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_SLEEP_EN);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_get_rtc_time(void)
|
||||
{
|
||||
SET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_UPDATE);
|
||||
uint64_t t = READ_PERI_REG(RTC_CNTL_TIME0_REG);
|
||||
t |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME1_REG)) << 32;
|
||||
return t;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_get_wakeup_cause(void)
|
||||
{
|
||||
return REG_GET_FIELD(RTC_CNTL_SLP_WAKEUP_CAUSE_REG, RTC_CNTL_WAKEUP_CAUSE);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,76 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The HAL layer for RTC CNTL (common part)
|
||||
|
||||
#include "soc/soc_caps.h"
|
||||
#include "soc/lldesc.h"
|
||||
#include "hal/dma_types.h"
|
||||
#include "hal/rtc_hal.h"
|
||||
#include "hal/assert.h"
|
||||
#include "esp_attr.h"
|
||||
|
||||
#define RTC_CNTL_HAL_LINK_BUF_SIZE_MIN (SOC_RTC_CNTL_CPU_PD_DMA_BLOCK_SIZE) /* The minimum size of dma link buffer */
|
||||
|
||||
typedef struct rtc_cntl_link_buf_conf {
|
||||
uint32_t cfg[4]; /* 4 word for dma link buffer configuration */
|
||||
} rtc_cntl_link_buf_conf_t;
|
||||
|
||||
void * rtc_cntl_hal_dma_link_init(void *elem, void *buff, int size, void *next)
|
||||
{
|
||||
HAL_ASSERT(elem != NULL);
|
||||
HAL_ASSERT(buff != NULL);
|
||||
HAL_ASSERT(size >= RTC_CNTL_HAL_LINK_BUF_SIZE_MIN);
|
||||
|
||||
lldesc_t *plink = (lldesc_t *)elem;
|
||||
|
||||
plink->eof = next ? 0 : 1;
|
||||
plink->owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA;
|
||||
plink->size = size >> 4; /* in unit of 16 bytes */
|
||||
plink->length = size >> 4;
|
||||
plink->buf = buff;
|
||||
plink->offset = 0;
|
||||
plink->sosf = 0;
|
||||
STAILQ_NEXT(plink, qe) = next;
|
||||
return (void *)plink;
|
||||
}
|
||||
|
||||
#if SOC_PM_SUPPORT_CPU_PD
|
||||
|
||||
void rtc_cntl_hal_enable_cpu_retention(void *addr)
|
||||
{
|
||||
rtc_cntl_sleep_retent_t *retent = (rtc_cntl_sleep_retent_t *)addr;
|
||||
|
||||
if (addr) {
|
||||
if (retent->cpu_pd_mem) {
|
||||
lldesc_t *plink = (lldesc_t *)retent->cpu_pd_mem;
|
||||
|
||||
/* dma link buffer configure */
|
||||
rtc_cntl_link_buf_conf_t *pbuf = (rtc_cntl_link_buf_conf_t *)plink->buf;
|
||||
pbuf->cfg[0] = 0;
|
||||
pbuf->cfg[1] = 0;
|
||||
pbuf->cfg[2] = 0;
|
||||
pbuf->cfg[3] = (uint32_t) -1;
|
||||
|
||||
rtc_cntl_ll_set_cpu_retention_link_addr((uint32_t)plink);
|
||||
rtc_cntl_ll_enable_cpu_retention_clock();
|
||||
rtc_cntl_ll_enable_cpu_retention();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void IRAM_ATTR rtc_cntl_hal_disable_cpu_retention(void *addr)
|
||||
{
|
||||
rtc_cntl_sleep_retent_t *retent = (rtc_cntl_sleep_retent_t *)addr;
|
||||
|
||||
if (addr) {
|
||||
if (retent->cpu_pd_mem) {
|
||||
rtc_cntl_ll_disable_cpu_retention();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#endif // SOC_PM_SUPPORT_CPU_PD
|
||||
@@ -0,0 +1,49 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The HAL layer for PMU
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "soc/soc_caps.h"
|
||||
#include "hal/pmu_ll.h"
|
||||
#include "hal/pmu_types.h"
|
||||
|
||||
typedef struct {
|
||||
pmu_dev_t *dev;
|
||||
} pmu_hal_context_t;
|
||||
|
||||
void pmu_hal_hp_set_digital_power_up_wait_cycle(pmu_hal_context_t *hal, uint32_t power_supply_wait_cycle, uint32_t power_up_wait_cycle);
|
||||
|
||||
uint32_t pmu_hal_hp_get_digital_power_up_wait_cycle(pmu_hal_context_t *hal);
|
||||
|
||||
void pmu_hal_lp_set_digital_power_up_wait_cycle(pmu_hal_context_t *hal, uint32_t power_supply_wait_cycle, uint32_t power_up_wait_cycle);
|
||||
|
||||
uint32_t pmu_hal_lp_get_digital_power_up_wait_cycle(pmu_hal_context_t *hal);
|
||||
|
||||
void pmu_hal_hp_set_control_ready_wait_cycle(pmu_hal_context_t *hal, uint32_t isolate_wait_cycle, uint32_t reset_wait_cycle);
|
||||
|
||||
void pmu_hal_lp_set_control_ready_wait_cycle(pmu_hal_context_t *hal, uint32_t isolate_wait_cycle, uint32_t reset_wait_cycle);
|
||||
|
||||
void pmu_hal_hp_set_sleep_active_backup_enable(pmu_hal_context_t *hal);
|
||||
|
||||
void pmu_hal_hp_set_sleep_active_backup_disable(pmu_hal_context_t *hal);
|
||||
|
||||
void pmu_hal_hp_set_sleep_modem_backup_enable(pmu_hal_context_t *hal);
|
||||
|
||||
void pmu_hal_hp_set_sleep_modem_backup_disable(pmu_hal_context_t *hal);
|
||||
|
||||
void pmu_hal_hp_set_modem_active_backup_enable(pmu_hal_context_t *hal);
|
||||
|
||||
void pmu_hal_hp_set_modem_active_backup_disable(pmu_hal_context_t *hal);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,729 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The LL layer for ESP32-C6 PMU register operations
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <stdbool.h>
|
||||
#include "soc/soc.h"
|
||||
#include "esp_attr.h"
|
||||
#include "hal/assert.h"
|
||||
#include "soc/pmu_struct.h"
|
||||
#include "hal/pmu_types.h"
|
||||
#include "hal/misc.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Set the power domain that needs to be powered down in the digital power
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param mode The pmu mode
|
||||
* @param flag Digital power domain flag
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_dig_power(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t flag)
|
||||
{
|
||||
hw->hp_sys[mode].dig_power.val = flag;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_func(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t icg_func)
|
||||
{
|
||||
hw->hp_sys[mode].icg_func = icg_func;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_apb(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t bitmap)
|
||||
{
|
||||
hw->hp_sys[mode].icg_apb = bitmap;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_modem(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t code)
|
||||
{
|
||||
hw->hp_sys[mode].icg_modem.code = code;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_uart_wakeup_enable(pmu_dev_t *hw, pmu_hp_mode_t mode, bool wakeup_en)
|
||||
{
|
||||
hw->hp_sys[mode].syscntl.uart_wakeup_en = wakeup_en;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_hold_all_lp_pad(pmu_dev_t *hw, pmu_hp_mode_t mode, bool hold_all)
|
||||
{
|
||||
hw->hp_sys[mode].syscntl.lp_pad_hold_all = hold_all;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_hold_all_hp_pad(pmu_dev_t *hw, pmu_hp_mode_t mode, bool hold_all)
|
||||
{
|
||||
hw->hp_sys[mode].syscntl.hp_pad_hold_all = hold_all;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_dig_pad_slp_sel(pmu_dev_t *hw, pmu_hp_mode_t mode, bool slp_sel)
|
||||
{
|
||||
hw->hp_sys[mode].syscntl.dig_pad_slp_sel = slp_sel;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_pause_watchdog(pmu_dev_t *hw, pmu_hp_mode_t mode, bool pause_wdt)
|
||||
{
|
||||
hw->hp_sys[mode].syscntl.dig_pause_wdt = pause_wdt;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_cpu_stall(pmu_dev_t *hw, pmu_hp_mode_t mode, bool cpu_stall)
|
||||
{
|
||||
hw->hp_sys[mode].syscntl.dig_cpu_stall = cpu_stall;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the power domain that needs to be powered down in the clock power
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param mode The pmu mode
|
||||
* @param flag Clock power domain flag
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_clk_power(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t xpd_flag)
|
||||
{
|
||||
hw->hp_sys[mode].clk_power.val = xpd_flag;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_xtal_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool xpd_xtal)
|
||||
{
|
||||
hw->hp_sys[mode].xtal.xpd_xtal = xpd_xtal;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_bias_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool xpd_bias)
|
||||
{
|
||||
hw->hp_sys[mode].bias.xpd_bias = xpd_bias;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_dbg_atten(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t value)
|
||||
{
|
||||
hw->hp_sys[mode].bias.dbg_atten = value;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_current_power_off(pmu_dev_t *hw, pmu_hp_mode_t mode, bool off)
|
||||
{
|
||||
hw->hp_sys[mode].bias.pd_cur = off;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_bias_sleep_enable(pmu_dev_t *hw, pmu_hp_mode_t mode, bool en)
|
||||
{
|
||||
hw->hp_sys[mode].bias.bias_sleep = en;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_retention_param(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t param)
|
||||
{
|
||||
hw->hp_sys[mode].backup.val = param;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_to_active_backup_enable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_sys[PMU_MODE_HP_ACTIVE].backup.hp_sleep2active_backup_en = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_to_active_backup_disable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_sys[PMU_MODE_HP_ACTIVE].backup.hp_sleep2active_backup_en = 0;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_modem_to_active_backup_enable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_sys[PMU_MODE_HP_ACTIVE].backup.hp_modem2active_backup_en = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_modem_to_active_backup_disable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_sys[PMU_MODE_HP_ACTIVE].backup.hp_modem2active_backup_en = 0;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_to_modem_backup_enable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_sys[PMU_MODE_HP_MODEM].backup.hp_sleep2modem_backup_en = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_to_modem_backup_disable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_sys[PMU_MODE_HP_MODEM].backup.hp_sleep2modem_backup_en = 0;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_active_to_sleep_backup_enable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_sys[PMU_MODE_HP_SLEEP].backup.hp_active2sleep_backup_en = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_active_to_sleep_backup_disable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_sys[PMU_MODE_HP_SLEEP].backup.hp_active2sleep_backup_en = 0;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_modem_to_sleep_backup_enable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_sys[PMU_MODE_HP_SLEEP].backup.hp_modem2sleep_backup_en = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_modem_to_sleep_backup_disable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_sys[PMU_MODE_HP_SLEEP].backup.hp_modem2sleep_backup_en = 0;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_backup_icg_func(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t icg_func)
|
||||
{
|
||||
hw->hp_sys[mode].backup_clk = icg_func;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_sysclk_nodiv(pmu_dev_t *hw, pmu_hp_mode_t mode, bool sysclk_nodiv)
|
||||
{
|
||||
hw->hp_sys[mode].sysclk.dig_sysclk_nodiv = sysclk_nodiv;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_sysclk_enable(pmu_dev_t *hw, pmu_hp_mode_t mode, bool icg_sysclk_en)
|
||||
{
|
||||
hw->hp_sys[mode].sysclk.icg_sysclk_en = icg_sysclk_en;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_sysclk_slp_sel(pmu_dev_t *hw, pmu_hp_mode_t mode, bool slp_sel)
|
||||
{
|
||||
hw->hp_sys[mode].sysclk.sysclk_slp_sel = slp_sel;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_sysclk_slp_sel(pmu_dev_t *hw, pmu_hp_mode_t mode, bool slp_sel)
|
||||
{
|
||||
hw->hp_sys[mode].sysclk.icg_slp_sel = slp_sel;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_dig_sysclk(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t sysclk_sel)
|
||||
{
|
||||
hw->hp_sys[mode].sysclk.dig_sysclk_sel = sysclk_sel;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_sleep_logic_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool slp_xpd)
|
||||
{
|
||||
hw->hp_sys[mode].regulator0.slp_logic_xpd = slp_xpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_sleep_memory_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool slp_xpd)
|
||||
{
|
||||
hw->hp_sys[mode].regulator0.slp_mem_xpd = slp_xpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool xpd)
|
||||
{
|
||||
hw->hp_sys[mode].regulator0.xpd = xpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_sleep_logic_dbias(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t slp_dbias)
|
||||
{
|
||||
hw->hp_sys[mode].regulator0.slp_logic_dbias = slp_dbias;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_sleep_memory_dbias(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t slp_dbias)
|
||||
{
|
||||
hw->hp_sys[mode].regulator0.slp_mem_dbias = slp_dbias;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_dbias(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t dbias)
|
||||
{
|
||||
hw->hp_sys[mode].regulator0.dbias = dbias;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_driver_bar(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t drv_b)
|
||||
{
|
||||
hw->hp_sys[mode].regulator1.drv_b = drv_b;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_regulator_slp_xpd(pmu_dev_t *hw, pmu_lp_mode_t mode, bool slp_xpd)
|
||||
{
|
||||
hw->lp_sys[mode].regulator0.slp_xpd = slp_xpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_regulator_xpd(pmu_dev_t *hw, pmu_lp_mode_t mode, bool xpd)
|
||||
{
|
||||
hw->lp_sys[mode].regulator0.xpd = xpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_regulator_sleep_dbias(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t slp_dbias)
|
||||
{
|
||||
hw->lp_sys[mode].regulator0.slp_dbias = slp_dbias;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_regulator_dbias(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t dbias)
|
||||
{
|
||||
hw->lp_sys[mode].regulator0.dbias = dbias;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_regulator_driver_bar(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t drv_b)
|
||||
{
|
||||
hw->lp_sys[mode].regulator1.drv_b = drv_b;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_xtal_xpd(pmu_dev_t *hw, pmu_lp_mode_t mode, bool xpd_xtal)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
|
||||
hw->lp_sys[mode].xtal.xpd_xtal = xpd_xtal;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_dig_power(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t flag)
|
||||
{
|
||||
hw->lp_sys[mode].dig_power.val = flag;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_clk_power(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t xpd_flag)
|
||||
{
|
||||
hw->lp_sys[mode].clk_power.val = xpd_flag;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_clk_power(pmu_dev_t *hw, pmu_lp_mode_t mode)
|
||||
{
|
||||
return hw->lp_sys[mode].clk_power.val;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_bias_xpd(pmu_dev_t *hw, pmu_lp_mode_t mode, bool xpd_bias)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
|
||||
hw->lp_sys[mode].bias.xpd_bias = xpd_bias;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_dbg_atten(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t value)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
|
||||
hw->lp_sys[mode].bias.dbg_atten = value;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_current_power_off(pmu_dev_t *hw, pmu_lp_mode_t mode, bool off)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
|
||||
hw->lp_sys[mode].bias.pd_cur = off;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_bias_sleep_enable(pmu_dev_t *hw, pmu_lp_mode_t mode, bool en)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
|
||||
hw->lp_sys[mode].bias.bias_sleep = en;
|
||||
}
|
||||
|
||||
/****/
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_set_clk_power(pmu_dev_t *hw, uint32_t flag)
|
||||
{
|
||||
hw->imm.clk_power.val = flag;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_set_icg_slp_sel(pmu_dev_t *hw, bool slp_sel)
|
||||
{
|
||||
if (slp_sel) {
|
||||
hw->imm.sleep_sysclk.tie_high_icg_slp_sel = 1;
|
||||
} else {
|
||||
hw->imm.sleep_sysclk.tie_low_icg_slp_sel = 1;
|
||||
}
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_update_dig_sysclk_sel(pmu_dev_t *hw, bool update)
|
||||
{
|
||||
hw->imm.sleep_sysclk.update_dig_sysclk_sel = update;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_update_dig_icg_switch(pmu_dev_t *hw, bool update)
|
||||
{
|
||||
hw->imm.sleep_sysclk.update_dig_icg_switch = update;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_update_dig_icg_func(pmu_dev_t *hw, bool icg_func_update)
|
||||
{
|
||||
hw->imm.hp_func_icg.update_dig_icg_func_en = icg_func_update;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_update_dig_icg_apb(pmu_dev_t *hw, bool icg_apb_update)
|
||||
{
|
||||
hw->imm.hp_apb_icg.update_dig_icg_apb_en = icg_apb_update;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_update_dig_icg_modem_code(pmu_dev_t *hw, bool icg_modem_update)
|
||||
{
|
||||
hw->imm.modem_icg.update_dig_icg_modem_en = icg_modem_update;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_set_lp_rootclk_sel(pmu_dev_t *hw, bool rootclk_sel)
|
||||
{
|
||||
if (rootclk_sel) {
|
||||
hw->imm.lp_icg.tie_high_lp_rootclk_sel = 1;
|
||||
} else {
|
||||
hw->imm.lp_icg.tie_low_lp_rootclk_sel = 1;
|
||||
}
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_set_hp_pad_hold_all(pmu_dev_t *hw, bool hold_all)
|
||||
{
|
||||
if (hold_all) {
|
||||
hw->imm.pad_hold_all.tie_high_hp_pad_hold_all = 1;
|
||||
} else {
|
||||
hw->imm.pad_hold_all.tie_low_hp_pad_hold_all = 1;
|
||||
}
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_set_lp_pad_hold_all(pmu_dev_t *hw, bool hold_all)
|
||||
{
|
||||
if (hold_all) {
|
||||
hw->imm.pad_hold_all.tie_high_lp_pad_hold_all = 1;
|
||||
} else {
|
||||
hw->imm.pad_hold_all.tie_low_lp_pad_hold_all = 1;
|
||||
}
|
||||
}
|
||||
|
||||
/*** */
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_reset(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool rst)
|
||||
{
|
||||
hw->power.hp_pd[domain].force_reset = rst;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_isolate(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool iso)
|
||||
{
|
||||
hw->power.hp_pd[domain].force_iso = iso;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_power_up(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool fpu)
|
||||
{
|
||||
hw->power.hp_pd[domain].force_pu = fpu;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_no_reset(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool no_rst)
|
||||
{
|
||||
hw->power.hp_pd[domain].force_no_reset = no_rst;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_no_isolate(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool no_iso)
|
||||
{
|
||||
hw->power.hp_pd[domain].force_no_iso = no_iso;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_power_down(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool fpd)
|
||||
{
|
||||
hw->power.hp_pd[domain].force_pd = fpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_reset(pmu_dev_t *hw, bool rst)
|
||||
{
|
||||
hw->power.lp_peri.force_reset = rst;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_isolate(pmu_dev_t *hw, bool iso)
|
||||
{
|
||||
hw->power.lp_peri.force_iso = iso;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_power_up(pmu_dev_t *hw, bool fpu)
|
||||
{
|
||||
hw->power.lp_peri.force_pu = fpu;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_no_reset(pmu_dev_t *hw, bool no_rst)
|
||||
{
|
||||
hw->power.lp_peri.force_no_reset = no_rst;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_no_isolate(pmu_dev_t *hw, bool no_iso)
|
||||
{
|
||||
hw->power.lp_peri.force_no_iso = no_iso;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_power_down(pmu_dev_t *hw, bool fpd)
|
||||
{
|
||||
hw->power.lp_peri.force_pd = fpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_memory_isolate(pmu_dev_t *hw, uint32_t iso)
|
||||
{
|
||||
hw->power.mem_cntl.force_hp_mem_iso = iso;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_memory_power_down(pmu_dev_t *hw, uint32_t fpd)
|
||||
{
|
||||
hw->power.mem_cntl.force_hp_mem_pd = fpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_memory_no_isolate(pmu_dev_t *hw, uint32_t no_iso)
|
||||
{
|
||||
hw->power.mem_cntl.force_hp_mem_no_iso = no_iso;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_memory_power_up(pmu_dev_t *hw, uint32_t fpu)
|
||||
{
|
||||
hw->power.mem_cntl.force_hp_mem_pu = fpu;
|
||||
}
|
||||
|
||||
/*** */
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_enable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->wakeup.cntl0.sleep_req = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_reject_enable(pmu_dev_t *hw, uint32_t reject)
|
||||
{
|
||||
hw->wakeup.cntl1.sleep_reject_ena = reject;
|
||||
hw->wakeup.cntl1.slp_reject_en = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_reject_disable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->wakeup.cntl1.slp_reject_en = 0;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_wakeup_enable(pmu_dev_t *hw, uint32_t wakeup)
|
||||
{
|
||||
hw->wakeup.cntl2 = wakeup;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_protect_mode(pmu_dev_t *hw, int mode)
|
||||
{
|
||||
hw->wakeup.cntl3.sleep_prt_sel = mode;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_min_sleep_cycle(pmu_dev_t *hw, uint32_t slow_clk_cycle)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wakeup.cntl3, hp_min_slp_val, slow_clk_cycle);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_clear_reject_cause(pmu_dev_t *hw)
|
||||
{
|
||||
hw->wakeup.cntl4.slp_reject_cause_clr = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR bool pmu_ll_hp_is_sleep_wakeup(pmu_dev_t *hw)
|
||||
{
|
||||
return (hw->hp_ext.int_raw.wakeup == 1);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR bool pmu_ll_hp_is_sleep_reject(pmu_dev_t *hw)
|
||||
{
|
||||
return (hw->hp_ext.int_raw.reject == 1);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_clear_sw_intr_status(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_ext.int_clr.sw = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_clear_wakeup_intr_status(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_ext.int_clr.wakeup = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_clear_reject_intr_status(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_ext.int_clr.reject = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_enable_sw_intr(pmu_dev_t *hw, bool enable)
|
||||
{
|
||||
hw->hp_ext.int_ena.sw = enable;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_wakeup_cause(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->wakeup.status0;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_reject_cause(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->wakeup.status1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_min_sleep_cycle(pmu_dev_t *hw, uint32_t slow_clk_cycle)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wakeup.cntl3, lp_min_slp_val, slow_clk_cycle);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_modify_icg_cntl_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hp_ext.clk_cntl, modify_icg_cntl_wait, cycle);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_modify_icg_cntl_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return HAL_FORCE_READ_U32_REG_FIELD(hw->hp_ext.clk_cntl, modify_icg_cntl_wait);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_switch_icg_cntl_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hp_ext.clk_cntl, switch_icg_cntl_wait, cycle);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_switch_icg_cntl_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return HAL_FORCE_READ_U32_REG_FIELD(hw->hp_ext.clk_cntl, switch_icg_cntl_wait);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_digital_power_down_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
hw->power.wait_timer0.powerdown_timer = cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_digital_power_down_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->power.wait_timer0.powerdown_timer;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_digital_power_down_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
hw->power.wait_timer1.powerdown_timer = cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_digital_power_down_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->power.wait_timer1.powerdown_timer;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_analog_wait_target_cycle(pmu_dev_t *hw, uint32_t slow_clk_cycle)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wakeup.cntl5, lp_ana_wait_target, slow_clk_cycle);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_analog_wait_target_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return HAL_FORCE_READ_U32_REG_FIELD(hw->wakeup.cntl5, lp_ana_wait_target);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_set_modem_wait_target_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
hw->wakeup.cntl5.modem_wait_target = cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_get_modem_wait_target_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->wakeup.cntl5.modem_wait_target;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_set_xtal_stable_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->power.clk_wait, wait_xtal_stable, cycle);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_get_xtal_stable_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return HAL_FORCE_READ_U32_REG_FIELD(hw->power.clk_wait, wait_xtal_stable);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_set_pll_stable_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->power.clk_wait, wait_pll_stable, cycle);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_get_pll_stable_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return HAL_FORCE_READ_U32_REG_FIELD(hw->power.clk_wait, wait_pll_stable);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_digital_power_supply_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
hw->power.wait_timer1.wait_timer = cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_digital_power_supply_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->power.wait_timer1.wait_timer;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_digital_power_up_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
hw->power.wait_timer1.powerup_timer = cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_digital_power_up_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->power.wait_timer1.powerup_timer;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_isolate_wait_cycle(pmu_dev_t *hw, uint32_t isolate_wait_cycle)
|
||||
{
|
||||
hw->power.wait_timer2.lp_iso_wait_timer = isolate_wait_cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_reset_wait_cycle(pmu_dev_t *hw, uint32_t reset_wait_cycle)
|
||||
{
|
||||
hw->power.wait_timer2.lp_rst_wait_timer = reset_wait_cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_isolate_wait_cycle(pmu_dev_t *hw, uint32_t isolate_wait_cycle)
|
||||
{
|
||||
hw->power.wait_timer2.hp_iso_wait_timer = isolate_wait_cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_reset_wait_cycle(pmu_dev_t *hw, uint32_t reset_wait_cycle)
|
||||
{
|
||||
hw->power.wait_timer2.hp_rst_wait_timer = reset_wait_cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_analog_wait_target_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wakeup.cntl7, ana_wait_target, cycle);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_analog_wait_target_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return HAL_FORCE_READ_U32_REG_FIELD(hw->wakeup.cntl7, ana_wait_target);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_digital_power_supply_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
hw->power.wait_timer0.wait_timer = cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_digital_power_supply_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->power.wait_timer0.wait_timer;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_digital_power_up_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
hw->power.wait_timer0.powerup_timer = cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_digital_power_up_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->power.wait_timer0.powerup_timer;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_get_sysclk_sleep_select_state(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->clk_state0.sysclk_slp_sel;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_interrupt_raw(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->lp_ext.int_raw.val;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_clear_intsts_mask(pmu_dev_t *hw, uint32_t mask)
|
||||
{
|
||||
hw->lp_ext.int_clr.val = mask;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_trigger_sw_intr(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_lp_cpu_comm.lp_trigger_hp = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_trigger_sw_intr(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_lp_cpu_comm.hp_trigger_lp = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_clear_sw_intr_status(pmu_dev_t *hw)
|
||||
{
|
||||
hw->lp_ext.int_clr.sw_trigger = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_enable_sw_intr(pmu_dev_t *hw, bool enable)
|
||||
{
|
||||
hw->lp_ext.int_ena.sw_trigger = enable;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,82 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The HAL layer for PMU (ESP32-C5 specific part)
|
||||
|
||||
#include "soc/soc.h"
|
||||
#include "esp_attr.h"
|
||||
#include "hal/pmu_hal.h"
|
||||
#include "hal/pmu_types.h"
|
||||
|
||||
void pmu_hal_hp_set_digital_power_up_wait_cycle(pmu_hal_context_t *hal, uint32_t power_supply_wait_cycle, uint32_t power_up_wait_cycle)
|
||||
{
|
||||
pmu_ll_hp_set_digital_power_supply_wait_cycle(hal->dev, power_supply_wait_cycle);
|
||||
pmu_ll_hp_set_digital_power_up_wait_cycle(hal->dev, power_up_wait_cycle);
|
||||
}
|
||||
|
||||
uint32_t pmu_hal_hp_get_digital_power_up_wait_cycle(pmu_hal_context_t *hal)
|
||||
{
|
||||
uint32_t power_supply_wait_cycle = pmu_ll_hp_get_digital_power_supply_wait_cycle(hal->dev);
|
||||
uint32_t power_up_wait_cycle = pmu_ll_hp_get_digital_power_up_wait_cycle(hal->dev);
|
||||
return power_supply_wait_cycle + power_up_wait_cycle;
|
||||
}
|
||||
|
||||
void pmu_hal_lp_set_digital_power_up_wait_cycle(pmu_hal_context_t *hal, uint32_t power_supply_wait_cycle, uint32_t power_up_wait_cycle)
|
||||
{
|
||||
pmu_ll_lp_set_digital_power_supply_wait_cycle(hal->dev, power_supply_wait_cycle);
|
||||
pmu_ll_lp_set_digital_power_up_wait_cycle(hal->dev, power_up_wait_cycle);
|
||||
}
|
||||
|
||||
uint32_t pmu_hal_lp_get_digital_power_up_wait_cycle(pmu_hal_context_t *hal)
|
||||
{
|
||||
uint32_t power_supply_wait_cycle = pmu_ll_lp_get_digital_power_supply_wait_cycle(hal->dev);
|
||||
uint32_t power_up_wait_cycle = pmu_ll_lp_get_digital_power_up_wait_cycle(hal->dev);
|
||||
return power_supply_wait_cycle + power_up_wait_cycle;
|
||||
}
|
||||
|
||||
void pmu_hal_hp_set_control_ready_wait_cycle(pmu_hal_context_t *hal, uint32_t isolate_wait_cycle, uint32_t reset_wait_cycle)
|
||||
{
|
||||
pmu_ll_hp_set_isolate_wait_cycle(hal->dev, isolate_wait_cycle);
|
||||
pmu_ll_hp_set_reset_wait_cycle(hal->dev, reset_wait_cycle);
|
||||
}
|
||||
|
||||
void pmu_hal_lp_set_control_ready_wait_cycle(pmu_hal_context_t *hal, uint32_t isolate_wait_cycle, uint32_t reset_wait_cycle)
|
||||
{
|
||||
pmu_ll_lp_set_isolate_wait_cycle(hal->dev, isolate_wait_cycle);
|
||||
pmu_ll_lp_set_reset_wait_cycle(hal->dev, reset_wait_cycle);
|
||||
}
|
||||
|
||||
void pmu_hal_hp_set_sleep_active_backup_enable(pmu_hal_context_t *hal)
|
||||
{
|
||||
pmu_ll_hp_set_active_to_sleep_backup_enable(hal->dev);
|
||||
pmu_ll_hp_set_sleep_to_active_backup_enable(hal->dev);
|
||||
}
|
||||
|
||||
void pmu_hal_hp_set_sleep_active_backup_disable(pmu_hal_context_t *hal)
|
||||
{
|
||||
pmu_ll_hp_set_sleep_to_active_backup_disable(hal->dev);
|
||||
pmu_ll_hp_set_active_to_sleep_backup_disable(hal->dev);
|
||||
}
|
||||
|
||||
void pmu_hal_hp_set_sleep_modem_backup_enable(pmu_hal_context_t *hal)
|
||||
{
|
||||
pmu_ll_hp_set_sleep_to_modem_backup_enable(hal->dev);
|
||||
}
|
||||
|
||||
void pmu_hal_hp_set_sleep_modem_backup_disable(pmu_hal_context_t *hal)
|
||||
{
|
||||
pmu_ll_hp_set_sleep_to_modem_backup_disable(hal->dev);
|
||||
}
|
||||
|
||||
void pmu_hal_hp_set_modem_active_backup_enable(pmu_hal_context_t *hal)
|
||||
{
|
||||
pmu_ll_hp_set_modem_to_active_backup_enable(hal->dev);
|
||||
}
|
||||
|
||||
void pmu_hal_hp_set_modem_active_backup_disable(pmu_hal_context_t *hal)
|
||||
{
|
||||
pmu_ll_hp_set_modem_to_active_backup_disable(hal->dev);
|
||||
}
|
||||
@@ -0,0 +1,45 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The HAL layer for PMU
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "soc/soc_caps.h"
|
||||
#include "hal/pmu_ll.h"
|
||||
#include "hal/pmu_types.h"
|
||||
|
||||
typedef struct {
|
||||
pmu_dev_t *dev;
|
||||
} pmu_hal_context_t;
|
||||
|
||||
void pmu_hal_hp_set_digital_power_up_wait_cycle(pmu_hal_context_t *hal, uint32_t power_supply_wait_cycle, uint32_t power_up_wait_cycle);
|
||||
|
||||
uint32_t pmu_hal_hp_get_digital_power_up_wait_cycle(pmu_hal_context_t *hal);
|
||||
|
||||
void pmu_hal_lp_set_digital_power_up_wait_cycle(pmu_hal_context_t *hal, uint32_t power_supply_wait_cycle, uint32_t power_up_wait_cycle);
|
||||
|
||||
uint32_t pmu_hal_lp_get_digital_power_up_wait_cycle(pmu_hal_context_t *hal);
|
||||
|
||||
void pmu_hal_hp_set_sleep_active_backup_enable(pmu_hal_context_t *hal);
|
||||
|
||||
void pmu_hal_hp_set_sleep_active_backup_disable(pmu_hal_context_t *hal);
|
||||
|
||||
void pmu_hal_hp_set_sleep_modem_backup_enable(pmu_hal_context_t *hal);
|
||||
|
||||
void pmu_hal_hp_set_sleep_modem_backup_disable(pmu_hal_context_t *hal);
|
||||
|
||||
void pmu_hal_hp_set_modem_active_backup_enable(pmu_hal_context_t *hal);
|
||||
|
||||
void pmu_hal_hp_set_modem_active_backup_disable(pmu_hal_context_t *hal);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,709 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The LL layer for ESP32-C6 PMU register operations
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <stdbool.h>
|
||||
#include "soc/soc.h"
|
||||
#include "esp_attr.h"
|
||||
#include "hal/assert.h"
|
||||
#include "soc/pmu_struct.h"
|
||||
#include "hal/pmu_types.h"
|
||||
#include "hal/misc.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Set the power domain that needs to be powered down in the digital power
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param mode The pmu mode
|
||||
* @param flag Digital power domain flag
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_dig_power(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t flag)
|
||||
{
|
||||
hw->hp_sys[mode].dig_power.val = flag;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_func(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t icg_func)
|
||||
{
|
||||
hw->hp_sys[mode].icg_func = icg_func;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_apb(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t bitmap)
|
||||
{
|
||||
hw->hp_sys[mode].icg_apb = bitmap;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_modem(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t code)
|
||||
{
|
||||
hw->hp_sys[mode].icg_modem.code = code;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_uart_wakeup_enable(pmu_dev_t *hw, pmu_hp_mode_t mode, bool wakeup_en)
|
||||
{
|
||||
hw->hp_sys[mode].syscntl.uart_wakeup_en = wakeup_en;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_hold_all_lp_pad(pmu_dev_t *hw, pmu_hp_mode_t mode, bool hold_all)
|
||||
{
|
||||
hw->hp_sys[mode].syscntl.lp_pad_hold_all = hold_all;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_hold_all_hp_pad(pmu_dev_t *hw, pmu_hp_mode_t mode, bool hold_all)
|
||||
{
|
||||
hw->hp_sys[mode].syscntl.hp_pad_hold_all = hold_all;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_dig_pad_slp_sel(pmu_dev_t *hw, pmu_hp_mode_t mode, bool slp_sel)
|
||||
{
|
||||
hw->hp_sys[mode].syscntl.dig_pad_slp_sel = slp_sel;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_pause_watchdog(pmu_dev_t *hw, pmu_hp_mode_t mode, bool pause_wdt)
|
||||
{
|
||||
hw->hp_sys[mode].syscntl.dig_pause_wdt = pause_wdt;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_cpu_stall(pmu_dev_t *hw, pmu_hp_mode_t mode, bool cpu_stall)
|
||||
{
|
||||
hw->hp_sys[mode].syscntl.dig_cpu_stall = cpu_stall;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the power domain that needs to be powered down in the clock power
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param mode The pmu mode
|
||||
* @param flag Clock power domain flag
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_clk_power(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t xpd_flag)
|
||||
{
|
||||
hw->hp_sys[mode].clk_power.val = xpd_flag;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_xtal_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool xpd_xtal)
|
||||
{
|
||||
hw->hp_sys[mode].xtal.xpd_xtal = xpd_xtal;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_bias_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool xpd_bias)
|
||||
{
|
||||
hw->hp_sys[mode].bias.xpd_bias = xpd_bias;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_dbg_atten(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t value)
|
||||
{
|
||||
hw->hp_sys[mode].bias.dbg_atten = value;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_current_power_off(pmu_dev_t *hw, pmu_hp_mode_t mode, bool off)
|
||||
{
|
||||
hw->hp_sys[mode].bias.pd_cur = off;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_bias_sleep_enable(pmu_dev_t *hw, pmu_hp_mode_t mode, bool en)
|
||||
{
|
||||
hw->hp_sys[mode].bias.bias_sleep = en;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_retention_param(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t param)
|
||||
{
|
||||
hw->hp_sys[mode].backup.val = param;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_to_active_backup_enable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_sys[PMU_MODE_HP_ACTIVE].backup.hp_sleep2active_backup_en = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_to_active_backup_disable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_sys[PMU_MODE_HP_ACTIVE].backup.hp_sleep2active_backup_en = 0;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_modem_to_active_backup_enable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_sys[PMU_MODE_HP_ACTIVE].backup.hp_modem2active_backup_en = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_modem_to_active_backup_disable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_sys[PMU_MODE_HP_ACTIVE].backup.hp_modem2active_backup_en = 0;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_to_modem_backup_enable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_sys[PMU_MODE_HP_MODEM].backup.hp_sleep2modem_backup_en = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_to_modem_backup_disable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_sys[PMU_MODE_HP_MODEM].backup.hp_sleep2modem_backup_en = 0;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_active_to_sleep_backup_enable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_sys[PMU_MODE_HP_SLEEP].backup.hp_active2sleep_backup_en = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_active_to_sleep_backup_disable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_sys[PMU_MODE_HP_SLEEP].backup.hp_active2sleep_backup_en = 0;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_modem_to_sleep_backup_enable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_sys[PMU_MODE_HP_SLEEP].backup.hp_modem2sleep_backup_en = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_modem_to_sleep_backup_disable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_sys[PMU_MODE_HP_SLEEP].backup.hp_modem2sleep_backup_en = 0;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_backup_icg_func(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t icg_func)
|
||||
{
|
||||
hw->hp_sys[mode].backup_clk = icg_func;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_sysclk_nodiv(pmu_dev_t *hw, pmu_hp_mode_t mode, bool sysclk_nodiv)
|
||||
{
|
||||
hw->hp_sys[mode].sysclk.dig_sysclk_nodiv = sysclk_nodiv;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_sysclk_enable(pmu_dev_t *hw, pmu_hp_mode_t mode, bool icg_sysclk_en)
|
||||
{
|
||||
hw->hp_sys[mode].sysclk.icg_sysclk_en = icg_sysclk_en;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_sysclk_slp_sel(pmu_dev_t *hw, pmu_hp_mode_t mode, bool slp_sel)
|
||||
{
|
||||
hw->hp_sys[mode].sysclk.sysclk_slp_sel = slp_sel;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_sysclk_slp_sel(pmu_dev_t *hw, pmu_hp_mode_t mode, bool slp_sel)
|
||||
{
|
||||
hw->hp_sys[mode].sysclk.icg_slp_sel = slp_sel;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_dig_sysclk(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t sysclk_sel)
|
||||
{
|
||||
hw->hp_sys[mode].sysclk.dig_sysclk_sel = sysclk_sel;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_sleep_logic_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool slp_xpd)
|
||||
{
|
||||
hw->hp_sys[mode].regulator0.slp_logic_xpd = slp_xpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_sleep_memory_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool slp_xpd)
|
||||
{
|
||||
hw->hp_sys[mode].regulator0.slp_mem_xpd = slp_xpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool xpd)
|
||||
{
|
||||
hw->hp_sys[mode].regulator0.xpd = xpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_sleep_logic_dbias(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t slp_dbias)
|
||||
{
|
||||
hw->hp_sys[mode].regulator0.slp_logic_dbias = slp_dbias;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_sleep_memory_dbias(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t slp_dbias)
|
||||
{
|
||||
hw->hp_sys[mode].regulator0.slp_mem_dbias = slp_dbias;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_dbias(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t dbias)
|
||||
{
|
||||
hw->hp_sys[mode].regulator0.dbias = dbias;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_driver_bar(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t drv_b)
|
||||
{
|
||||
hw->hp_sys[mode].regulator1.drv_b = drv_b;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_regulator_slp_xpd(pmu_dev_t *hw, pmu_lp_mode_t mode, bool slp_xpd)
|
||||
{
|
||||
hw->lp_sys[mode].regulator0.slp_xpd = slp_xpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_regulator_xpd(pmu_dev_t *hw, pmu_lp_mode_t mode, bool xpd)
|
||||
{
|
||||
hw->lp_sys[mode].regulator0.xpd = xpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_regulator_sleep_dbias(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t slp_dbias)
|
||||
{
|
||||
hw->lp_sys[mode].regulator0.slp_dbias = slp_dbias;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_regulator_dbias(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t dbias)
|
||||
{
|
||||
hw->lp_sys[mode].regulator0.dbias = dbias;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_regulator_driver_bar(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t drv_b)
|
||||
{
|
||||
hw->lp_sys[mode].regulator1.drv_b = drv_b;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_xtal_xpd(pmu_dev_t *hw, pmu_lp_mode_t mode, bool xpd_xtal)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
|
||||
hw->lp_sys[mode].xtal.xpd_xtal = xpd_xtal;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_dig_power(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t flag)
|
||||
{
|
||||
hw->lp_sys[mode].dig_power.val = flag;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_clk_power(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t xpd_flag)
|
||||
{
|
||||
hw->lp_sys[mode].clk_power.val = xpd_flag;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_clk_power(pmu_dev_t *hw, pmu_lp_mode_t mode)
|
||||
{
|
||||
return hw->lp_sys[mode].clk_power.val;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_bias_xpd(pmu_dev_t *hw, pmu_lp_mode_t mode, bool xpd_bias)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
|
||||
hw->lp_sys[mode].bias.xpd_bias = xpd_bias;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_dbg_atten(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t value)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
|
||||
hw->lp_sys[mode].bias.dbg_atten = value;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_current_power_off(pmu_dev_t *hw, pmu_lp_mode_t mode, bool off)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
|
||||
hw->lp_sys[mode].bias.pd_cur = off;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_bias_sleep_enable(pmu_dev_t *hw, pmu_lp_mode_t mode, bool en)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
|
||||
hw->lp_sys[mode].bias.bias_sleep = en;
|
||||
}
|
||||
|
||||
/****/
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_set_clk_power(pmu_dev_t *hw, uint32_t flag)
|
||||
{
|
||||
hw->imm.clk_power.val = flag;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_set_icg_slp_sel(pmu_dev_t *hw, bool slp_sel)
|
||||
{
|
||||
if (slp_sel) {
|
||||
hw->imm.sleep_sysclk.tie_high_icg_slp_sel = 1;
|
||||
} else {
|
||||
hw->imm.sleep_sysclk.tie_low_icg_slp_sel = 1;
|
||||
}
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_update_dig_sysclk_sel(pmu_dev_t *hw, bool update)
|
||||
{
|
||||
hw->imm.sleep_sysclk.update_dig_sysclk_sel = update;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_update_dig_icg_switch(pmu_dev_t *hw, bool update)
|
||||
{
|
||||
hw->imm.sleep_sysclk.update_dig_icg_switch = update;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_update_dig_icg_func(pmu_dev_t *hw, bool icg_func_update)
|
||||
{
|
||||
hw->imm.hp_func_icg.update_dig_icg_func_en = icg_func_update;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_update_dig_icg_apb(pmu_dev_t *hw, bool icg_apb_update)
|
||||
{
|
||||
hw->imm.hp_apb_icg.update_dig_icg_apb_en = icg_apb_update;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_update_dig_icg_modem_code(pmu_dev_t *hw, bool icg_modem_update)
|
||||
{
|
||||
hw->imm.modem_icg.update_dig_icg_modem_en = icg_modem_update;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_set_lp_rootclk_sel(pmu_dev_t *hw, bool rootclk_sel)
|
||||
{
|
||||
if (rootclk_sel) {
|
||||
hw->imm.lp_icg.tie_high_lp_rootclk_sel = 1;
|
||||
} else {
|
||||
hw->imm.lp_icg.tie_low_lp_rootclk_sel = 1;
|
||||
}
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_set_hp_pad_hold_all(pmu_dev_t *hw, bool hold_all)
|
||||
{
|
||||
if (hold_all) {
|
||||
hw->imm.pad_hold_all.tie_high_hp_pad_hold_all = 1;
|
||||
} else {
|
||||
hw->imm.pad_hold_all.tie_low_hp_pad_hold_all = 1;
|
||||
}
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_set_lp_pad_hold_all(pmu_dev_t *hw, bool hold_all)
|
||||
{
|
||||
if (hold_all) {
|
||||
hw->imm.pad_hold_all.tie_high_lp_pad_hold_all = 1;
|
||||
} else {
|
||||
hw->imm.pad_hold_all.tie_low_lp_pad_hold_all = 1;
|
||||
}
|
||||
}
|
||||
|
||||
/*** */
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_reset(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool rst)
|
||||
{
|
||||
hw->power.hp_pd[domain].force_reset = rst;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_isolate(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool iso)
|
||||
{
|
||||
hw->power.hp_pd[domain].force_iso = iso;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_power_up(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool fpu)
|
||||
{
|
||||
hw->power.hp_pd[domain].force_pu = fpu;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_no_reset(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool no_rst)
|
||||
{
|
||||
hw->power.hp_pd[domain].force_no_reset = no_rst;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_no_isolate(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool no_iso)
|
||||
{
|
||||
hw->power.hp_pd[domain].force_no_iso = no_iso;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_power_down(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool fpd)
|
||||
{
|
||||
hw->power.hp_pd[domain].force_pd = fpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_reset(pmu_dev_t *hw, bool rst)
|
||||
{
|
||||
hw->power.lp_peri.force_reset = rst;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_isolate(pmu_dev_t *hw, bool iso)
|
||||
{
|
||||
hw->power.lp_peri.force_iso = iso;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_power_up(pmu_dev_t *hw, bool fpu)
|
||||
{
|
||||
hw->power.lp_peri.force_pu = fpu;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_no_reset(pmu_dev_t *hw, bool no_rst)
|
||||
{
|
||||
hw->power.lp_peri.force_no_reset = no_rst;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_no_isolate(pmu_dev_t *hw, bool no_iso)
|
||||
{
|
||||
hw->power.lp_peri.force_no_iso = no_iso;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_power_down(pmu_dev_t *hw, bool fpd)
|
||||
{
|
||||
hw->power.lp_peri.force_pd = fpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_memory_isolate(pmu_dev_t *hw, uint32_t iso)
|
||||
{
|
||||
hw->power.mem_cntl.force_hp_mem_iso = iso;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_memory_power_down(pmu_dev_t *hw, uint32_t fpd)
|
||||
{
|
||||
hw->power.mem_cntl.force_hp_mem_pd = fpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_memory_no_isolate(pmu_dev_t *hw, uint32_t no_iso)
|
||||
{
|
||||
hw->power.mem_cntl.force_hp_mem_no_iso = no_iso;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_memory_power_up(pmu_dev_t *hw, uint32_t fpu)
|
||||
{
|
||||
hw->power.mem_cntl.force_hp_mem_pu = fpu;
|
||||
}
|
||||
|
||||
/*** */
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_enable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->wakeup.cntl0.sleep_req = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_reject_enable(pmu_dev_t *hw, uint32_t reject)
|
||||
{
|
||||
hw->wakeup.cntl1.sleep_reject_ena = reject;
|
||||
hw->wakeup.cntl1.slp_reject_en = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_reject_disable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->wakeup.cntl1.slp_reject_en = 0;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_wakeup_enable(pmu_dev_t *hw, uint32_t wakeup)
|
||||
{
|
||||
hw->wakeup.cntl2 = wakeup;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_protect_mode(pmu_dev_t *hw, int mode)
|
||||
{
|
||||
hw->wakeup.cntl3.sleep_prt_sel = mode;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_min_sleep_cycle(pmu_dev_t *hw, uint32_t slow_clk_cycle)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wakeup.cntl3, hp_min_slp_val, slow_clk_cycle);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_clear_reject_cause(pmu_dev_t *hw)
|
||||
{
|
||||
hw->wakeup.cntl4.slp_reject_cause_clr = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR bool pmu_ll_hp_is_sleep_wakeup(pmu_dev_t *hw)
|
||||
{
|
||||
return (hw->hp_ext.int_raw.wakeup == 1);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR bool pmu_ll_hp_is_sleep_reject(pmu_dev_t *hw)
|
||||
{
|
||||
return (hw->hp_ext.int_raw.reject == 1);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_clear_sw_intr_status(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_ext.int_clr.sw = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_clear_wakeup_intr_status(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_ext.int_clr.wakeup = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_clear_reject_intr_status(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_ext.int_clr.reject = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_enable_sw_intr(pmu_dev_t *hw, bool enable)
|
||||
{
|
||||
hw->hp_ext.int_ena.sw = enable;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_wakeup_cause(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->wakeup.status0;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_reject_cause(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->wakeup.status1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_interrupt_raw(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->lp_ext.int_raw.val;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_clear_intsts_mask(pmu_dev_t *hw, uint32_t mask)
|
||||
{
|
||||
hw->lp_ext.int_clr.val = mask;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_trigger_sw_intr(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_lp_cpu_comm.lp_trigger_hp = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_trigger_sw_intr(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_lp_cpu_comm.hp_trigger_lp = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_clear_sw_intr_status(pmu_dev_t *hw)
|
||||
{
|
||||
hw->lp_ext.int_clr.sw_trigger = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_enable_sw_intr(pmu_dev_t *hw, bool enable)
|
||||
{
|
||||
hw->lp_ext.int_ena.sw_trigger = enable;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_min_sleep_cycle(pmu_dev_t *hw, uint32_t slow_clk_cycle)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wakeup.cntl3, lp_min_slp_val, slow_clk_cycle);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_modify_icg_cntl_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hp_ext.clk_cntl, modify_icg_cntl_wait, cycle);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_modify_icg_cntl_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return HAL_FORCE_READ_U32_REG_FIELD(hw->hp_ext.clk_cntl, modify_icg_cntl_wait);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_switch_icg_cntl_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hp_ext.clk_cntl, switch_icg_cntl_wait, cycle);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_switch_icg_cntl_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return HAL_FORCE_READ_U32_REG_FIELD(hw->hp_ext.clk_cntl, switch_icg_cntl_wait);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_digital_power_down_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
hw->power.wait_timer0.powerdown_timer = cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_digital_power_down_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->power.wait_timer0.powerdown_timer;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_digital_power_down_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
hw->power.wait_timer1.powerdown_timer = cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_digital_power_down_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->power.wait_timer1.powerdown_timer;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_analog_wait_target_cycle(pmu_dev_t *hw, uint32_t slow_clk_cycle)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wakeup.cntl5, lp_ana_wait_target, slow_clk_cycle);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_analog_wait_target_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return HAL_FORCE_READ_U32_REG_FIELD(hw->wakeup.cntl5, lp_ana_wait_target);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_set_modem_wait_target_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
hw->wakeup.cntl5.modem_wait_target = cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_get_modem_wait_target_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->wakeup.cntl5.modem_wait_target;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_set_xtal_stable_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->power.clk_wait, wait_xtal_stable, cycle);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_get_xtal_stable_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return HAL_FORCE_READ_U32_REG_FIELD(hw->power.clk_wait, wait_xtal_stable);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_set_pll_stable_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->power.clk_wait, wait_pll_stable, cycle);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_get_pll_stable_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return HAL_FORCE_READ_U32_REG_FIELD(hw->power.clk_wait, wait_pll_stable);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_digital_power_supply_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
hw->power.wait_timer1.wait_timer = cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_digital_power_supply_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->power.wait_timer1.wait_timer;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_digital_power_up_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
hw->power.wait_timer1.powerup_timer = cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_digital_power_up_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->power.wait_timer1.powerup_timer;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_analog_wait_target_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wakeup.cntl7, ana_wait_target, cycle);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_analog_wait_target_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return HAL_FORCE_READ_U32_REG_FIELD(hw->wakeup.cntl7, ana_wait_target);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_digital_power_supply_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
hw->power.wait_timer0.wait_timer = cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_digital_power_supply_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->power.wait_timer0.wait_timer;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_digital_power_up_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
hw->power.wait_timer0.powerup_timer = cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_digital_power_up_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->power.wait_timer0.powerup_timer;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_get_sysclk_sleep_select_state(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->clk_state0.sysclk_slp_sel;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,70 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The HAL layer for PMU (ESP32-C6 specific part)
|
||||
|
||||
#include "soc/soc.h"
|
||||
#include "esp_attr.h"
|
||||
#include "hal/pmu_hal.h"
|
||||
#include "hal/pmu_types.h"
|
||||
|
||||
void pmu_hal_hp_set_digital_power_up_wait_cycle(pmu_hal_context_t *hal, uint32_t power_supply_wait_cycle, uint32_t power_up_wait_cycle)
|
||||
{
|
||||
pmu_ll_hp_set_digital_power_supply_wait_cycle(hal->dev, power_supply_wait_cycle);
|
||||
pmu_ll_hp_set_digital_power_up_wait_cycle(hal->dev, power_up_wait_cycle);
|
||||
}
|
||||
|
||||
uint32_t pmu_hal_hp_get_digital_power_up_wait_cycle(pmu_hal_context_t *hal)
|
||||
{
|
||||
uint32_t power_supply_wait_cycle = pmu_ll_hp_get_digital_power_supply_wait_cycle(hal->dev);
|
||||
uint32_t power_up_wait_cycle = pmu_ll_hp_get_digital_power_up_wait_cycle(hal->dev);
|
||||
return power_supply_wait_cycle + power_up_wait_cycle;
|
||||
}
|
||||
|
||||
void pmu_hal_lp_set_digital_power_up_wait_cycle(pmu_hal_context_t *hal, uint32_t power_supply_wait_cycle, uint32_t power_up_wait_cycle)
|
||||
{
|
||||
pmu_ll_lp_set_digital_power_supply_wait_cycle(hal->dev, power_supply_wait_cycle);
|
||||
pmu_ll_lp_set_digital_power_up_wait_cycle(hal->dev, power_up_wait_cycle);
|
||||
}
|
||||
|
||||
uint32_t pmu_hal_lp_get_digital_power_up_wait_cycle(pmu_hal_context_t *hal)
|
||||
{
|
||||
uint32_t power_supply_wait_cycle = pmu_ll_lp_get_digital_power_supply_wait_cycle(hal->dev);
|
||||
uint32_t power_up_wait_cycle = pmu_ll_lp_get_digital_power_up_wait_cycle(hal->dev);
|
||||
return power_supply_wait_cycle + power_up_wait_cycle;
|
||||
}
|
||||
|
||||
void pmu_hal_hp_set_sleep_active_backup_enable(pmu_hal_context_t *hal)
|
||||
{
|
||||
pmu_ll_hp_set_active_to_sleep_backup_enable(hal->dev);
|
||||
pmu_ll_hp_set_sleep_to_active_backup_enable(hal->dev);
|
||||
}
|
||||
|
||||
void pmu_hal_hp_set_sleep_active_backup_disable(pmu_hal_context_t *hal)
|
||||
{
|
||||
pmu_ll_hp_set_sleep_to_active_backup_disable(hal->dev);
|
||||
pmu_ll_hp_set_active_to_sleep_backup_disable(hal->dev);
|
||||
}
|
||||
|
||||
void pmu_hal_hp_set_sleep_modem_backup_enable(pmu_hal_context_t *hal)
|
||||
{
|
||||
pmu_ll_hp_set_sleep_to_modem_backup_enable(hal->dev);
|
||||
}
|
||||
|
||||
void pmu_hal_hp_set_sleep_modem_backup_disable(pmu_hal_context_t *hal)
|
||||
{
|
||||
pmu_ll_hp_set_sleep_to_modem_backup_disable(hal->dev);
|
||||
}
|
||||
|
||||
void pmu_hal_hp_set_modem_active_backup_enable(pmu_hal_context_t *hal)
|
||||
{
|
||||
pmu_ll_hp_set_modem_to_active_backup_enable(hal->dev);
|
||||
}
|
||||
|
||||
void pmu_hal_hp_set_modem_active_backup_disable(pmu_hal_context_t *hal)
|
||||
{
|
||||
pmu_ll_hp_set_modem_to_active_backup_disable(hal->dev);
|
||||
}
|
||||
@@ -0,0 +1,49 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The HAL layer for PMU
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "soc/soc_caps.h"
|
||||
#include "hal/pmu_ll.h"
|
||||
#include "hal/pmu_types.h"
|
||||
|
||||
typedef struct {
|
||||
pmu_dev_t *dev;
|
||||
} pmu_hal_context_t;
|
||||
|
||||
void pmu_hal_hp_set_digital_power_up_wait_cycle(pmu_hal_context_t *hal, uint32_t power_supply_wait_cycle, uint32_t power_up_wait_cycle);
|
||||
|
||||
uint32_t pmu_hal_hp_get_digital_power_up_wait_cycle(pmu_hal_context_t *hal);
|
||||
|
||||
void pmu_hal_lp_set_digital_power_up_wait_cycle(pmu_hal_context_t *hal, uint32_t power_supply_wait_cycle, uint32_t power_up_wait_cycle);
|
||||
|
||||
uint32_t pmu_hal_lp_get_digital_power_up_wait_cycle(pmu_hal_context_t *hal);
|
||||
|
||||
void pmu_hal_hp_set_control_ready_wait_cycle(pmu_hal_context_t *hal, uint32_t isolate_wait_cycle, uint32_t reset_wait_cycle);
|
||||
|
||||
void pmu_hal_lp_set_control_ready_wait_cycle(pmu_hal_context_t *hal, uint32_t isolate_wait_cycle, uint32_t reset_wait_cycle);
|
||||
|
||||
void pmu_hal_hp_set_sleep_active_backup_enable(pmu_hal_context_t *hal);
|
||||
|
||||
void pmu_hal_hp_set_sleep_active_backup_disable(pmu_hal_context_t *hal);
|
||||
|
||||
void pmu_hal_hp_set_sleep_modem_backup_enable(pmu_hal_context_t *hal);
|
||||
|
||||
void pmu_hal_hp_set_sleep_modem_backup_disable(pmu_hal_context_t *hal);
|
||||
|
||||
void pmu_hal_hp_set_modem_active_backup_enable(pmu_hal_context_t *hal);
|
||||
|
||||
void pmu_hal_hp_set_modem_active_backup_disable(pmu_hal_context_t *hal);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,707 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The LL layer for ESP32-C61 PMU register operations
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <stdbool.h>
|
||||
#include "soc/soc.h"
|
||||
#include "esp_attr.h"
|
||||
#include "hal/assert.h"
|
||||
#include "soc/pmu_struct.h"
|
||||
#include "hal/pmu_types.h"
|
||||
#include "hal/misc.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Set the power domain that needs to be powered down in the digital power
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param mode The pmu mode
|
||||
* @param flag Digital power domain flag
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_dig_power(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t flag)
|
||||
{
|
||||
hw->hp_sys[mode].dig_power.val = flag;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_func(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t icg_func)
|
||||
{
|
||||
hw->hp_sys[mode].icg_func = icg_func;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_apb(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t bitmap)
|
||||
{
|
||||
hw->hp_sys[mode].icg_apb = bitmap;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_modem(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t code)
|
||||
{
|
||||
hw->hp_sys[mode].icg_modem.code = code;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_uart_wakeup_enable(pmu_dev_t *hw, pmu_hp_mode_t mode, bool wakeup_en)
|
||||
{
|
||||
hw->hp_sys[mode].syscntl.uart_wakeup_en = wakeup_en;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_hold_all_lp_pad(pmu_dev_t *hw, pmu_hp_mode_t mode, bool hold_all)
|
||||
{
|
||||
hw->hp_sys[mode].syscntl.lp_pad_hold_all = hold_all;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_hold_all_hp_pad(pmu_dev_t *hw, pmu_hp_mode_t mode, bool hold_all)
|
||||
{
|
||||
hw->hp_sys[mode].syscntl.hp_pad_hold_all = hold_all;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_dig_pad_slp_sel(pmu_dev_t *hw, pmu_hp_mode_t mode, bool slp_sel)
|
||||
{
|
||||
hw->hp_sys[mode].syscntl.dig_pad_slp_sel = slp_sel;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_pause_watchdog(pmu_dev_t *hw, pmu_hp_mode_t mode, bool pause_wdt)
|
||||
{
|
||||
hw->hp_sys[mode].syscntl.dig_pause_wdt = pause_wdt;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_cpu_stall(pmu_dev_t *hw, pmu_hp_mode_t mode, bool cpu_stall)
|
||||
{
|
||||
hw->hp_sys[mode].syscntl.dig_cpu_stall = cpu_stall;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the power domain that needs to be powered down in the clock power
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param mode The pmu mode
|
||||
* @param flag Clock power domain flag
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_clk_power(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t xpd_flag)
|
||||
{
|
||||
hw->hp_sys[mode].clk_power.val = xpd_flag;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_xtal_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool xpd_xtal)
|
||||
{
|
||||
hw->hp_sys[mode].xtal.xpd_xtal = xpd_xtal;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_bias_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool xpd_bias)
|
||||
{
|
||||
hw->hp_sys[mode].bias.xpd_bias = xpd_bias;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_dbg_atten(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t value)
|
||||
{
|
||||
hw->hp_sys[mode].bias.dbg_atten = value;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_current_power_off(pmu_dev_t *hw, pmu_hp_mode_t mode, bool off)
|
||||
{
|
||||
hw->hp_sys[mode].bias.pd_cur = off;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_bias_sleep_enable(pmu_dev_t *hw, pmu_hp_mode_t mode, bool en)
|
||||
{
|
||||
hw->hp_sys[mode].bias.bias_sleep = en;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_retention_param(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t param)
|
||||
{
|
||||
hw->hp_sys[mode].backup.val = param;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_to_active_backup_enable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_sys[PMU_MODE_HP_ACTIVE].backup.hp_sleep2active_backup_en = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_to_active_backup_disable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_sys[PMU_MODE_HP_ACTIVE].backup.hp_sleep2active_backup_en = 0;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_modem_to_active_backup_enable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_sys[PMU_MODE_HP_ACTIVE].backup.hp_modem2active_backup_en = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_modem_to_active_backup_disable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_sys[PMU_MODE_HP_ACTIVE].backup.hp_modem2active_backup_en = 0;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_to_modem_backup_enable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_sys[PMU_MODE_HP_MODEM].backup.hp_sleep2modem_backup_en = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_to_modem_backup_disable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_sys[PMU_MODE_HP_MODEM].backup.hp_sleep2modem_backup_en = 0;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_active_to_sleep_backup_enable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_sys[PMU_MODE_HP_SLEEP].backup.hp_active2sleep_backup_en = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_active_to_sleep_backup_disable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_sys[PMU_MODE_HP_SLEEP].backup.hp_active2sleep_backup_en = 0;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_modem_to_sleep_backup_enable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_sys[PMU_MODE_HP_SLEEP].backup.hp_modem2sleep_backup_en = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_modem_to_sleep_backup_disable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_sys[PMU_MODE_HP_SLEEP].backup.hp_modem2sleep_backup_en = 0;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_backup_icg_func(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t icg_func)
|
||||
{
|
||||
hw->hp_sys[mode].backup_clk = icg_func;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_sysclk_nodiv(pmu_dev_t *hw, pmu_hp_mode_t mode, bool sysclk_nodiv)
|
||||
{
|
||||
hw->hp_sys[mode].sysclk.dig_sysclk_nodiv = sysclk_nodiv;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_sysclk_enable(pmu_dev_t *hw, pmu_hp_mode_t mode, bool icg_sysclk_en)
|
||||
{
|
||||
hw->hp_sys[mode].sysclk.icg_sysclk_en = icg_sysclk_en;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_sysclk_slp_sel(pmu_dev_t *hw, pmu_hp_mode_t mode, bool slp_sel)
|
||||
{
|
||||
hw->hp_sys[mode].sysclk.sysclk_slp_sel = slp_sel;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_sysclk_slp_sel(pmu_dev_t *hw, pmu_hp_mode_t mode, bool slp_sel)
|
||||
{
|
||||
hw->hp_sys[mode].sysclk.icg_slp_sel = slp_sel;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_dig_sysclk(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t sysclk_sel)
|
||||
{
|
||||
hw->hp_sys[mode].sysclk.dig_sysclk_sel = sysclk_sel;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_sleep_logic_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool slp_xpd)
|
||||
{
|
||||
hw->hp_sys[mode].regulator0.slp_logic_xpd = slp_xpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_sleep_memory_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool slp_xpd)
|
||||
{
|
||||
hw->hp_sys[mode].regulator0.slp_mem_xpd = slp_xpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool xpd)
|
||||
{
|
||||
hw->hp_sys[mode].regulator0.xpd = xpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_sleep_logic_dbias(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t slp_dbias)
|
||||
{
|
||||
hw->hp_sys[mode].regulator0.slp_logic_dbias = slp_dbias;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_sleep_memory_dbias(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t slp_dbias)
|
||||
{
|
||||
hw->hp_sys[mode].regulator0.slp_mem_dbias = slp_dbias;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_dbias(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t dbias)
|
||||
{
|
||||
hw->hp_sys[mode].regulator0.dbias = dbias;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_driver_bar(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t drv_b)
|
||||
{
|
||||
hw->hp_sys[mode].regulator1.drv_b = drv_b;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_regulator_slp_xpd(pmu_dev_t *hw, pmu_lp_mode_t mode, bool slp_xpd)
|
||||
{
|
||||
hw->lp_sys[mode].regulator0.slp_xpd = slp_xpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_regulator_xpd(pmu_dev_t *hw, pmu_lp_mode_t mode, bool xpd)
|
||||
{
|
||||
hw->lp_sys[mode].regulator0.xpd = xpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_regulator_sleep_dbias(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t slp_dbias)
|
||||
{
|
||||
hw->lp_sys[mode].regulator0.slp_dbias = slp_dbias;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_regulator_dbias(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t dbias)
|
||||
{
|
||||
hw->lp_sys[mode].regulator0.dbias = dbias;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_regulator_driver_bar(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t drv_b)
|
||||
{
|
||||
hw->lp_sys[mode].regulator1.drv_b = drv_b;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_xtal_xpd(pmu_dev_t *hw, pmu_lp_mode_t mode, bool xpd_xtal)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
|
||||
hw->lp_sys[mode].xtal.xpd_xtal = xpd_xtal;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_dig_power(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t flag)
|
||||
{
|
||||
hw->lp_sys[mode].dig_power.val = flag;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_clk_power(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t xpd_flag)
|
||||
{
|
||||
hw->lp_sys[mode].clk_power.val = xpd_flag;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_clk_power(pmu_dev_t *hw, pmu_lp_mode_t mode)
|
||||
{
|
||||
return hw->lp_sys[mode].clk_power.val;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_bias_xpd(pmu_dev_t *hw, pmu_lp_mode_t mode, bool xpd_bias)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
|
||||
hw->lp_sys[mode].bias.xpd_bias = xpd_bias;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_dbg_atten(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t value)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
|
||||
hw->lp_sys[mode].bias.dbg_atten = value;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_current_power_off(pmu_dev_t *hw, pmu_lp_mode_t mode, bool off)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
|
||||
hw->lp_sys[mode].bias.pd_cur = off;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_bias_sleep_enable(pmu_dev_t *hw, pmu_lp_mode_t mode, bool en)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
|
||||
hw->lp_sys[mode].bias.bias_sleep = en;
|
||||
}
|
||||
|
||||
/****/
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_set_clk_power(pmu_dev_t *hw, uint32_t flag)
|
||||
{
|
||||
hw->imm.clk_power.val = flag;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_set_icg_slp_sel(pmu_dev_t *hw, bool slp_sel)
|
||||
{
|
||||
if (slp_sel) {
|
||||
hw->imm.sleep_sysclk.tie_high_icg_slp_sel = 1;
|
||||
} else {
|
||||
hw->imm.sleep_sysclk.tie_low_icg_slp_sel = 1;
|
||||
}
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_update_dig_sysclk_sel(pmu_dev_t *hw, bool update)
|
||||
{
|
||||
hw->imm.sleep_sysclk.update_dig_sysclk_sel = update;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_update_dig_icg_switch(pmu_dev_t *hw, bool update)
|
||||
{
|
||||
hw->imm.sleep_sysclk.update_dig_icg_switch = update;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_update_dig_icg_func(pmu_dev_t *hw, bool icg_func_update)
|
||||
{
|
||||
hw->imm.hp_func_icg.update_dig_icg_func_en = icg_func_update;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_update_dig_icg_apb(pmu_dev_t *hw, bool icg_apb_update)
|
||||
{
|
||||
hw->imm.hp_apb_icg.update_dig_icg_apb_en = icg_apb_update;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_update_dig_icg_modem_code(pmu_dev_t *hw, bool icg_modem_update)
|
||||
{
|
||||
hw->imm.modem_icg.update_dig_icg_modem_en = icg_modem_update;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_set_lp_rootclk_sel(pmu_dev_t *hw, bool rootclk_sel)
|
||||
{
|
||||
if (rootclk_sel) {
|
||||
hw->imm.lp_icg.tie_high_lp_rootclk_sel = 1;
|
||||
} else {
|
||||
hw->imm.lp_icg.tie_low_lp_rootclk_sel = 1;
|
||||
}
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_set_hp_pad_hold_all(pmu_dev_t *hw, bool hold_all)
|
||||
{
|
||||
if (hold_all) {
|
||||
hw->imm.pad_hold_all.tie_high_hp_pad_hold_all = 1;
|
||||
} else {
|
||||
hw->imm.pad_hold_all.tie_low_hp_pad_hold_all = 1;
|
||||
}
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_set_lp_pad_hold_all(pmu_dev_t *hw, bool hold_all)
|
||||
{
|
||||
if (hold_all) {
|
||||
hw->imm.pad_hold_all.tie_high_lp_pad_hold_all = 1;
|
||||
} else {
|
||||
hw->imm.pad_hold_all.tie_low_lp_pad_hold_all = 1;
|
||||
}
|
||||
}
|
||||
|
||||
/*** */
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_reset(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool rst)
|
||||
{
|
||||
hw->power.hp_pd[domain].force_reset = rst;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_isolate(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool iso)
|
||||
{
|
||||
hw->power.hp_pd[domain].force_iso = iso;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_power_up(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool fpu)
|
||||
{
|
||||
hw->power.hp_pd[domain].force_pu = fpu;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_no_reset(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool no_rst)
|
||||
{
|
||||
hw->power.hp_pd[domain].force_no_reset = no_rst;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_no_isolate(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool no_iso)
|
||||
{
|
||||
hw->power.hp_pd[domain].force_no_iso = no_iso;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_power_down(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool fpd)
|
||||
{
|
||||
hw->power.hp_pd[domain].force_pd = fpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_reset(pmu_dev_t *hw, bool rst)
|
||||
{
|
||||
hw->power.lp_peri.force_reset = rst;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_isolate(pmu_dev_t *hw, bool iso)
|
||||
{
|
||||
hw->power.lp_peri.force_iso = iso;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_power_up(pmu_dev_t *hw, bool fpu)
|
||||
{
|
||||
hw->power.lp_peri.force_pu = fpu;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_no_reset(pmu_dev_t *hw, bool no_rst)
|
||||
{
|
||||
hw->power.lp_peri.force_no_reset = no_rst;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_no_isolate(pmu_dev_t *hw, bool no_iso)
|
||||
{
|
||||
hw->power.lp_peri.force_no_iso = no_iso;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_power_down(pmu_dev_t *hw, bool fpd)
|
||||
{
|
||||
hw->power.lp_peri.force_pd = fpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_memory_isolate(pmu_dev_t *hw, uint32_t iso)
|
||||
{
|
||||
hw->power.mem_cntl.force_hp_mem_iso = iso;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_memory_power_down(pmu_dev_t *hw, uint32_t fpd)
|
||||
{
|
||||
hw->power.mem_cntl.force_hp_mem_pd = fpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_memory_no_isolate(pmu_dev_t *hw, uint32_t no_iso)
|
||||
{
|
||||
hw->power.mem_cntl.force_hp_mem_no_iso = no_iso;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_memory_power_up(pmu_dev_t *hw, uint32_t fpu)
|
||||
{
|
||||
hw->power.mem_cntl.force_hp_mem_pu = fpu;
|
||||
}
|
||||
|
||||
/*** */
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_enable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->wakeup.cntl0.sleep_req = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_reject_enable(pmu_dev_t *hw, uint32_t reject)
|
||||
{
|
||||
hw->wakeup.cntl1.sleep_reject_ena = reject;
|
||||
hw->wakeup.cntl1.slp_reject_en = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_reject_disable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->wakeup.cntl1.slp_reject_en = 0;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_wakeup_enable(pmu_dev_t *hw, uint32_t wakeup)
|
||||
{
|
||||
hw->wakeup.cntl2 = wakeup;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_protect_mode(pmu_dev_t *hw, int mode)
|
||||
{
|
||||
hw->wakeup.cntl3.sleep_prt_sel = mode;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_min_sleep_cycle(pmu_dev_t *hw, uint32_t slow_clk_cycle)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wakeup.cntl3, hp_min_slp_val, slow_clk_cycle);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_clear_reject_cause(pmu_dev_t *hw)
|
||||
{
|
||||
hw->wakeup.cntl4.slp_reject_cause_clr = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR bool pmu_ll_hp_is_sleep_wakeup(pmu_dev_t *hw)
|
||||
{
|
||||
return (hw->hp_ext.int_raw.wakeup == 1);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR bool pmu_ll_hp_is_sleep_reject(pmu_dev_t *hw)
|
||||
{
|
||||
return (hw->hp_ext.int_raw.reject == 1);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_clear_sw_intr_status(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_ext.int_clr.sw = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_clear_wakeup_intr_status(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_ext.int_clr.wakeup = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_clear_reject_intr_status(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_ext.int_clr.reject = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_wakeup_cause(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->wakeup.status0;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_reject_cause(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->wakeup.status1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_interrupt_raw(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->lp_ext.int_raw.val;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_clear_intsts_mask(pmu_dev_t *hw, uint32_t mask)
|
||||
{
|
||||
hw->lp_ext.int_clr.val = mask;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_min_sleep_cycle(pmu_dev_t *hw, uint32_t slow_clk_cycle)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wakeup.cntl3, lp_min_slp_val, slow_clk_cycle);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_modify_icg_cntl_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hp_ext.clk_cntl, modify_icg_cntl_wait, cycle);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_modify_icg_cntl_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return HAL_FORCE_READ_U32_REG_FIELD(hw->hp_ext.clk_cntl, modify_icg_cntl_wait);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_switch_icg_cntl_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hp_ext.clk_cntl, switch_icg_cntl_wait, cycle);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_switch_icg_cntl_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return HAL_FORCE_READ_U32_REG_FIELD(hw->hp_ext.clk_cntl, switch_icg_cntl_wait);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_digital_power_down_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
hw->power.wait_timer0.powerdown_timer = cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_digital_power_down_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->power.wait_timer0.powerdown_timer;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_digital_power_down_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
hw->power.wait_timer1.powerdown_timer = cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_digital_power_down_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->power.wait_timer1.powerdown_timer;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_isolate_wait_cycle(pmu_dev_t *hw, uint32_t isolate_wait_cycle)
|
||||
{
|
||||
hw->power.wait_timer2.lp_iso_wait_timer = isolate_wait_cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_reset_wait_cycle(pmu_dev_t *hw, uint32_t reset_wait_cycle)
|
||||
{
|
||||
hw->power.wait_timer2.lp_rst_wait_timer = reset_wait_cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_isolate_wait_cycle(pmu_dev_t *hw, uint32_t isolate_wait_cycle)
|
||||
{
|
||||
hw->power.wait_timer2.hp_iso_wait_timer = isolate_wait_cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_reset_wait_cycle(pmu_dev_t *hw, uint32_t reset_wait_cycle)
|
||||
{
|
||||
hw->power.wait_timer2.hp_rst_wait_timer = reset_wait_cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_analog_wait_target_cycle(pmu_dev_t *hw, uint32_t slow_clk_cycle)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wakeup.cntl5, lp_ana_wait_target, slow_clk_cycle);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_analog_wait_target_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return HAL_FORCE_READ_U32_REG_FIELD(hw->wakeup.cntl5, lp_ana_wait_target);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_set_modem_wait_target_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
hw->wakeup.cntl5.modem_wait_target = cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_get_modem_wait_target_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->wakeup.cntl5.modem_wait_target;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_set_xtal_stable_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->power.clk_wait, wait_xtal_stable, cycle);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_get_xtal_stable_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return HAL_FORCE_READ_U32_REG_FIELD(hw->power.clk_wait, wait_xtal_stable);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_set_pll_stable_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->power.clk_wait, wait_pll_stable, cycle);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_get_pll_stable_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return HAL_FORCE_READ_U32_REG_FIELD(hw->power.clk_wait, wait_pll_stable);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_digital_power_supply_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
hw->power.wait_timer1.wait_timer = cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_digital_power_supply_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->power.wait_timer1.wait_timer;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_digital_power_up_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
hw->power.wait_timer1.powerup_timer = cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_digital_power_up_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->power.wait_timer1.powerup_timer;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_analog_wait_target_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wakeup.cntl7, ana_wait_target, cycle);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_analog_wait_target_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return HAL_FORCE_READ_U32_REG_FIELD(hw->wakeup.cntl7, ana_wait_target);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_digital_power_supply_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
if (cycle > 0x1FF) {
|
||||
cycle = 0x1FF;
|
||||
}
|
||||
hw->power.wait_timer0.wait_timer = cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_digital_power_supply_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->power.wait_timer0.wait_timer;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_digital_power_up_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
hw->power.wait_timer0.powerup_timer = cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_digital_power_up_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->power.wait_timer0.powerup_timer;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_get_sysclk_sleep_select_state(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->clk_state0.sysclk_slp_sel;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,82 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The HAL layer for PMU (ESP32-C61 specific part)
|
||||
|
||||
#include "soc/soc.h"
|
||||
#include "esp_attr.h"
|
||||
#include "hal/pmu_hal.h"
|
||||
#include "hal/pmu_types.h"
|
||||
|
||||
void pmu_hal_hp_set_digital_power_up_wait_cycle(pmu_hal_context_t *hal, uint32_t power_supply_wait_cycle, uint32_t power_up_wait_cycle)
|
||||
{
|
||||
pmu_ll_hp_set_digital_power_supply_wait_cycle(hal->dev, power_supply_wait_cycle);
|
||||
pmu_ll_hp_set_digital_power_up_wait_cycle(hal->dev, power_up_wait_cycle);
|
||||
}
|
||||
|
||||
uint32_t pmu_hal_hp_get_digital_power_up_wait_cycle(pmu_hal_context_t *hal)
|
||||
{
|
||||
uint32_t power_supply_wait_cycle = pmu_ll_hp_get_digital_power_supply_wait_cycle(hal->dev);
|
||||
uint32_t power_up_wait_cycle = pmu_ll_hp_get_digital_power_up_wait_cycle(hal->dev);
|
||||
return power_supply_wait_cycle + power_up_wait_cycle;
|
||||
}
|
||||
|
||||
void pmu_hal_lp_set_digital_power_up_wait_cycle(pmu_hal_context_t *hal, uint32_t power_supply_wait_cycle, uint32_t power_up_wait_cycle)
|
||||
{
|
||||
pmu_ll_lp_set_digital_power_supply_wait_cycle(hal->dev, power_supply_wait_cycle);
|
||||
pmu_ll_lp_set_digital_power_up_wait_cycle(hal->dev, power_up_wait_cycle);
|
||||
}
|
||||
|
||||
uint32_t pmu_hal_lp_get_digital_power_up_wait_cycle(pmu_hal_context_t *hal)
|
||||
{
|
||||
uint32_t power_supply_wait_cycle = pmu_ll_lp_get_digital_power_supply_wait_cycle(hal->dev);
|
||||
uint32_t power_up_wait_cycle = pmu_ll_lp_get_digital_power_up_wait_cycle(hal->dev);
|
||||
return power_supply_wait_cycle + power_up_wait_cycle;
|
||||
}
|
||||
|
||||
void pmu_hal_hp_set_control_ready_wait_cycle(pmu_hal_context_t *hal, uint32_t isolate_wait_cycle, uint32_t reset_wait_cycle)
|
||||
{
|
||||
pmu_ll_hp_set_isolate_wait_cycle(hal->dev, isolate_wait_cycle);
|
||||
pmu_ll_hp_set_reset_wait_cycle(hal->dev, reset_wait_cycle);
|
||||
}
|
||||
|
||||
void pmu_hal_lp_set_control_ready_wait_cycle(pmu_hal_context_t *hal, uint32_t isolate_wait_cycle, uint32_t reset_wait_cycle)
|
||||
{
|
||||
pmu_ll_lp_set_isolate_wait_cycle(hal->dev, isolate_wait_cycle);
|
||||
pmu_ll_lp_set_reset_wait_cycle(hal->dev, reset_wait_cycle);
|
||||
}
|
||||
|
||||
void pmu_hal_hp_set_sleep_active_backup_enable(pmu_hal_context_t *hal)
|
||||
{
|
||||
pmu_ll_hp_set_active_to_sleep_backup_enable(hal->dev);
|
||||
pmu_ll_hp_set_sleep_to_active_backup_enable(hal->dev);
|
||||
}
|
||||
|
||||
void pmu_hal_hp_set_sleep_active_backup_disable(pmu_hal_context_t *hal)
|
||||
{
|
||||
pmu_ll_hp_set_sleep_to_active_backup_disable(hal->dev);
|
||||
pmu_ll_hp_set_active_to_sleep_backup_disable(hal->dev);
|
||||
}
|
||||
|
||||
void pmu_hal_hp_set_sleep_modem_backup_enable(pmu_hal_context_t *hal)
|
||||
{
|
||||
pmu_ll_hp_set_sleep_to_modem_backup_enable(hal->dev);
|
||||
}
|
||||
|
||||
void pmu_hal_hp_set_sleep_modem_backup_disable(pmu_hal_context_t *hal)
|
||||
{
|
||||
pmu_ll_hp_set_sleep_to_modem_backup_disable(hal->dev);
|
||||
}
|
||||
|
||||
void pmu_hal_hp_set_modem_active_backup_enable(pmu_hal_context_t *hal)
|
||||
{
|
||||
pmu_ll_hp_set_modem_to_active_backup_enable(hal->dev);
|
||||
}
|
||||
|
||||
void pmu_hal_hp_set_modem_active_backup_disable(pmu_hal_context_t *hal)
|
||||
{
|
||||
pmu_ll_hp_set_modem_to_active_backup_disable(hal->dev);
|
||||
}
|
||||
@@ -0,0 +1,37 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The HAL layer for PMU
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "soc/soc_caps.h"
|
||||
#include "hal/pmu_ll.h"
|
||||
#include "hal/pmu_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef struct {
|
||||
pmu_dev_t *dev;
|
||||
} pmu_hal_context_t;
|
||||
|
||||
void pmu_hal_hp_set_digital_power_up_wait_cycle(pmu_hal_context_t *hal, uint32_t power_supply_wait_cycle, uint32_t power_up_wait_cycle);
|
||||
|
||||
uint32_t pmu_hal_hp_get_digital_power_up_wait_cycle(pmu_hal_context_t *hal);
|
||||
|
||||
void pmu_hal_lp_set_digital_power_up_wait_cycle(pmu_hal_context_t *hal, uint32_t power_supply_wait_cycle, uint32_t power_up_wait_cycle);
|
||||
|
||||
uint32_t pmu_hal_lp_get_digital_power_up_wait_cycle(pmu_hal_context_t *hal);
|
||||
|
||||
void pmu_hal_hp_set_sleep_active_backup_enable(pmu_hal_context_t *hal);
|
||||
|
||||
void pmu_hal_hp_set_sleep_active_backup_disable(pmu_hal_context_t *hal);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,615 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The LL layer for ESP32-H2 PMU register operations
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <stdbool.h>
|
||||
#include "soc/soc.h"
|
||||
#include "esp_attr.h"
|
||||
#include "hal/assert.h"
|
||||
#include "soc/pmu_struct.h"
|
||||
#include "hal/pmu_types.h"
|
||||
#include "hal/misc.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Set the power domain that needs to be powered down in the digital power
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param mode The pmu mode
|
||||
* @param flag Digital power domain flag
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_dig_power(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t flag)
|
||||
{
|
||||
hw->hp_sys[mode].dig_power.val = flag;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_func(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t icg_func)
|
||||
{
|
||||
hw->hp_sys[mode].icg_func = icg_func;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_apb(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t bitmap)
|
||||
{
|
||||
hw->hp_sys[mode].icg_apb = bitmap;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_modem(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t code)
|
||||
{
|
||||
hw->hp_sys[mode].icg_modem.code = code;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_uart_wakeup_enable(pmu_dev_t *hw, pmu_hp_mode_t mode, bool wakeup_en)
|
||||
{
|
||||
hw->hp_sys[mode].syscntl.uart_wakeup_en = wakeup_en;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_hold_all_lp_pad(pmu_dev_t *hw, pmu_hp_mode_t mode, bool hold_all)
|
||||
{
|
||||
hw->hp_sys[mode].syscntl.lp_pad_hold_all = hold_all;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_hold_all_hp_pad(pmu_dev_t *hw, pmu_hp_mode_t mode, bool hold_all)
|
||||
{
|
||||
hw->hp_sys[mode].syscntl.hp_pad_hold_all = hold_all;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_dig_pad_slp_sel(pmu_dev_t *hw, pmu_hp_mode_t mode, bool slp_sel)
|
||||
{
|
||||
hw->hp_sys[mode].syscntl.dig_pad_slp_sel = slp_sel;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_pause_watchdog(pmu_dev_t *hw, pmu_hp_mode_t mode, bool pause_wdt)
|
||||
{
|
||||
hw->hp_sys[mode].syscntl.dig_pause_wdt = pause_wdt;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_cpu_stall(pmu_dev_t *hw, pmu_hp_mode_t mode, bool cpu_stall)
|
||||
{
|
||||
hw->hp_sys[mode].syscntl.dig_cpu_stall = cpu_stall;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the power domain that needs to be powered down in the clock power
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param mode The pmu mode
|
||||
* @param flag Clock power domain flag
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_clk_power(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t xpd_flag)
|
||||
{
|
||||
hw->hp_sys[mode].clk_power.val = xpd_flag;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_bias_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool xpd_bias)
|
||||
{
|
||||
hw->hp_sys[mode].bias.xpd_bias = xpd_bias;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_trx_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool xpd_trx)
|
||||
{
|
||||
hw->hp_sys[mode].bias.xpd_trx = xpd_trx;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_xtal_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool xpd_xtal)
|
||||
{
|
||||
hw->hp_sys[mode].xtal.xpd_xtal = xpd_xtal;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_current_power_off(pmu_dev_t *hw, pmu_hp_mode_t mode, bool off)
|
||||
{
|
||||
hw->hp_sys[mode].bias.pd_cur = off;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_bias_sleep_enable(pmu_dev_t *hw, pmu_hp_mode_t mode, bool en)
|
||||
{
|
||||
hw->hp_sys[mode].bias.bias_sleep = en;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_retention_param(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t param)
|
||||
{
|
||||
hw->hp_sys[mode].backup.val = param;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_to_active_backup_enable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_sys[PMU_MODE_HP_ACTIVE].backup.hp_sleep2active_backup_en = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_to_active_backup_disable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_sys[PMU_MODE_HP_ACTIVE].backup.hp_sleep2active_backup_en = 0;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_active_to_sleep_backup_enable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_sys[PMU_MODE_HP_SLEEP].backup.hp_active2sleep_backup_en = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_active_to_sleep_backup_disable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_sys[PMU_MODE_HP_SLEEP].backup.hp_active2sleep_backup_en = 0;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_backup_icg_func(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t icg_func)
|
||||
{
|
||||
hw->hp_sys[mode].backup_clk = icg_func;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_sysclk_nodiv(pmu_dev_t *hw, pmu_hp_mode_t mode, bool sysclk_nodiv)
|
||||
{
|
||||
hw->hp_sys[mode].sysclk.dig_sysclk_nodiv = sysclk_nodiv;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_sysclk_enable(pmu_dev_t *hw, pmu_hp_mode_t mode, bool icg_sysclk_en)
|
||||
{
|
||||
hw->hp_sys[mode].sysclk.icg_sysclk_en = icg_sysclk_en;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_sysclk_slp_sel(pmu_dev_t *hw, pmu_hp_mode_t mode, bool slp_sel)
|
||||
{
|
||||
hw->hp_sys[mode].sysclk.sysclk_slp_sel = slp_sel;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_sysclk_slp_sel(pmu_dev_t *hw, pmu_hp_mode_t mode, bool slp_sel)
|
||||
{
|
||||
hw->hp_sys[mode].sysclk.icg_slp_sel = slp_sel;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_dig_sysclk(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t sysclk_sel)
|
||||
{
|
||||
hw->hp_sys[mode].sysclk.dig_sysclk_sel = sysclk_sel;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_sleep_logic_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool slp_xpd)
|
||||
{
|
||||
hw->hp_sys[mode].regulator0.slp_logic_xpd = slp_xpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_sleep_memory_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool slp_xpd)
|
||||
{
|
||||
hw->hp_sys[mode].regulator0.slp_mem_xpd = slp_xpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool xpd)
|
||||
{
|
||||
hw->hp_sys[mode].regulator0.xpd = xpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_sleep_logic_dbias(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t slp_dbias)
|
||||
{
|
||||
hw->hp_sys[mode].regulator0.slp_logic_dbias = slp_dbias;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_sleep_memory_dbias(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t slp_dbias)
|
||||
{
|
||||
hw->hp_sys[mode].regulator0.slp_mem_dbias = slp_dbias;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_dbias(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t dbias)
|
||||
{
|
||||
hw->hp_sys[mode].regulator0.dbias = dbias;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_driver_bar(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t drv_b)
|
||||
{
|
||||
hw->hp_sys[mode].regulator1.drv_b = drv_b;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_regulator_slp_xpd(pmu_dev_t *hw, pmu_lp_mode_t mode, bool slp_xpd)
|
||||
{
|
||||
hw->lp_sys[mode].regulator0.slp_xpd = slp_xpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_regulator_xpd(pmu_dev_t *hw, pmu_lp_mode_t mode, bool xpd)
|
||||
{
|
||||
hw->lp_sys[mode].regulator0.xpd = xpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_regulator_sleep_dbias(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t slp_dbias)
|
||||
{
|
||||
hw->lp_sys[mode].regulator0.slp_dbias = slp_dbias;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_regulator_dbias(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t dbias)
|
||||
{
|
||||
hw->lp_sys[mode].regulator0.dbias = dbias;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_regulator_driver_bar(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t drv_b)
|
||||
{
|
||||
hw->lp_sys[mode].regulator1.drv_b = drv_b;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_xtal_xpd(pmu_dev_t *hw, pmu_lp_mode_t mode, bool slp_xpd)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
|
||||
hw->lp_sys[mode].xtal.xpd_xtal = slp_xpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_dig_power(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t flag)
|
||||
{
|
||||
hw->lp_sys[mode].dig_power.val = flag;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_clk_power(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t xpd_flag)
|
||||
{
|
||||
hw->lp_sys[mode].clk_power.val = xpd_flag;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_clk_power(pmu_dev_t *hw, pmu_lp_mode_t mode)
|
||||
{
|
||||
return hw->lp_sys[mode].clk_power.val;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_bias_xpd(pmu_dev_t *hw, pmu_lp_mode_t mode, bool xpd_bias)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
|
||||
hw->lp_sys[mode].bias.xpd_bias = xpd_bias;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_current_power_off(pmu_dev_t *hw, pmu_lp_mode_t mode, bool off)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
|
||||
hw->lp_sys[mode].bias.pd_cur = off;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_bias_sleep_enable(pmu_dev_t *hw, pmu_lp_mode_t mode, bool en)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
|
||||
hw->lp_sys[mode].bias.bias_sleep = en;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_set_clk_power(pmu_dev_t *hw, uint32_t flag)
|
||||
{
|
||||
hw->imm.clk_power.val = flag;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_set_icg_slp_sel(pmu_dev_t *hw, bool slp_sel)
|
||||
{
|
||||
if (slp_sel) {
|
||||
hw->imm.sleep_sysclk.tie_high_icg_slp_sel = 1;
|
||||
} else {
|
||||
hw->imm.sleep_sysclk.tie_low_icg_slp_sel = 1;
|
||||
}
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_update_dig_sysclk_sel(pmu_dev_t *hw, bool update)
|
||||
{
|
||||
hw->imm.sleep_sysclk.update_dig_sysclk_sel = update;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_update_dig_icg_switch(pmu_dev_t *hw, bool update)
|
||||
{
|
||||
hw->imm.sleep_sysclk.update_dig_icg_switch = update;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_update_dig_icg_func(pmu_dev_t *hw, bool icg_func_update)
|
||||
{
|
||||
hw->imm.hp_func_icg.update_dig_icg_func_en = icg_func_update;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_update_dig_icg_apb(pmu_dev_t *hw, bool icg_apb_update)
|
||||
{
|
||||
hw->imm.hp_apb_icg.update_dig_icg_apb_en = icg_apb_update;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_update_dig_icg_modem_code(pmu_dev_t *hw, bool icg_modem_update)
|
||||
{
|
||||
hw->imm.modem_icg.update_dig_icg_modem_en = icg_modem_update;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_set_lp_rootclk_sel(pmu_dev_t *hw, bool rootclk_sel)
|
||||
{
|
||||
if (rootclk_sel) {
|
||||
hw->imm.lp_icg.tie_high_lp_rootclk_sel = 1;
|
||||
} else {
|
||||
hw->imm.lp_icg.tie_low_lp_rootclk_sel = 1;
|
||||
}
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_set_hp_pad_hold_all(pmu_dev_t *hw, bool hold_all)
|
||||
{
|
||||
if (hold_all) {
|
||||
hw->imm.pad_hold_all.tie_high_hp_pad_hold_all = 1;
|
||||
} else {
|
||||
hw->imm.pad_hold_all.tie_low_hp_pad_hold_all = 1;
|
||||
}
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_set_lp_pad_hold_all(pmu_dev_t *hw, bool hold_all)
|
||||
{
|
||||
if (hold_all) {
|
||||
hw->imm.pad_hold_all.tie_high_lp_pad_hold_all = 1;
|
||||
} else {
|
||||
hw->imm.pad_hold_all.tie_low_lp_pad_hold_all = 1;
|
||||
}
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_reset(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool rst)
|
||||
{
|
||||
hw->power.hp_pd[domain].force_reset = rst;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_isolate(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool iso)
|
||||
{
|
||||
hw->power.hp_pd[domain].force_iso = iso;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_power_up(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool fpu)
|
||||
{
|
||||
hw->power.hp_pd[domain].force_pu = fpu;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_no_reset(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool no_rst)
|
||||
{
|
||||
hw->power.hp_pd[domain].force_no_reset = no_rst;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_no_isolate(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool no_iso)
|
||||
{
|
||||
hw->power.hp_pd[domain].force_no_iso = no_iso;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_power_down(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool fpd)
|
||||
{
|
||||
hw->power.hp_pd[domain].force_pd = fpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_reset(pmu_dev_t *hw, bool rst)
|
||||
{
|
||||
hw->power.lp_peri.force_reset = rst;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_isolate(pmu_dev_t *hw, bool iso)
|
||||
{
|
||||
hw->power.lp_peri.force_iso = iso;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_power_up(pmu_dev_t *hw, bool fpu)
|
||||
{
|
||||
hw->power.lp_peri.force_pu = fpu;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_no_reset(pmu_dev_t *hw, bool no_rst)
|
||||
{
|
||||
hw->power.lp_peri.force_no_reset = no_rst;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_no_isolate(pmu_dev_t *hw, bool no_iso)
|
||||
{
|
||||
hw->power.lp_peri.force_no_iso = no_iso;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_power_down(pmu_dev_t *hw, bool fpd)
|
||||
{
|
||||
hw->power.lp_peri.force_pd = fpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_memory_isolate(pmu_dev_t *hw, uint32_t iso)
|
||||
{
|
||||
hw->power.mem_cntl.force_hp_mem_iso = iso;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_memory_power_down(pmu_dev_t *hw, uint32_t fpd)
|
||||
{
|
||||
hw->power.mem_cntl.force_hp_mem_pd = fpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_memory_no_isolate(pmu_dev_t *hw, uint32_t no_iso)
|
||||
{
|
||||
hw->power.mem_cntl.force_hp_mem_no_iso = no_iso;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_memory_power_up(pmu_dev_t *hw, uint32_t fpu)
|
||||
{
|
||||
hw->power.mem_cntl.force_hp_mem_pu = fpu;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_enable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->wakeup.cntl0.sleep_req = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_reject_enable(pmu_dev_t *hw, uint32_t reject)
|
||||
{
|
||||
hw->wakeup.cntl1.sleep_reject_ena = reject;
|
||||
hw->wakeup.cntl1.slp_reject_en = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_reject_disable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->wakeup.cntl1.slp_reject_en = 0;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_wakeup_enable(pmu_dev_t *hw, uint32_t wakeup)
|
||||
{
|
||||
hw->wakeup.cntl2 = wakeup;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_protect_mode(pmu_dev_t *hw, int mode)
|
||||
{
|
||||
hw->wakeup.cntl3.sleep_prt_sel = mode;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_min_sleep_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wakeup.cntl3, hp_min_slp_val, cycle);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_clear_reject_cause(pmu_dev_t *hw)
|
||||
{
|
||||
hw->wakeup.cntl4.slp_reject_cause_clr = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR bool pmu_ll_hp_is_sleep_wakeup(pmu_dev_t *hw)
|
||||
{
|
||||
return (hw->hp_ext.int_raw.wakeup == 1);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR bool pmu_ll_hp_is_sleep_reject(pmu_dev_t *hw)
|
||||
{
|
||||
return (hw->hp_ext.int_raw.reject == 1);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_clear_wakeup_intr_status(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_ext.int_clr.wakeup = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_clear_reject_intr_status(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_ext.int_clr.reject = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_wakeup_cause(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->wakeup.status0;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_reject_cause(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->wakeup.status1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_min_sleep_cycle(pmu_dev_t *hw, uint32_t slow_clk_cycle)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wakeup.cntl3, lp_min_slp_val, slow_clk_cycle);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_modify_icg_cntl_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hp_ext.clk_cntl, modify_icg_cntl_wait, cycle);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_modify_icg_cntl_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return HAL_FORCE_READ_U32_REG_FIELD(hw->hp_ext.clk_cntl, modify_icg_cntl_wait);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_switch_icg_cntl_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hp_ext.clk_cntl, switch_icg_cntl_wait, cycle);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_switch_icg_cntl_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return HAL_FORCE_READ_U32_REG_FIELD(hw->hp_ext.clk_cntl, switch_icg_cntl_wait);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_digital_power_down_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
hw->power.wait_timer0.powerdown_timer = cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_digital_power_down_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->power.wait_timer0.powerdown_timer;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_digital_power_down_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
hw->power.wait_timer1.powerdown_timer = cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_digital_power_down_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->power.wait_timer1.powerdown_timer;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_analog_wait_target_cycle(pmu_dev_t *hw, uint32_t slow_clk_cycle)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wakeup.cntl5, lp_ana_wait_target, slow_clk_cycle);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_analog_wait_target_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return HAL_FORCE_READ_U32_REG_FIELD(hw->wakeup.cntl5, lp_ana_wait_target);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_set_xtal_stable_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->power.clk_wait, wait_xtal_stable, cycle);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_get_xtal_stable_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return HAL_FORCE_READ_U32_REG_FIELD(hw->power.clk_wait, wait_xtal_stable);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_set_pll_stable_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->power.clk_wait, wait_pll_stable, cycle);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_get_pll_stable_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return HAL_FORCE_READ_U32_REG_FIELD(hw->power.clk_wait, wait_pll_stable);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_digital_power_supply_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
hw->power.wait_timer1.wait_timer = cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_digital_power_supply_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->power.wait_timer1.wait_timer;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_digital_power_up_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
hw->power.wait_timer1.powerup_timer = cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_digital_power_up_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->power.wait_timer1.powerup_timer;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_analog_wait_target_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wakeup.cntl7, ana_wait_target, cycle);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_analog_wait_target_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return HAL_FORCE_READ_U32_REG_FIELD(hw->wakeup.cntl7, ana_wait_target);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_digital_power_supply_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
hw->power.wait_timer0.wait_timer = cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_digital_power_supply_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->power.wait_timer0.wait_timer;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_digital_power_up_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
hw->power.wait_timer0.powerup_timer = cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_digital_power_up_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->power.wait_timer0.powerup_timer;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,50 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The HAL layer for PMU (ESP32-H2 specific part)
|
||||
|
||||
#include "soc/soc.h"
|
||||
#include "esp_attr.h"
|
||||
#include "hal/pmu_hal.h"
|
||||
#include "hal/pmu_types.h"
|
||||
|
||||
void pmu_hal_hp_set_digital_power_up_wait_cycle(pmu_hal_context_t *hal, uint32_t power_supply_wait_cycle, uint32_t power_up_wait_cycle)
|
||||
{
|
||||
pmu_ll_hp_set_digital_power_supply_wait_cycle(hal->dev, power_supply_wait_cycle);
|
||||
pmu_ll_hp_set_digital_power_up_wait_cycle(hal->dev, power_up_wait_cycle);
|
||||
}
|
||||
|
||||
uint32_t pmu_hal_hp_get_digital_power_up_wait_cycle(pmu_hal_context_t *hal)
|
||||
{
|
||||
uint32_t power_supply_wait_cycle = pmu_ll_hp_get_digital_power_supply_wait_cycle(hal->dev);
|
||||
uint32_t power_up_wait_cycle = pmu_ll_hp_get_digital_power_up_wait_cycle(hal->dev);
|
||||
return power_supply_wait_cycle + power_up_wait_cycle;
|
||||
}
|
||||
|
||||
void pmu_hal_lp_set_digital_power_up_wait_cycle(pmu_hal_context_t *hal, uint32_t power_supply_wait_cycle, uint32_t power_up_wait_cycle)
|
||||
{
|
||||
pmu_ll_lp_set_digital_power_supply_wait_cycle(hal->dev, power_supply_wait_cycle);
|
||||
pmu_ll_lp_set_digital_power_up_wait_cycle(hal->dev, power_up_wait_cycle);
|
||||
}
|
||||
|
||||
uint32_t pmu_hal_lp_get_digital_power_up_wait_cycle(pmu_hal_context_t *hal)
|
||||
{
|
||||
uint32_t power_supply_wait_cycle = pmu_ll_lp_get_digital_power_supply_wait_cycle(hal->dev);
|
||||
uint32_t power_up_wait_cycle = pmu_ll_lp_get_digital_power_up_wait_cycle(hal->dev);
|
||||
return power_supply_wait_cycle + power_up_wait_cycle;
|
||||
}
|
||||
|
||||
void pmu_hal_hp_set_sleep_active_backup_enable(pmu_hal_context_t *hal)
|
||||
{
|
||||
pmu_ll_hp_set_active_to_sleep_backup_enable(hal->dev);
|
||||
pmu_ll_hp_set_sleep_to_active_backup_enable(hal->dev);
|
||||
}
|
||||
|
||||
void pmu_hal_hp_set_sleep_active_backup_disable(pmu_hal_context_t *hal)
|
||||
{
|
||||
pmu_ll_hp_set_sleep_to_active_backup_disable(hal->dev);
|
||||
pmu_ll_hp_set_active_to_sleep_backup_disable(hal->dev);
|
||||
}
|
||||
@@ -0,0 +1,41 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The HAL layer for PMU
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "soc/soc_caps.h"
|
||||
#include "hal/pmu_ll.h"
|
||||
#include "hal/pmu_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef struct {
|
||||
pmu_dev_t *dev;
|
||||
} pmu_hal_context_t;
|
||||
|
||||
void pmu_hal_hp_set_digital_power_up_wait_cycle(pmu_hal_context_t *hal, uint32_t power_supply_wait_cycle, uint32_t power_up_wait_cycle);
|
||||
|
||||
uint32_t pmu_hal_hp_get_digital_power_up_wait_cycle(pmu_hal_context_t *hal);
|
||||
|
||||
void pmu_hal_lp_set_digital_power_up_wait_cycle(pmu_hal_context_t *hal, uint32_t power_supply_wait_cycle, uint32_t power_up_wait_cycle);
|
||||
|
||||
uint32_t pmu_hal_lp_get_digital_power_up_wait_cycle(pmu_hal_context_t *hal);
|
||||
|
||||
void pmu_hal_hp_set_control_ready_wait_cycle(pmu_hal_context_t *hal, uint32_t isolate_wait_cycle, uint32_t reset_wait_cycle);
|
||||
|
||||
void pmu_hal_lp_set_control_ready_wait_cycle(pmu_hal_context_t *hal, uint32_t isolate_wait_cycle, uint32_t reset_wait_cycle);
|
||||
|
||||
void pmu_hal_hp_set_sleep_active_backup_enable(pmu_hal_context_t *hal);
|
||||
|
||||
void pmu_hal_hp_set_sleep_active_backup_disable(pmu_hal_context_t *hal);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,742 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The LL layer for ESP32-H21 PMU register operations
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <stdbool.h>
|
||||
#include "soc/soc.h"
|
||||
#include "esp_attr.h"
|
||||
#include "hal/assert.h"
|
||||
#include "soc/pmu_struct.h"
|
||||
#include "hal/pmu_types.h"
|
||||
#include "hal/misc.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Set the power domain that needs to be powered down in the digital power
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param mode The pmu mode
|
||||
* @param flag Digital power domain flag
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_dig_power(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t flag)
|
||||
{
|
||||
hw->hp_sys[mode].dig_power.val = flag;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_func(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t icg_func)
|
||||
{
|
||||
hw->hp_sys[mode].icg_func = icg_func;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_apb(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t bitmap)
|
||||
{
|
||||
hw->hp_sys[mode].icg_apb = bitmap;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_modem(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t code)
|
||||
{
|
||||
hw->hp_sys[mode].icg_modem.code = code;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_uart_wakeup_enable(pmu_dev_t *hw, pmu_hp_mode_t mode, bool wakeup_en)
|
||||
{
|
||||
hw->hp_sys[mode].syscntl.uart_wakeup_en = wakeup_en;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_hold_all_lp_pad(pmu_dev_t *hw, pmu_hp_mode_t mode, bool hold_all)
|
||||
{
|
||||
hw->hp_sys[mode].syscntl.lp_pad_hold_all = hold_all;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_hold_all_hp_pad(pmu_dev_t *hw, pmu_hp_mode_t mode, bool hold_all)
|
||||
{
|
||||
hw->hp_sys[mode].syscntl.hp_pad_hold_all = hold_all;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_dig_pad_slp_sel(pmu_dev_t *hw, pmu_hp_mode_t mode, bool slp_sel)
|
||||
{
|
||||
hw->hp_sys[mode].syscntl.dig_pad_slp_sel = slp_sel;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_pause_watchdog(pmu_dev_t *hw, pmu_hp_mode_t mode, bool pause_wdt)
|
||||
{
|
||||
hw->hp_sys[mode].syscntl.dig_pause_wdt = pause_wdt;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_cpu_stall(pmu_dev_t *hw, pmu_hp_mode_t mode, bool cpu_stall)
|
||||
{
|
||||
hw->hp_sys[mode].syscntl.dig_cpu_stall = cpu_stall;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the power domain that needs to be powered down in the clock power
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param mode The pmu mode
|
||||
* @param flag Clock power domain flag
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_clk_power(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t xpd_flag)
|
||||
{
|
||||
hw->hp_sys[mode].clk_power.val = xpd_flag;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_dcdc_ccm_enable(pmu_dev_t *hw, pmu_hp_mode_t mode, bool enable)
|
||||
{
|
||||
hw->hp_sys[mode].bias.dcdc_ccm_enb = enable;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_dig_reg_dpcur_bias(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t bias)
|
||||
{
|
||||
hw->hp_sys[mode].bias.dig_reg_dpcur_bias = bias;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_dig_reg_dsfmos(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t value)
|
||||
{
|
||||
hw->hp_sys[mode].bias.dig_reg_dsfmos = value;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_dcm_vset(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t value)
|
||||
{
|
||||
hw->hp_sys[mode].bias.dcm_vset = value;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_dcm_mode(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t dcm_mode)
|
||||
{
|
||||
hw->hp_sys[mode].bias.dcm_mode = dcm_mode;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_bias_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool xpd_bias)
|
||||
{
|
||||
hw->hp_sys[mode].bias.xpd_bias = xpd_bias;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_trx_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool xpd_trx)
|
||||
{
|
||||
hw->hp_sys[mode].bias.xpd_trx = xpd_trx;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_xtal_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool xpd_xtal)
|
||||
{
|
||||
hw->hp_sys[mode].xtal.xpd_xtal = xpd_xtal;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_discnnt_dig_rtc(pmu_dev_t *hw, pmu_hp_mode_t mode, bool discnnt)
|
||||
{
|
||||
hw->hp_sys[mode].bias.discnnt_dig_rtc = discnnt;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_current_power_off(pmu_dev_t *hw, pmu_hp_mode_t mode, bool off)
|
||||
{
|
||||
hw->hp_sys[mode].bias.pd_cur = off;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_bias_sleep_enable(pmu_dev_t *hw, pmu_hp_mode_t mode, bool en)
|
||||
{
|
||||
hw->hp_sys[mode].bias.bias_sleep = en;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_retention_param(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t param)
|
||||
{
|
||||
hw->hp_sys[mode].backup.val = param;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_to_active_backup_enable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_sys[PMU_MODE_HP_ACTIVE].backup.hp_sleep2active_backup_en = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_to_active_backup_disable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_sys[PMU_MODE_HP_ACTIVE].backup.hp_sleep2active_backup_en = 0;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_active_to_sleep_backup_enable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_sys[PMU_MODE_HP_SLEEP].backup.hp_active2sleep_backup_en = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_active_to_sleep_backup_disable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_sys[PMU_MODE_HP_SLEEP].backup.hp_active2sleep_backup_en = 0;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_backup_icg_func(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t icg_func)
|
||||
{
|
||||
hw->hp_sys[mode].backup_clk = icg_func;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_sysclk_nodiv(pmu_dev_t *hw, pmu_hp_mode_t mode, bool sysclk_nodiv)
|
||||
{
|
||||
hw->hp_sys[mode].sysclk.dig_sysclk_nodiv = sysclk_nodiv;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_sysclk_enable(pmu_dev_t *hw, pmu_hp_mode_t mode, bool icg_sysclk_en)
|
||||
{
|
||||
hw->hp_sys[mode].sysclk.icg_sysclk_en = icg_sysclk_en;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_sysclk_slp_sel(pmu_dev_t *hw, pmu_hp_mode_t mode, bool slp_sel)
|
||||
{
|
||||
hw->hp_sys[mode].sysclk.sysclk_slp_sel = slp_sel;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_sysclk_slp_sel(pmu_dev_t *hw, pmu_hp_mode_t mode, bool slp_sel)
|
||||
{
|
||||
hw->hp_sys[mode].sysclk.icg_slp_sel = slp_sel;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_dig_sysclk(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t sysclk_sel)
|
||||
{
|
||||
hw->hp_sys[mode].sysclk.dig_sysclk_sel = sysclk_sel;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_power_detect_bypass(pmu_dev_t *hw, pmu_hp_mode_t mode, bool bypass)
|
||||
{
|
||||
hw->hp_sys[mode].regulator0.power_det_bypass = bypass;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_lp_dbias_voltage(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t voltage)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_HP_ACTIVE);
|
||||
hw->hp_sys[mode].regulator0.lp_dbias_vol = voltage;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_hp_dbias_voltage(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t voltage)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_HP_ACTIVE);
|
||||
hw->hp_sys[mode].regulator0.hp_dbias_vol = voltage;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_dbias_select(pmu_dev_t *hw, pmu_hp_mode_t mode, bool sel)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_HP_ACTIVE);
|
||||
hw->hp_sys[mode].regulator0.dbias_sel = sel;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_dbias_init(pmu_dev_t *hw, pmu_hp_mode_t mode, bool init)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_HP_ACTIVE);
|
||||
hw->hp_sys[mode].regulator0.dbias_init = init;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_sleep_logic_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool slp_xpd)
|
||||
{
|
||||
hw->hp_sys[mode].regulator0.slp_logic_xpd = slp_xpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_sleep_memory_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool slp_xpd)
|
||||
{
|
||||
hw->hp_sys[mode].regulator0.slp_mem_xpd = slp_xpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool xpd)
|
||||
{
|
||||
hw->hp_sys[mode].regulator0.xpd = xpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_sleep_logic_dbias(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t slp_dbias)
|
||||
{
|
||||
hw->hp_sys[mode].regulator0.slp_logic_dbias = slp_dbias;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_sleep_memory_dbias(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t slp_dbias)
|
||||
{
|
||||
hw->hp_sys[mode].regulator0.slp_mem_dbias = slp_dbias;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_dbias(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t dbias)
|
||||
{
|
||||
hw->hp_sys[mode].regulator0.dbias = dbias;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_driver_bar(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t drv_b)
|
||||
{
|
||||
hw->hp_sys[mode].regulator1.drv_b = drv_b;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_regulator_slp_xpd(pmu_dev_t *hw, pmu_lp_mode_t mode, bool slp_xpd)
|
||||
{
|
||||
hw->lp_sys[mode].regulator0.slp_xpd = slp_xpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_regulator_xpd(pmu_dev_t *hw, pmu_lp_mode_t mode, bool xpd)
|
||||
{
|
||||
hw->lp_sys[mode].regulator0.xpd = xpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_regulator_sleep_dbias(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t slp_dbias)
|
||||
{
|
||||
hw->lp_sys[mode].regulator0.slp_dbias = slp_dbias;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_regulator_dbias(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t dbias)
|
||||
{
|
||||
hw->lp_sys[mode].regulator0.dbias = dbias;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_regulator_driver_bar(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t drv_b)
|
||||
{
|
||||
hw->lp_sys[mode].regulator1.drv_b = drv_b;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_xtal_xpd(pmu_dev_t *hw, pmu_lp_mode_t mode, bool slp_xpd)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
|
||||
hw->lp_sys[mode].xtal.xpd_xtal = slp_xpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_dig_power(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t flag)
|
||||
{
|
||||
hw->lp_sys[mode].dig_power.val = flag;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_clk_power(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t xpd_flag)
|
||||
{
|
||||
hw->lp_sys[mode].clk_power.val = xpd_flag;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_clk_power(pmu_dev_t *hw, pmu_lp_mode_t mode)
|
||||
{
|
||||
return hw->lp_sys[mode].clk_power.val;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_dcdc_ccm_enable(pmu_dev_t *hw, pmu_lp_mode_t mode, bool enable)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
|
||||
hw->lp_sys[mode].bias.dcdc_ccm_enb = enable;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_dig_reg_dpcur_bias(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t value)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
|
||||
hw->lp_sys[mode].bias.dig_reg_dpcur_bias = value;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_dig_reg_dsfmos(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t value)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
|
||||
hw->lp_sys[mode].bias.dig_reg_dsfmos = value;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_dcm_vset(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t value)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
|
||||
hw->lp_sys[mode].bias.dcm_vset = value;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_dcm_mode(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t dcm_mode)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
|
||||
hw->lp_sys[mode].bias.dcm_mode = dcm_mode;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_bias_xpd(pmu_dev_t *hw, pmu_lp_mode_t mode, bool xpd_bias)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
|
||||
hw->lp_sys[mode].bias.xpd_bias = xpd_bias;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_memory_power_on_mask(pmu_dev_t *hw, uint32_t mem_mask)
|
||||
{
|
||||
hw->power.mem_mask.mem0_mask = mem_mask & BIT(0);
|
||||
hw->power.mem_mask.mem1_mask = mem_mask & BIT(1);
|
||||
hw->power.mem_mask.mem2_mask = mem_mask & BIT(2);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_discnnt_dig_rtc(pmu_dev_t *hw, pmu_lp_mode_t mode, bool discnnt)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
|
||||
hw->lp_sys[mode].bias.discnnt_dig_rtc = discnnt;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_current_power_off(pmu_dev_t *hw, pmu_lp_mode_t mode, bool off)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
|
||||
hw->lp_sys[mode].bias.pd_cur = off;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_bias_sleep_enable(pmu_dev_t *hw, pmu_lp_mode_t mode, bool en)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
|
||||
hw->lp_sys[mode].bias.bias_sleep = en;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_set_clk_power(pmu_dev_t *hw, uint32_t flag)
|
||||
{
|
||||
hw->imm.clk_power.val = flag;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_set_icg_slp_sel(pmu_dev_t *hw, bool slp_sel)
|
||||
{
|
||||
if (slp_sel) {
|
||||
hw->imm.sleep_sysclk.tie_high_icg_slp_sel = 1;
|
||||
} else {
|
||||
hw->imm.sleep_sysclk.tie_low_icg_slp_sel = 1;
|
||||
}
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_update_dig_sysclk_sel(pmu_dev_t *hw, bool update)
|
||||
{
|
||||
hw->imm.sleep_sysclk.update_dig_sysclk_sel = update;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_update_dig_icg_switch(pmu_dev_t *hw, bool update)
|
||||
{
|
||||
hw->imm.sleep_sysclk.update_dig_icg_switch = update;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_update_dig_icg_func(pmu_dev_t *hw, bool icg_func_update)
|
||||
{
|
||||
hw->imm.hp_func_icg.update_dig_icg_func_en = icg_func_update;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_update_dig_icg_apb(pmu_dev_t *hw, bool icg_apb_update)
|
||||
{
|
||||
hw->imm.hp_apb_icg.update_dig_icg_apb_en = icg_apb_update;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_update_dig_icg_modem_code(pmu_dev_t *hw, bool icg_modem_update)
|
||||
{
|
||||
hw->imm.modem_icg.update_dig_icg_modem_en = icg_modem_update;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_set_lp_rootclk_sel(pmu_dev_t *hw, bool rootclk_sel)
|
||||
{
|
||||
if (rootclk_sel) {
|
||||
hw->imm.lp_icg.tie_high_lp_rootclk_sel = 1;
|
||||
} else {
|
||||
hw->imm.lp_icg.tie_low_lp_rootclk_sel = 1;
|
||||
}
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_set_hp_pad_hold_all(pmu_dev_t *hw, bool hold_all)
|
||||
{
|
||||
if (hold_all) {
|
||||
hw->imm.pad_hold_all.tie_high_hp_pad_hold_all = 1;
|
||||
} else {
|
||||
hw->imm.pad_hold_all.tie_low_hp_pad_hold_all = 1;
|
||||
}
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_set_lp_pad_hold_all(pmu_dev_t *hw, bool hold_all)
|
||||
{
|
||||
if (hold_all) {
|
||||
hw->imm.pad_hold_all.tie_high_lp_pad_hold_all = 1;
|
||||
} else {
|
||||
hw->imm.pad_hold_all.tie_low_lp_pad_hold_all = 1;
|
||||
}
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_reset(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool rst)
|
||||
{
|
||||
hw->power.hp_pd[domain].force_reset = rst;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_isolate(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool iso)
|
||||
{
|
||||
hw->power.hp_pd[domain].force_iso = iso;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_power_up(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool fpu)
|
||||
{
|
||||
hw->power.hp_pd[domain].force_pu = fpu;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_no_reset(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool no_rst)
|
||||
{
|
||||
hw->power.hp_pd[domain].force_no_reset = no_rst;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_no_isolate(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool no_iso)
|
||||
{
|
||||
hw->power.hp_pd[domain].force_no_iso = no_iso;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_power_down(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool fpd)
|
||||
{
|
||||
hw->power.hp_pd[domain].force_pd = fpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_reset(pmu_dev_t *hw, bool rst)
|
||||
{
|
||||
hw->power.lp_peri.force_reset = rst;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_isolate(pmu_dev_t *hw, bool iso)
|
||||
{
|
||||
hw->power.lp_peri.force_iso = iso;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_power_up(pmu_dev_t *hw, bool fpu)
|
||||
{
|
||||
hw->power.lp_peri.force_pu = fpu;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_no_reset(pmu_dev_t *hw, bool no_rst)
|
||||
{
|
||||
hw->power.lp_peri.force_no_reset = no_rst;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_no_isolate(pmu_dev_t *hw, bool no_iso)
|
||||
{
|
||||
hw->power.lp_peri.force_no_iso = no_iso;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_power_down(pmu_dev_t *hw, bool fpd)
|
||||
{
|
||||
hw->power.lp_peri.force_pd = fpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_memory_isolate(pmu_dev_t *hw, uint32_t iso)
|
||||
{
|
||||
hw->power.mem_cntl.force_hp_mem_iso = iso;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_memory_power_down(pmu_dev_t *hw, uint32_t fpd)
|
||||
{
|
||||
hw->power.mem_cntl.force_hp_mem_pd = fpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_memory_no_isolate(pmu_dev_t *hw, uint32_t no_iso)
|
||||
{
|
||||
hw->power.mem_cntl.force_hp_mem_no_iso = no_iso;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_memory_power_up(pmu_dev_t *hw, uint32_t fpu)
|
||||
{
|
||||
hw->power.mem_cntl.force_hp_mem_pu = fpu;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_enable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->wakeup.cntl0.sleep_req = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_reject_enable(pmu_dev_t *hw, uint32_t reject)
|
||||
{
|
||||
hw->wakeup.cntl1.sleep_reject_ena = reject;
|
||||
hw->wakeup.cntl1.slp_reject_en = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_reject_disable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->wakeup.cntl1.slp_reject_en = 0;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_wakeup_enable(pmu_dev_t *hw, uint32_t wakeup)
|
||||
{
|
||||
hw->wakeup.cntl2 = wakeup;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_protect_mode(pmu_dev_t *hw, int mode)
|
||||
{
|
||||
hw->wakeup.cntl3.sleep_prt_sel = mode;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_min_sleep_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wakeup.cntl3, hp_min_slp_val, cycle);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_clear_reject_cause(pmu_dev_t *hw)
|
||||
{
|
||||
hw->wakeup.cntl4.slp_reject_cause_clr = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR bool pmu_ll_hp_is_sleep_wakeup(pmu_dev_t *hw)
|
||||
{
|
||||
return (hw->hp_ext.int_raw.soc_wakeup == 1);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR bool pmu_ll_hp_is_sleep_reject(pmu_dev_t *hw)
|
||||
{
|
||||
return (hw->hp_ext.int_raw.soc_sleep_reject == 1);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_clear_wakeup_intr_status(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_ext.int_clr.soc_wakeup = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_clear_reject_intr_status(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_ext.int_clr.soc_sleep_reject = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_wakeup_cause(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->wakeup.status0;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_reject_cause(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->wakeup.status1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_min_sleep_cycle(pmu_dev_t *hw, uint32_t slow_clk_cycle)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wakeup.cntl3, lp_min_slp_val, slow_clk_cycle);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_modify_icg_cntl_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hp_ext.clk_cntl, modify_icg_cntl_wait, cycle);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_modify_icg_cntl_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return HAL_FORCE_READ_U32_REG_FIELD(hw->hp_ext.clk_cntl, modify_icg_cntl_wait);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_switch_icg_cntl_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hp_ext.clk_cntl, switch_icg_cntl_wait, cycle);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_switch_icg_cntl_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return HAL_FORCE_READ_U32_REG_FIELD(hw->hp_ext.clk_cntl, switch_icg_cntl_wait);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_digital_power_down_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
hw->power.wait_timer0.powerdown_timer = cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_digital_power_down_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->power.wait_timer0.powerdown_timer;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_digital_power_down_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
hw->power.wait_timer1.powerdown_timer = cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_digital_power_down_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->power.wait_timer1.powerdown_timer;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_analog_wait_target_cycle(pmu_dev_t *hw, uint32_t slow_clk_cycle)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wakeup.cntl5, lp_ana_wait_target, slow_clk_cycle);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_analog_wait_target_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return HAL_FORCE_READ_U32_REG_FIELD(hw->wakeup.cntl5, lp_ana_wait_target);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_set_xtal_stable_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->power.clk_wait, wait_xtal_stable, cycle);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_get_xtal_stable_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return HAL_FORCE_READ_U32_REG_FIELD(hw->power.clk_wait, wait_xtal_stable);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_set_pll_stable_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->power.clk_wait, wait_pll_stable, cycle);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_get_pll_stable_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return HAL_FORCE_READ_U32_REG_FIELD(hw->power.clk_wait, wait_pll_stable);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_digital_power_supply_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
hw->power.wait_timer1.wait_timer = cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_digital_power_supply_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->power.wait_timer1.wait_timer;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_digital_power_up_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
hw->power.wait_timer1.powerup_timer = cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_digital_power_up_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->power.wait_timer1.powerup_timer;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_isolate_wait_cycle(pmu_dev_t *hw, uint32_t isolate_wait_cycle)
|
||||
{
|
||||
hw->power.wait_timer2.lp_iso_wait_timer = isolate_wait_cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_reset_wait_cycle(pmu_dev_t *hw, uint32_t reset_wait_cycle)
|
||||
{
|
||||
hw->power.wait_timer2.lp_rst_wait_timer = reset_wait_cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_isolate_wait_cycle(pmu_dev_t *hw, uint32_t isolate_wait_cycle)
|
||||
{
|
||||
hw->power.wait_timer2.hp_iso_wait_timer = isolate_wait_cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_reset_wait_cycle(pmu_dev_t *hw, uint32_t reset_wait_cycle)
|
||||
{
|
||||
hw->power.wait_timer2.hp_rst_wait_timer = reset_wait_cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_analog_wait_target_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wakeup.cntl7, ana_wait_target, cycle);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_analog_wait_target_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return HAL_FORCE_READ_U32_REG_FIELD(hw->wakeup.cntl7, ana_wait_target);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_digital_power_supply_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
hw->power.wait_timer0.wait_timer = cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_digital_power_supply_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->power.wait_timer0.wait_timer;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_digital_power_up_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
hw->power.wait_timer0.powerup_timer = cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_digital_power_up_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->power.wait_timer0.powerup_timer;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_set_dcdc_ccm_sw_en(pmu_dev_t *hw, bool enable)
|
||||
{
|
||||
hw->dcm_ctrl.dcdc_ccm_sw_en = enable;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,62 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The HAL layer for PMU (ESP32-H2 specific part)
|
||||
|
||||
#include "soc/soc.h"
|
||||
#include "esp_attr.h"
|
||||
#include "hal/pmu_hal.h"
|
||||
#include "hal/pmu_types.h"
|
||||
|
||||
void pmu_hal_hp_set_digital_power_up_wait_cycle(pmu_hal_context_t *hal, uint32_t power_supply_wait_cycle, uint32_t power_up_wait_cycle)
|
||||
{
|
||||
pmu_ll_hp_set_digital_power_supply_wait_cycle(hal->dev, power_supply_wait_cycle);
|
||||
pmu_ll_hp_set_digital_power_up_wait_cycle(hal->dev, power_up_wait_cycle);
|
||||
}
|
||||
|
||||
uint32_t pmu_hal_hp_get_digital_power_up_wait_cycle(pmu_hal_context_t *hal)
|
||||
{
|
||||
uint32_t power_supply_wait_cycle = pmu_ll_hp_get_digital_power_supply_wait_cycle(hal->dev);
|
||||
uint32_t power_up_wait_cycle = pmu_ll_hp_get_digital_power_up_wait_cycle(hal->dev);
|
||||
return power_supply_wait_cycle + power_up_wait_cycle;
|
||||
}
|
||||
|
||||
void pmu_hal_lp_set_digital_power_up_wait_cycle(pmu_hal_context_t *hal, uint32_t power_supply_wait_cycle, uint32_t power_up_wait_cycle)
|
||||
{
|
||||
pmu_ll_lp_set_digital_power_supply_wait_cycle(hal->dev, power_supply_wait_cycle);
|
||||
pmu_ll_lp_set_digital_power_up_wait_cycle(hal->dev, power_up_wait_cycle);
|
||||
}
|
||||
|
||||
uint32_t pmu_hal_lp_get_digital_power_up_wait_cycle(pmu_hal_context_t *hal)
|
||||
{
|
||||
uint32_t power_supply_wait_cycle = pmu_ll_lp_get_digital_power_supply_wait_cycle(hal->dev);
|
||||
uint32_t power_up_wait_cycle = pmu_ll_lp_get_digital_power_up_wait_cycle(hal->dev);
|
||||
return power_supply_wait_cycle + power_up_wait_cycle;
|
||||
}
|
||||
|
||||
void pmu_hal_hp_set_control_ready_wait_cycle(pmu_hal_context_t *hal, uint32_t isolate_wait_cycle, uint32_t reset_wait_cycle)
|
||||
{
|
||||
pmu_ll_hp_set_isolate_wait_cycle(hal->dev, isolate_wait_cycle);
|
||||
pmu_ll_hp_set_reset_wait_cycle(hal->dev, reset_wait_cycle);
|
||||
}
|
||||
|
||||
void pmu_hal_lp_set_control_ready_wait_cycle(pmu_hal_context_t *hal, uint32_t isolate_wait_cycle, uint32_t reset_wait_cycle)
|
||||
{
|
||||
pmu_ll_lp_set_isolate_wait_cycle(hal->dev, isolate_wait_cycle);
|
||||
pmu_ll_lp_set_reset_wait_cycle(hal->dev, reset_wait_cycle);
|
||||
}
|
||||
|
||||
void pmu_hal_hp_set_sleep_active_backup_enable(pmu_hal_context_t *hal)
|
||||
{
|
||||
pmu_ll_hp_set_active_to_sleep_backup_enable(hal->dev);
|
||||
pmu_ll_hp_set_sleep_to_active_backup_enable(hal->dev);
|
||||
}
|
||||
|
||||
void pmu_hal_hp_set_sleep_active_backup_disable(pmu_hal_context_t *hal)
|
||||
{
|
||||
pmu_ll_hp_set_sleep_to_active_backup_disable(hal->dev);
|
||||
pmu_ll_hp_set_active_to_sleep_backup_disable(hal->dev);
|
||||
}
|
||||
@@ -0,0 +1,49 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The HAL layer for PMU
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "soc/soc_caps.h"
|
||||
#include "hal/pmu_ll.h"
|
||||
#include "hal/pmu_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef struct {
|
||||
pmu_dev_t *dev;
|
||||
} pmu_hal_context_t;
|
||||
|
||||
void pmu_hal_hp_set_digital_power_up_wait_cycle(pmu_hal_context_t *hal, uint32_t power_supply_wait_cycle, uint32_t power_up_wait_cycle);
|
||||
|
||||
uint32_t pmu_hal_hp_get_digital_power_up_wait_cycle(pmu_hal_context_t *hal);
|
||||
|
||||
void pmu_hal_lp_set_digital_power_up_wait_cycle(pmu_hal_context_t *hal, uint32_t power_supply_wait_cycle, uint32_t power_up_wait_cycle);
|
||||
|
||||
uint32_t pmu_hal_lp_get_digital_power_up_wait_cycle(pmu_hal_context_t *hal);
|
||||
|
||||
void pmu_hal_hp_set_control_ready_wait_cycle(pmu_hal_context_t *hal, uint32_t isolate_wait_cycle, uint32_t reset_wait_cycle);
|
||||
|
||||
void pmu_hal_lp_set_control_ready_wait_cycle(pmu_hal_context_t *hal, uint32_t isolate_wait_cycle, uint32_t reset_wait_cycle);
|
||||
|
||||
void pmu_hal_hp_set_sleep_active_backup_enable(pmu_hal_context_t *hal);
|
||||
|
||||
void pmu_hal_hp_set_sleep_active_backup_disable(pmu_hal_context_t *hal);
|
||||
|
||||
void pmu_hal_hp_set_sleep_modem_backup_enable(pmu_hal_context_t *hal);
|
||||
|
||||
void pmu_hal_hp_set_sleep_modem_backup_disable(pmu_hal_context_t *hal);
|
||||
|
||||
void pmu_hal_hp_set_modem_active_backup_enable(pmu_hal_context_t *hal);
|
||||
|
||||
void pmu_hal_hp_set_modem_active_backup_disable(pmu_hal_context_t *hal);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,848 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The LL layer for ESP32-H4 PMU register operations
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <stdbool.h>
|
||||
#include "soc/soc.h"
|
||||
#include "esp_attr.h"
|
||||
#include "hal/assert.h"
|
||||
#include "soc/pmu_struct.h"
|
||||
#include "hal/pmu_types.h"
|
||||
#include "hal/misc.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Set the power domain that needs to be powered down in the digital power
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param mode The pmu mode
|
||||
* @param flag Digital power domain flag
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_dig_power(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t flag)
|
||||
{
|
||||
hw->hp_sys[mode].dig_power.val = flag;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_func(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t icg_func)
|
||||
{
|
||||
hw->hp_sys[mode].icg_func = icg_func;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_apb(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t bitmap)
|
||||
{
|
||||
hw->hp_sys[mode].icg_apb = bitmap;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_modem(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t code)
|
||||
{
|
||||
hw->hp_sys[mode].icg_modem.code = code;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_uart_wakeup_enable(pmu_dev_t *hw, pmu_hp_mode_t mode, bool wakeup_en)
|
||||
{
|
||||
hw->hp_sys[mode].syscntl.uart_wakeup_en = wakeup_en;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_hold_all_lp_pad(pmu_dev_t *hw, pmu_hp_mode_t mode, bool hold_all)
|
||||
{
|
||||
hw->hp_sys[mode].syscntl.lp_pad_hold_all = hold_all;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_hold_all_hp_pad(pmu_dev_t *hw, pmu_hp_mode_t mode, bool hold_all)
|
||||
{
|
||||
hw->hp_sys[mode].syscntl.hp_pad_hold_all = hold_all;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_dig_pad_slp_sel(pmu_dev_t *hw, pmu_hp_mode_t mode, bool slp_sel)
|
||||
{
|
||||
hw->hp_sys[mode].syscntl.dig_pad_slp_sel = slp_sel;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_pause_watchdog(pmu_dev_t *hw, pmu_hp_mode_t mode, bool pause_wdt)
|
||||
{
|
||||
hw->hp_sys[mode].syscntl.dig_pause_wdt = pause_wdt;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_cpu_stall(pmu_dev_t *hw, pmu_hp_mode_t mode, bool cpu_stall)
|
||||
{
|
||||
hw->hp_sys[mode].syscntl.dig_cpu_stall = cpu_stall;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the power domain that needs to be powered down in the clock power
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param mode The pmu mode
|
||||
* @param flag Clock power domain flag
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_clk_power(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t xpd_flag)
|
||||
{
|
||||
hw->hp_sys[mode].clk_power.val = xpd_flag;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_xtal_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool xpd_xtal)
|
||||
{
|
||||
hw->hp_sys[mode].xtal.xpd_xtal = xpd_xtal;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_xtalx2_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool xpd_xtalx2)
|
||||
{
|
||||
hw->hp_sys[mode].xtal.xpd_xtalx2 = xpd_xtalx2;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_bias_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool xpd_bias)
|
||||
{
|
||||
hw->hp_sys[mode].bias.xpd_bias = xpd_bias;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_trx_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool xpd_trx)
|
||||
{
|
||||
hw->hp_sys[mode].bias.xpd_trx = xpd_trx;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_dcdc_ccm_enable(pmu_dev_t *hw, pmu_hp_mode_t mode, bool enable)
|
||||
{
|
||||
hw->hp_sys[mode].bias.dcdc_ccm_enb = enable;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_dcdc_clear_ready(pmu_dev_t *hw, pmu_hp_mode_t mode, bool clear_rdy)
|
||||
{
|
||||
hw->hp_sys[mode].bias.dcdc_clear_rdy = clear_rdy;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_dig_reg_dpcur_bias(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t value)
|
||||
{
|
||||
hw->hp_sys[mode].bias.dig_reg_dpcur_bias = value;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_dig_reg_dsfmos(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t value)
|
||||
{
|
||||
hw->hp_sys[mode].bias.dig_reg_dsfmos = value;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_dcm_vset(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t value)
|
||||
{
|
||||
hw->hp_sys[mode].bias.dcm_vset = value;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_dcm_mode(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t dcm_mode)
|
||||
{
|
||||
hw->hp_sys[mode].bias.dcm_mode = dcm_mode;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_xpd_trx(pmu_dev_t *hw, pmu_hp_mode_t mode, bool xpd_trx)
|
||||
{
|
||||
hw->hp_sys[mode].bias.xpd_trx = xpd_trx;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_discnnt_dig_rtc(pmu_dev_t *hw, pmu_hp_mode_t mode, bool discnnt)
|
||||
{
|
||||
hw->hp_sys[mode].bias.discnnt_dig_rtc = discnnt;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_current_power_off(pmu_dev_t *hw, pmu_hp_mode_t mode, bool off)
|
||||
{
|
||||
hw->hp_sys[mode].bias.pd_cur = off;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_bias_sleep_enable(pmu_dev_t *hw, pmu_hp_mode_t mode, bool en)
|
||||
{
|
||||
hw->hp_sys[mode].bias.bias_sleep = en;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_retention_param(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t param)
|
||||
{
|
||||
hw->hp_sys[mode].backup.val = param;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_to_active_backup_enable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_sys[PMU_MODE_HP_ACTIVE].backup.hp_sleep2active_backup_en = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_to_active_backup_disable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_sys[PMU_MODE_HP_ACTIVE].backup.hp_sleep2active_backup_en = 0;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_modem_to_active_backup_enable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_sys[PMU_MODE_HP_ACTIVE].backup.hp_modem2active_backup_en = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_modem_to_active_backup_disable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_sys[PMU_MODE_HP_ACTIVE].backup.hp_modem2active_backup_en = 0;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_to_modem_backup_enable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_sys[PMU_MODE_HP_MODEM].backup.hp_sleep2modem_backup_en = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_to_modem_backup_disable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_sys[PMU_MODE_HP_MODEM].backup.hp_sleep2modem_backup_en = 0;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_active_to_sleep_backup_enable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_sys[PMU_MODE_HP_SLEEP].backup.hp_active2sleep_backup_en = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_active_to_sleep_backup_disable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_sys[PMU_MODE_HP_SLEEP].backup.hp_active2sleep_backup_en = 0;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_modem_to_sleep_backup_enable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_sys[PMU_MODE_HP_SLEEP].backup.hp_modem2sleep_backup_en = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_modem_to_sleep_backup_disable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_sys[PMU_MODE_HP_SLEEP].backup.hp_modem2sleep_backup_en = 0;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_backup_icg_func(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t icg_func)
|
||||
{
|
||||
hw->hp_sys[mode].backup_clk = icg_func;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_sysclk_nodiv(pmu_dev_t *hw, pmu_hp_mode_t mode, bool sysclk_nodiv)
|
||||
{
|
||||
hw->hp_sys[mode].sysclk.dig_sysclk_nodiv = sysclk_nodiv;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_sysclk_enable(pmu_dev_t *hw, pmu_hp_mode_t mode, bool icg_sysclk_en)
|
||||
{
|
||||
hw->hp_sys[mode].sysclk.icg_sysclk_en = icg_sysclk_en;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_sysclk_slp_sel(pmu_dev_t *hw, pmu_hp_mode_t mode, bool slp_sel)
|
||||
{
|
||||
hw->hp_sys[mode].sysclk.sysclk_slp_sel = slp_sel;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_sysclk_slp_sel(pmu_dev_t *hw, pmu_hp_mode_t mode, bool slp_sel)
|
||||
{
|
||||
hw->hp_sys[mode].sysclk.icg_slp_sel = slp_sel;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_dig_sysclk(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t sysclk_sel)
|
||||
{
|
||||
hw->hp_sys[mode].sysclk.dig_sysclk_sel = sysclk_sel;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_sleep_logic_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool slp_xpd)
|
||||
{
|
||||
hw->hp_sys[mode].regulator0.slp_logic_xpd = slp_xpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_power_detect_bypass(pmu_dev_t *hw, pmu_hp_mode_t mode, bool bypass)
|
||||
{
|
||||
hw->hp_sys[mode].regulator0.power_det_bypass = bypass;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_dbias_sel(pmu_dev_t *hw, pmu_hp_mode_t mode, bool dbias_sel)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_HP_ACTIVE);
|
||||
hw->hp_sys[mode].regulator0.dbias_sel = dbias_sel;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_dbias_init(pmu_dev_t *hw, pmu_hp_mode_t mode, bool dbias_init)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_HP_ACTIVE);
|
||||
hw->hp_sys[mode].regulator0.dbias_init = dbias_init;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_lp_dbias_voltage(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t dbias_voltage)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_HP_ACTIVE);
|
||||
hw->hp_sys[mode].regulator0.lp_dbias_vol = dbias_voltage;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_hp_dbias_voltage(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t hp_dbias_vol)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_HP_ACTIVE);
|
||||
hw->hp_sys[mode].regulator0.hp_dbias_vol = hp_dbias_vol;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_sleep_memory_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool slp_xpd)
|
||||
{
|
||||
hw->hp_sys[mode].regulator0.slp_mem_xpd = slp_xpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool xpd)
|
||||
{
|
||||
hw->hp_sys[mode].regulator0.xpd = xpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_sleep_logic_dbias(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t slp_dbias)
|
||||
{
|
||||
hw->hp_sys[mode].regulator0.slp_logic_dbias = slp_dbias;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_sleep_memory_dbias(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t slp_dbias)
|
||||
{
|
||||
hw->hp_sys[mode].regulator0.slp_mem_dbias = slp_dbias;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_dbias(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t dbias)
|
||||
{
|
||||
hw->hp_sys[mode].regulator0.dbias = dbias;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_driver_bar(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t drv_b)
|
||||
{
|
||||
hw->hp_sys[mode].regulator1.drv_b = drv_b;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_regulator_slp_xpd(pmu_dev_t *hw, pmu_lp_mode_t mode, bool slp_xpd)
|
||||
{
|
||||
hw->lp_sys[mode].regulator0.slp_xpd = slp_xpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_regulator_xpd(pmu_dev_t *hw, pmu_lp_mode_t mode, bool xpd)
|
||||
{
|
||||
hw->lp_sys[mode].regulator0.xpd = xpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_regulator_sleep_dbias(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t slp_dbias)
|
||||
{
|
||||
hw->lp_sys[mode].regulator0.slp_dbias = slp_dbias;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_regulator_dbias(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t dbias)
|
||||
{
|
||||
hw->lp_sys[mode].regulator0.dbias = dbias;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_regulator_driver_bar(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t drv_b)
|
||||
{
|
||||
hw->lp_sys[mode].regulator1.drv_b = drv_b;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_xtal_xpd(pmu_dev_t *hw, pmu_lp_mode_t mode, bool xpd_xtal)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
|
||||
hw->lp_sys[mode].xtal.xpd_xtal = xpd_xtal;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_xtalx2_xpd(pmu_dev_t *hw, pmu_lp_mode_t mode, bool xpd_xtalx2)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
|
||||
hw->lp_sys[mode].xtal.xpd_xtalx2 = xpd_xtalx2;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_dig_power(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t flag)
|
||||
{
|
||||
hw->lp_sys[mode].dig_power.val = flag;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_clk_power(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t xpd_flag)
|
||||
{
|
||||
hw->lp_sys[mode].clk_power.val = xpd_flag;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_clk_power(pmu_dev_t *hw, pmu_lp_mode_t mode)
|
||||
{
|
||||
return hw->lp_sys[mode].clk_power.val;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_dcdc_ccm_enable(pmu_dev_t *hw, pmu_lp_mode_t mode, bool enable)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
|
||||
hw->lp_sys[mode].bias.dcdc_ccm_enb = enable;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_dcdc_clear_ready(pmu_dev_t *hw, pmu_lp_mode_t mode, bool clear_rdy)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
|
||||
hw->lp_sys[mode].bias.dcdc_clear_rdy = clear_rdy;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_dig_reg_dpcur_bias(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t dpcur_bias)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
|
||||
hw->lp_sys[mode].bias.dig_reg_dpcur_bias = dpcur_bias;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_dig_reg_dsfmos(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t value)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
|
||||
hw->lp_sys[mode].bias.dig_reg_dsfmos = value;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_dcm_vset(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t value)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
|
||||
hw->lp_sys[mode].bias.dcm_vset = value;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_dcm_mode(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t dcm_mode)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
|
||||
hw->lp_sys[mode].bias.dcm_mode = dcm_mode;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_bias_xpd(pmu_dev_t *hw, pmu_lp_mode_t mode, bool xpd_bias)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
|
||||
hw->lp_sys[mode].bias.xpd_bias = xpd_bias;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_discnnt_dig_rtc(pmu_dev_t *hw, pmu_lp_mode_t mode, bool discnnt)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
|
||||
hw->lp_sys[mode].bias.discnnt_dig_rtc = discnnt;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_current_power_off(pmu_dev_t *hw, pmu_lp_mode_t mode, bool off)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
|
||||
hw->lp_sys[mode].bias.pd_cur = off;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_bias_sleep_enable(pmu_dev_t *hw, pmu_lp_mode_t mode, bool en)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
|
||||
hw->lp_sys[mode].bias.bias_sleep = en;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_set_clk_power(pmu_dev_t *hw, uint32_t flag)
|
||||
{
|
||||
hw->imm.clk_power.val = flag;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_set_icg_slp_sel(pmu_dev_t *hw, bool slp_sel)
|
||||
{
|
||||
if (slp_sel) {
|
||||
hw->imm.sleep_sysclk.tie_high_icg_slp_sel = 1;
|
||||
} else {
|
||||
hw->imm.sleep_sysclk.tie_low_icg_slp_sel = 1;
|
||||
}
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_update_dig_sysclk_sel(pmu_dev_t *hw, bool update)
|
||||
{
|
||||
hw->imm.sleep_sysclk.update_dig_sysclk_sel = update;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_update_dig_icg_switch(pmu_dev_t *hw, bool update)
|
||||
{
|
||||
hw->imm.sleep_sysclk.update_dig_icg_switch = update;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_update_dig_icg_func(pmu_dev_t *hw, bool icg_func_update)
|
||||
{
|
||||
hw->imm.hp_func_icg.update_dig_icg_func_en = icg_func_update;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_update_dig_icg_apb(pmu_dev_t *hw, bool icg_apb_update)
|
||||
{
|
||||
hw->imm.hp_apb_icg.update_dig_icg_apb_en = icg_apb_update;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_update_dig_icg_modem_code(pmu_dev_t *hw, bool icg_modem_update)
|
||||
{
|
||||
hw->imm.modem_icg.update_dig_icg_modem_en = icg_modem_update;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_set_lp_rootclk_sel(pmu_dev_t *hw, bool rootclk_sel)
|
||||
{
|
||||
if (rootclk_sel) {
|
||||
hw->imm.lp_icg.tie_high_lp_rootclk_sel = 1;
|
||||
} else {
|
||||
hw->imm.lp_icg.tie_low_lp_rootclk_sel = 1;
|
||||
}
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_set_hp_pad_hold_all(pmu_dev_t *hw, bool hold_all)
|
||||
{
|
||||
if (hold_all) {
|
||||
hw->imm.pad_hold_all.tie_high_hp_pad_hold_all = 1;
|
||||
} else {
|
||||
hw->imm.pad_hold_all.tie_low_hp_pad_hold_all = 1;
|
||||
}
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_set_lp_pad_hold_all(pmu_dev_t *hw, bool hold_all)
|
||||
{
|
||||
if (hold_all) {
|
||||
hw->imm.pad_hold_all.tie_high_lp_pad_hold_all = 1;
|
||||
} else {
|
||||
hw->imm.pad_hold_all.tie_low_lp_pad_hold_all = 1;
|
||||
}
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_reset(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool rst)
|
||||
{
|
||||
hw->power.hp_pd[domain].force_reset = rst;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_isolate(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool iso)
|
||||
{
|
||||
hw->power.hp_pd[domain].force_iso = iso;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_power_up(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool fpu)
|
||||
{
|
||||
hw->power.hp_pd[domain].force_pu = fpu;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_no_reset(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool no_rst)
|
||||
{
|
||||
hw->power.hp_pd[domain].force_no_reset = no_rst;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_no_isolate(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool no_iso)
|
||||
{
|
||||
hw->power.hp_pd[domain].force_no_iso = no_iso;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_power_down(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool fpd)
|
||||
{
|
||||
hw->power.hp_pd[domain].force_pd = fpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_reset(pmu_dev_t *hw, bool rst)
|
||||
{
|
||||
hw->power.lp_peri.force_reset = rst;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_isolate(pmu_dev_t *hw, bool iso)
|
||||
{
|
||||
hw->power.lp_peri.force_iso = iso;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_power_up(pmu_dev_t *hw, bool fpu)
|
||||
{
|
||||
hw->power.lp_peri.force_pu = fpu;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_no_reset(pmu_dev_t *hw, bool no_rst)
|
||||
{
|
||||
hw->power.lp_peri.force_no_reset = no_rst;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_no_isolate(pmu_dev_t *hw, bool no_iso)
|
||||
{
|
||||
hw->power.lp_peri.force_no_iso = no_iso;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_power_down(pmu_dev_t *hw, bool fpd)
|
||||
{
|
||||
hw->power.lp_peri.force_pd = fpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_memory_isolate(pmu_dev_t *hw, uint32_t iso)
|
||||
{
|
||||
hw->power.mem_cntl.force_hp_mem_iso = iso;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_memory_power_down(pmu_dev_t *hw, uint32_t fpd)
|
||||
{
|
||||
hw->power.mem_cntl.force_hp_mem_pd = fpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_memory_no_isolate(pmu_dev_t *hw, uint32_t no_iso)
|
||||
{
|
||||
hw->power.mem_cntl.force_hp_mem_no_iso = no_iso;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_memory_power_up(pmu_dev_t *hw, uint32_t fpu)
|
||||
{
|
||||
hw->power.mem_cntl.force_hp_mem_pu = fpu;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_memory_power_on_mask(pmu_dev_t *hw, uint32_t mem_mask)
|
||||
{
|
||||
hw->power.mem_mask.mem0_mask = mem_mask & BIT(0);
|
||||
hw->power.mem_mask.mem1_mask = mem_mask & BIT(1);
|
||||
hw->power.mem_mask.mem2_mask = mem_mask & BIT(2);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_memory_power_off_mask(pmu_dev_t *hw, uint32_t mem0_pd_mask, uint32_t mem1_pd_mask, uint32_t mem2_pd_mask)
|
||||
{
|
||||
hw->power.mem_mask.mem0_pd_mask = mem0_pd_mask;
|
||||
hw->power.mem_mask.mem1_pd_mask = mem1_pd_mask;
|
||||
hw->power.mem_mask.mem2_pd_mask = mem2_pd_mask;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_enable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->wakeup.cntl0.sleep_req = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_reject_enable(pmu_dev_t *hw, uint32_t reject)
|
||||
{
|
||||
hw->wakeup.cntl1.sleep_reject_ena = reject;
|
||||
hw->wakeup.cntl1.slp_reject_en = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_reject_disable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->wakeup.cntl1.slp_reject_en = 0;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_wakeup_enable(pmu_dev_t *hw, uint32_t wakeup)
|
||||
{
|
||||
hw->wakeup.cntl2 = wakeup;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_protect_mode(pmu_dev_t *hw, int mode)
|
||||
{
|
||||
hw->wakeup.cntl3.sleep_prt_sel = mode;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_min_sleep_cycle(pmu_dev_t *hw, uint32_t slow_clk_cycle)
|
||||
{
|
||||
hw->wakeup.cntl3.hp_min_slp_val = slow_clk_cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_clear_reject_cause(pmu_dev_t *hw)
|
||||
{
|
||||
hw->wakeup.cntl4.slp_reject_cause_clr = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR bool pmu_ll_hp_is_sleep_wakeup(pmu_dev_t *hw)
|
||||
{
|
||||
return (hw->hp_ext.int_raw.soc_wakeup == 1);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR bool pmu_ll_hp_is_sleep_reject(pmu_dev_t *hw)
|
||||
{
|
||||
return (hw->hp_ext.int_raw.soc_sleep_reject == 1);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_clear_sw_intr_status(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_ext.int_clr.sw = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_clear_wakeup_intr_status(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_ext.int_clr.soc_wakeup = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_clear_reject_intr_status(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_ext.int_clr.soc_sleep_reject = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_wakeup_cause(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->wakeup.status0.val;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_reject_cause(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->wakeup.status1.val;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_min_sleep_cycle(pmu_dev_t *hw, uint32_t slow_clk_cycle)
|
||||
{
|
||||
hw->wakeup.cntl3.lp_min_slp_val = slow_clk_cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_modify_icg_cntl_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
hw->hp_ext.clk_cntl.modify_icg_cntl_wait = cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_modify_icg_cntl_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->hp_ext.clk_cntl.modify_icg_cntl_wait;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_switch_icg_cntl_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
hw->hp_ext.clk_cntl.switch_icg_cntl_wait = cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_switch_icg_cntl_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->hp_ext.clk_cntl.switch_icg_cntl_wait;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_digital_power_down_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
hw->power.wait_timer0.hp_powerdown_timer = cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_digital_power_down_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->power.wait_timer0.hp_powerdown_timer;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_digital_power_down_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
hw->power.wait_timer1.lp_powerdown_timer = cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_digital_power_down_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->power.wait_timer1.lp_powerdown_timer;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_analog_wait_target_cycle(pmu_dev_t *hw, uint32_t slow_clk_cycle)
|
||||
{
|
||||
hw->wakeup.cntl5.lp_ana_wait_target = slow_clk_cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_analog_wait_target_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->wakeup.cntl5.lp_ana_wait_target;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_set_modem_wait_target_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
hw->wakeup.cntl5.modem_wait_target = cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_get_modem_wait_target_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->wakeup.cntl5.modem_wait_target;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_set_xtal_stable_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
hw->power.clk_wait.wait_xtal_stable = cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_get_xtal_stable_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->power.clk_wait.wait_xtal_stable;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_set_pll_stable_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
hw->power.clk_wait.wait_pll_stable = cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_get_pll_stable_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->power.clk_wait.wait_pll_stable;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_digital_power_supply_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
hw->power.wait_timer1.lp_wait_timer = cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_digital_power_supply_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->power.wait_timer1.lp_wait_timer;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_digital_power_up_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
hw->power.wait_timer1.lp_powerup_timer = cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_digital_power_up_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->power.wait_timer1.lp_powerup_timer;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_isolate_wait_cycle(pmu_dev_t *hw, uint32_t isolate_wait_cycle)
|
||||
{
|
||||
hw->power.wait_timer2.lp_iso_wait_timer = isolate_wait_cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_reset_wait_cycle(pmu_dev_t *hw, uint32_t reset_wait_cycle)
|
||||
{
|
||||
hw->power.wait_timer2.lp_rst_wait_timer = reset_wait_cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_isolate_wait_cycle(pmu_dev_t *hw, uint32_t isolate_wait_cycle)
|
||||
{
|
||||
hw->power.wait_timer2.hp_iso_wait_timer = isolate_wait_cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_reset_wait_cycle(pmu_dev_t *hw, uint32_t reset_wait_cycle)
|
||||
{
|
||||
hw->power.wait_timer2.hp_rst_wait_timer = reset_wait_cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_analog_wait_target_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
hw->wakeup.cntl7.ana_wait_target = cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_analog_wait_target_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->wakeup.cntl7.ana_wait_target;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_digital_power_supply_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
hw->power.wait_timer0.hp_wait_timer = cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_digital_power_supply_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->power.wait_timer0.hp_wait_timer;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_digital_power_up_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
hw->power.wait_timer0.hp_powerup_timer = cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_digital_power_up_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->power.wait_timer0.hp_powerup_timer;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_vddspi_ldo_set_sw_adjust(bool sw_enable, uint32_t vdd_flash_mode)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(PMU.power.flash_ldo[vdd_flash_mode], sw_en_xpd, sw_enable);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(PMU.power.flash_ldo[vdd_flash_mode], sw_en_power_adjust, sw_enable);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_vddspi_ldo_set_sw_adjust_value(uint32_t value, uint32_t vdd_flash_mode)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(PMU.power.flash_ldo[vdd_flash_mode], power_adjust, value);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_vddio_ldo_set_sw_adjust(bool sw_enable)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(PMU.power.io_ldo, sw_en_xpd, sw_enable);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(PMU.power.io_ldo, sw_en_power_adjust, sw_enable);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_vddio_ldo_set_sw_adjust_value(uint32_t value)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(PMU.power.io_ldo, power_adjust, value);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_get_sysclk_sleep_select_state(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->clk_state0.sysclk_slp_sel_state;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_set_dcdc_ccm_sw_en(pmu_dev_t *hw, bool en)
|
||||
{
|
||||
hw->dcm_ctrl.dcdc_ccm_sw_en = en;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,82 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The HAL layer for PMU (ESP32-H4 specific part)
|
||||
|
||||
#include "soc/soc.h"
|
||||
#include "esp_attr.h"
|
||||
#include "hal/pmu_hal.h"
|
||||
#include "hal/pmu_types.h"
|
||||
|
||||
void pmu_hal_hp_set_digital_power_up_wait_cycle(pmu_hal_context_t *hal, uint32_t power_supply_wait_cycle, uint32_t power_up_wait_cycle)
|
||||
{
|
||||
pmu_ll_hp_set_digital_power_supply_wait_cycle(hal->dev, power_supply_wait_cycle);
|
||||
pmu_ll_hp_set_digital_power_up_wait_cycle(hal->dev, power_up_wait_cycle);
|
||||
}
|
||||
|
||||
uint32_t pmu_hal_hp_get_digital_power_up_wait_cycle(pmu_hal_context_t *hal)
|
||||
{
|
||||
uint32_t power_supply_wait_cycle = pmu_ll_hp_get_digital_power_supply_wait_cycle(hal->dev);
|
||||
uint32_t power_up_wait_cycle = pmu_ll_hp_get_digital_power_up_wait_cycle(hal->dev);
|
||||
return power_supply_wait_cycle + power_up_wait_cycle;
|
||||
}
|
||||
|
||||
void pmu_hal_lp_set_digital_power_up_wait_cycle(pmu_hal_context_t *hal, uint32_t power_supply_wait_cycle, uint32_t power_up_wait_cycle)
|
||||
{
|
||||
pmu_ll_lp_set_digital_power_supply_wait_cycle(hal->dev, power_supply_wait_cycle);
|
||||
pmu_ll_lp_set_digital_power_up_wait_cycle(hal->dev, power_up_wait_cycle);
|
||||
}
|
||||
|
||||
uint32_t pmu_hal_lp_get_digital_power_up_wait_cycle(pmu_hal_context_t *hal)
|
||||
{
|
||||
uint32_t power_supply_wait_cycle = pmu_ll_lp_get_digital_power_supply_wait_cycle(hal->dev);
|
||||
uint32_t power_up_wait_cycle = pmu_ll_lp_get_digital_power_up_wait_cycle(hal->dev);
|
||||
return power_supply_wait_cycle + power_up_wait_cycle;
|
||||
}
|
||||
|
||||
void pmu_hal_hp_set_control_ready_wait_cycle(pmu_hal_context_t *hal, uint32_t isolate_wait_cycle, uint32_t reset_wait_cycle)
|
||||
{
|
||||
pmu_ll_hp_set_isolate_wait_cycle(hal->dev, isolate_wait_cycle);
|
||||
pmu_ll_hp_set_reset_wait_cycle(hal->dev, reset_wait_cycle);
|
||||
}
|
||||
|
||||
void pmu_hal_lp_set_control_ready_wait_cycle(pmu_hal_context_t *hal, uint32_t isolate_wait_cycle, uint32_t reset_wait_cycle)
|
||||
{
|
||||
pmu_ll_lp_set_isolate_wait_cycle(hal->dev, isolate_wait_cycle);
|
||||
pmu_ll_lp_set_reset_wait_cycle(hal->dev, reset_wait_cycle);
|
||||
}
|
||||
|
||||
void pmu_hal_hp_set_sleep_active_backup_enable(pmu_hal_context_t *hal)
|
||||
{
|
||||
pmu_ll_hp_set_active_to_sleep_backup_enable(hal->dev);
|
||||
pmu_ll_hp_set_sleep_to_active_backup_enable(hal->dev);
|
||||
}
|
||||
|
||||
void pmu_hal_hp_set_sleep_active_backup_disable(pmu_hal_context_t *hal)
|
||||
{
|
||||
pmu_ll_hp_set_sleep_to_active_backup_disable(hal->dev);
|
||||
pmu_ll_hp_set_active_to_sleep_backup_disable(hal->dev);
|
||||
}
|
||||
|
||||
void pmu_hal_hp_set_sleep_modem_backup_enable(pmu_hal_context_t *hal)
|
||||
{
|
||||
pmu_ll_hp_set_sleep_to_modem_backup_enable(hal->dev);
|
||||
}
|
||||
|
||||
void pmu_hal_hp_set_sleep_modem_backup_disable(pmu_hal_context_t *hal)
|
||||
{
|
||||
pmu_ll_hp_set_sleep_to_modem_backup_disable(hal->dev);
|
||||
}
|
||||
|
||||
void pmu_hal_hp_set_modem_active_backup_enable(pmu_hal_context_t *hal)
|
||||
{
|
||||
pmu_ll_hp_set_modem_to_active_backup_enable(hal->dev);
|
||||
}
|
||||
|
||||
void pmu_hal_hp_set_modem_active_backup_disable(pmu_hal_context_t *hal)
|
||||
{
|
||||
pmu_ll_hp_set_modem_to_active_backup_disable(hal->dev);
|
||||
}
|
||||
@@ -0,0 +1,45 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The HAL layer for PMU
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "soc/soc_caps.h"
|
||||
#include "hal/pmu_ll.h"
|
||||
#include "hal/pmu_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef struct {
|
||||
pmu_dev_t *dev;
|
||||
} pmu_hal_context_t;
|
||||
|
||||
void pmu_hal_hp_set_digital_power_up_wait_cycle(pmu_hal_context_t *hal, uint32_t power_supply_wait_cycle, uint32_t power_up_wait_cycle);
|
||||
|
||||
uint32_t pmu_hal_hp_get_digital_power_up_wait_cycle(pmu_hal_context_t *hal);
|
||||
|
||||
void pmu_hal_lp_set_digital_power_up_wait_cycle(pmu_hal_context_t *hal, uint32_t power_supply_wait_cycle, uint32_t power_up_wait_cycle);
|
||||
|
||||
uint32_t pmu_hal_lp_get_digital_power_up_wait_cycle(pmu_hal_context_t *hal);
|
||||
|
||||
void pmu_hal_hp_set_sleep_active_backup_enable(pmu_hal_context_t *hal);
|
||||
|
||||
void pmu_hal_hp_set_sleep_active_backup_disable(pmu_hal_context_t *hal);
|
||||
|
||||
void pmu_hal_hp_set_sleep_modem_backup_enable(pmu_hal_context_t *hal);
|
||||
|
||||
void pmu_hal_hp_set_sleep_modem_backup_disable(pmu_hal_context_t *hal);
|
||||
|
||||
void pmu_hal_hp_set_modem_active_backup_enable(pmu_hal_context_t *hal);
|
||||
|
||||
void pmu_hal_hp_set_modem_active_backup_disable(pmu_hal_context_t *hal);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,789 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The LL layer for ESP32-P4 PMU register operations
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <stdbool.h>
|
||||
#include "soc/soc.h"
|
||||
#include "esp_attr.h"
|
||||
#include "hal/assert.h"
|
||||
#include "soc/pmu_struct.h"
|
||||
#include "hal/pmu_types.h"
|
||||
#include "hal/misc.h"
|
||||
#include "hal/config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_interrupt_raw(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->lp_ext.int_raw.val;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_clear_intsts_mask(pmu_dev_t *hw, uint32_t mask)
|
||||
{
|
||||
hw->lp_ext.int_clr.val = mask;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_clear_sw_intr_status(pmu_dev_t *hw)
|
||||
{
|
||||
hw->lp_ext.int_clr.hp_sw_trigger = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_enable_sw_intr(pmu_dev_t *hw, bool enable)
|
||||
{
|
||||
hw->lp_ext.int_ena.hp_sw_trigger = enable;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_dig_power(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t flag)
|
||||
{
|
||||
hw->hp_sys[mode].dig_power.val = flag;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_func(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t icg_func)
|
||||
{
|
||||
hw->hp_sys[mode].icg_func = icg_func;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_apb(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t bitmap)
|
||||
{
|
||||
hw->hp_sys[mode].icg_apb = bitmap;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_power_detect_bypass_enable(pmu_dev_t *hw, pmu_hp_mode_t mode, bool bypass_en)
|
||||
{
|
||||
hw->hp_sys[mode].syscntl.power_det_bypass = bypass_en;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_uart_wakeup_enable(pmu_dev_t *hw, pmu_hp_mode_t mode, bool wakeup_en)
|
||||
{
|
||||
hw->hp_sys[mode].syscntl.uart_wakeup_en = wakeup_en;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_hold_all_lp_pad(pmu_dev_t *hw, pmu_hp_mode_t mode, bool hold_all)
|
||||
{
|
||||
hw->hp_sys[mode].syscntl.lp_pad_hold_all = hold_all;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_hold_all_hp_pad(pmu_dev_t *hw, pmu_hp_mode_t mode, bool hold_all)
|
||||
{
|
||||
hw->hp_sys[mode].syscntl.hp_pad_hold_all = hold_all;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_dig_pad_slp_sel(pmu_dev_t *hw, pmu_hp_mode_t mode, bool slp_sel)
|
||||
{
|
||||
hw->hp_sys[mode].syscntl.dig_pad_slp_sel = slp_sel;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_pause_watchdog(pmu_dev_t *hw, pmu_hp_mode_t mode, bool pause_wdt)
|
||||
{
|
||||
hw->hp_sys[mode].syscntl.dig_pause_wdt = pause_wdt;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_cpu_stall(pmu_dev_t *hw, pmu_hp_mode_t mode, bool cpu_stall)
|
||||
{
|
||||
hw->hp_sys[mode].syscntl.dig_cpu_stall = cpu_stall;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the power domain that needs to be powered down in the clock power
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param mode The pmu mode
|
||||
* @param flag Clock power domain flag
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_clk_power(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t xpd_flag)
|
||||
{
|
||||
hw->hp_sys[mode].clk_power.val = xpd_flag;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_xtal_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool xpd_xtal)
|
||||
{
|
||||
hw->hp_sys[mode].xtal.xpd_xtal = xpd_xtal;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_dcm_mode(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t dcm_mode)
|
||||
{
|
||||
hw->hp_sys[mode].bias.dcm_mode = dcm_mode;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_dcm_vset(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t dcm_vset)
|
||||
{
|
||||
hw->hp_sys[mode].bias.dcm_vset = dcm_vset;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_bias_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool xpd_bias)
|
||||
{
|
||||
hw->hp_sys[mode].bias.xpd_bias = xpd_bias;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_dbg_atten(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t value)
|
||||
{
|
||||
hw->hp_sys[mode].bias.dbg_atten = value;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_current_power_off(pmu_dev_t *hw, pmu_hp_mode_t mode, bool off)
|
||||
{
|
||||
hw->hp_sys[mode].bias.pd_cur = off;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_bias_sleep_enable(pmu_dev_t *hw, pmu_hp_mode_t mode, bool en)
|
||||
{
|
||||
hw->hp_sys[mode].bias.bias_sleep = en;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_retention_param(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t param)
|
||||
{
|
||||
hw->hp_sys[mode].backup.val = param;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_to_active_backup_enable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_sys[PMU_MODE_HP_ACTIVE].backup.hp_sleep2active_backup_en = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_to_active_backup_disable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_sys[PMU_MODE_HP_ACTIVE].backup.hp_sleep2active_backup_en = 0;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_active_to_sleep_backup_enable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_sys[PMU_MODE_HP_SLEEP].backup.hp_active2sleep_backup_en = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_active_to_sleep_backup_disable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_sys[PMU_MODE_HP_SLEEP].backup.hp_active2sleep_backup_en = 0;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_backup_icg_func(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t icg_func)
|
||||
{
|
||||
hw->hp_sys[mode].backup_clk = icg_func;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_sysclk_nodiv(pmu_dev_t *hw, pmu_hp_mode_t mode, bool sysclk_nodiv)
|
||||
{
|
||||
hw->hp_sys[mode].sysclk.dig_sysclk_nodiv = sysclk_nodiv;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_sysclk_enable(pmu_dev_t *hw, pmu_hp_mode_t mode, bool icg_sysclk_en)
|
||||
{
|
||||
hw->hp_sys[mode].sysclk.icg_sysclk_en = icg_sysclk_en;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_sysclk_slp_sel(pmu_dev_t *hw, pmu_hp_mode_t mode, bool slp_sel)
|
||||
{
|
||||
hw->hp_sys[mode].sysclk.sysclk_slp_sel = slp_sel;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_sysclk_slp_sel(pmu_dev_t *hw, pmu_hp_mode_t mode, bool slp_sel)
|
||||
{
|
||||
hw->hp_sys[mode].sysclk.icg_slp_sel = slp_sel;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_dig_sysclk(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t sysclk_sel)
|
||||
{
|
||||
hw->hp_sys[mode].sysclk.dig_sysclk_sel = sysclk_sel;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_sleep_logic_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool slp_xpd)
|
||||
{
|
||||
hw->hp_sys[mode].regulator0.slp_logic_xpd = slp_xpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_sleep_memory_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool slp_xpd)
|
||||
{
|
||||
hw->hp_sys[mode].regulator0.slp_mem_xpd = slp_xpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool xpd)
|
||||
{
|
||||
hw->hp_sys[mode].regulator0.xpd = xpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_sleep_logic_dbias(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t slp_dbias)
|
||||
{
|
||||
hw->hp_sys[mode].regulator0.slp_logic_dbias = slp_dbias;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_enable_sleep_flash_ldo_channel(pmu_dev_t *hw, bool enable)
|
||||
{
|
||||
// slp_mem_dbias[3] is used to control the volt output of VO1 for chip_revision >= 100,
|
||||
// and this field is not used for chip_revision < 100.
|
||||
hw->hp_sys[PMU_MODE_HP_SLEEP].regulator0.xpd_0p1a = (enable ? 8 : 0);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_dbias(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t dbias)
|
||||
{
|
||||
hw->hp_sys[mode].regulator0.dbias = dbias;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_driver_bar(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t drv_b)
|
||||
{
|
||||
hw->hp_sys[mode].regulator1.drv_b = drv_b;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_regulator_slp_xpd(pmu_dev_t *hw, pmu_lp_mode_t mode, bool slp_xpd)
|
||||
{
|
||||
hw->lp_sys[mode].regulator0.slp_xpd = slp_xpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_regulator_xpd(pmu_dev_t *hw, pmu_lp_mode_t mode, bool xpd)
|
||||
{
|
||||
hw->lp_sys[mode].regulator0.xpd = xpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_regulator_sleep_dbias(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t slp_dbias)
|
||||
{
|
||||
hw->lp_sys[mode].regulator0.slp_dbias = slp_dbias;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_regulator_dbias(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t dbias)
|
||||
{
|
||||
hw->lp_sys[mode].regulator0.dbias = dbias;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_regulator_driver_bar(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t drv_b)
|
||||
{
|
||||
hw->lp_sys[mode].regulator1.drv_b = drv_b;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_xtal_xpd(pmu_dev_t *hw, pmu_lp_mode_t mode, bool xpd_xtal)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
|
||||
hw->lp_sys[mode].xtal.xpd_xtal = xpd_xtal;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_dig_power(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t flag)
|
||||
{
|
||||
hw->lp_sys[mode].dig_power.val = flag;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_clk_power(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t xpd_flag)
|
||||
{
|
||||
hw->lp_sys[mode].clk_power.val = xpd_flag;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_clk_power(pmu_dev_t *hw, pmu_lp_mode_t mode)
|
||||
{
|
||||
return hw->lp_sys[mode].clk_power.val;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_bias_xpd(pmu_dev_t *hw, pmu_lp_mode_t mode, bool xpd_bias)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
|
||||
hw->lp_sys[mode].bias.xpd_bias = xpd_bias;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_dbg_atten(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t value)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
|
||||
hw->lp_sys[mode].bias.dbg_atten = value;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_current_power_off(pmu_dev_t *hw, pmu_lp_mode_t mode, bool off)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
|
||||
hw->lp_sys[mode].bias.pd_cur = off;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_bias_sleep_enable(pmu_dev_t *hw, pmu_lp_mode_t mode, bool en)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
|
||||
hw->lp_sys[mode].bias.bias_sleep = en;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_set_clk_power(pmu_dev_t *hw, uint32_t flag)
|
||||
{
|
||||
hw->imm.clk_power.val = flag;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_set_icg_slp_sel(pmu_dev_t *hw, bool slp_sel)
|
||||
{
|
||||
if (slp_sel) {
|
||||
hw->imm.sleep_sysclk.tie_high_icg_slp_sel = 1;
|
||||
} else {
|
||||
hw->imm.sleep_sysclk.tie_low_icg_slp_sel = 1;
|
||||
}
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_update_dig_sysclk_sel(pmu_dev_t *hw, bool update)
|
||||
{
|
||||
hw->imm.sleep_sysclk.update_dig_sysclk_sel = update;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_update_dig_icg_switch(pmu_dev_t *hw, bool update)
|
||||
{
|
||||
hw->imm.sleep_sysclk.update_dig_icg_switch = update;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_update_dig_icg_func(pmu_dev_t *hw, bool icg_func_update)
|
||||
{
|
||||
hw->imm.hp_func_icg.update_dig_icg_func_en = icg_func_update;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_update_dig_icg_apb(pmu_dev_t *hw, bool icg_apb_update)
|
||||
{
|
||||
hw->imm.hp_apb_icg.update_dig_icg_apb_en = icg_apb_update;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_set_lp_rootclk_sel(pmu_dev_t *hw, bool rootclk_sel)
|
||||
{
|
||||
if (rootclk_sel) {
|
||||
hw->imm.lp_icg.tie_high_lp_rootclk_sel = 1;
|
||||
} else {
|
||||
hw->imm.lp_icg.tie_low_lp_rootclk_sel = 1;
|
||||
}
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_set_pad_slp_sel(pmu_dev_t *hw, bool sleep_sel)
|
||||
{
|
||||
if (sleep_sel) {
|
||||
// Switch the pad configuration from active state to sleep state
|
||||
hw->imm.pad_hold_all.tie_high_pad_slp_sel = 1;
|
||||
} else {
|
||||
// Switch the pad configuration from sleep state to active state
|
||||
hw->imm.pad_hold_all.tie_low_pad_slp_sel = 1;
|
||||
}
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_set_hp_pad_hold_all(pmu_dev_t *hw, bool hold_all)
|
||||
{
|
||||
if (hold_all) {
|
||||
hw->imm.pad_hold_all.tie_high_hp_pad_hold_all = 1;
|
||||
} else {
|
||||
hw->imm.pad_hold_all.tie_low_hp_pad_hold_all = 1;
|
||||
}
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_set_lp_pad_hold_all(pmu_dev_t *hw, bool hold_all)
|
||||
{
|
||||
if (hold_all) {
|
||||
hw->imm.pad_hold_all.tie_high_lp_pad_hold_all = 1;
|
||||
} else {
|
||||
hw->imm.pad_hold_all.tie_low_lp_pad_hold_all = 1;
|
||||
}
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_reset(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool rst)
|
||||
{
|
||||
if (domain == PMU_HP_PD_CPU) {
|
||||
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
|
||||
hw->power_pd_hp_cpu_cntl.force_hp_cpu_reset = rst;
|
||||
#endif
|
||||
} else {
|
||||
hw->power.hp_pd[domain].force_reset = rst;
|
||||
}
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_isolate(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool iso)
|
||||
{
|
||||
if (domain == PMU_HP_PD_CPU) {
|
||||
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
|
||||
hw->power_pd_hp_cpu_cntl.force_hp_cpu_iso = iso;
|
||||
#endif
|
||||
} else {
|
||||
hw->power.hp_pd[domain].force_iso = iso;
|
||||
}
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_power_up(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool fpu)
|
||||
{
|
||||
if (domain == PMU_HP_PD_CPU) {
|
||||
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
|
||||
hw->power_pd_hp_cpu_cntl.force_hp_cpu_pu = fpu;
|
||||
#endif
|
||||
} else {
|
||||
hw->power.hp_pd[domain].force_pu = fpu;
|
||||
}
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_no_reset(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool no_rst)
|
||||
{
|
||||
if (domain == PMU_HP_PD_CPU) {
|
||||
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
|
||||
hw->power_pd_hp_cpu_cntl.force_hp_cpu_no_reset = no_rst;
|
||||
#endif
|
||||
} else {
|
||||
hw->power.hp_pd[domain].force_no_reset = no_rst;
|
||||
}
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_no_isolate(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool no_iso)
|
||||
{
|
||||
if (domain == PMU_HP_PD_CPU) {
|
||||
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
|
||||
hw->power_pd_hp_cpu_cntl.force_hp_cpu_no_iso = no_iso;
|
||||
#endif
|
||||
} else {
|
||||
hw->power.hp_pd[domain].force_no_iso = no_iso;
|
||||
}
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_power_down(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool fpd)
|
||||
{
|
||||
if (domain == PMU_HP_PD_CPU) {
|
||||
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
|
||||
hw->power_pd_hp_cpu_cntl.force_hp_cpu_pd = fpd;
|
||||
#endif
|
||||
} else {
|
||||
hw->power.hp_pd[domain].force_pd = fpd;
|
||||
}
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_reset(pmu_dev_t *hw, bool rst)
|
||||
{
|
||||
hw->power.lp_peri.force_reset = rst;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_isolate(pmu_dev_t *hw, bool iso)
|
||||
{
|
||||
hw->power.lp_peri.force_iso = iso;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_power_up(pmu_dev_t *hw, bool fpu)
|
||||
{
|
||||
hw->power.lp_peri.force_pu = fpu;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_no_reset(pmu_dev_t *hw, bool no_rst)
|
||||
{
|
||||
hw->power.lp_peri.force_no_reset = no_rst;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_no_isolate(pmu_dev_t *hw, bool no_iso)
|
||||
{
|
||||
hw->power.lp_peri.force_no_iso = no_iso;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_power_down(pmu_dev_t *hw, bool fpd)
|
||||
{
|
||||
hw->power.lp_peri.force_pd = fpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_memory_isolate(pmu_dev_t *hw, uint32_t iso)
|
||||
{
|
||||
hw->power.hp_pd[PMU_HP_PD_HPMEM].force_iso = iso;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_memory_power_down(pmu_dev_t *hw, uint32_t fpd)
|
||||
{
|
||||
hw->power.hp_pd[PMU_HP_PD_HPMEM].force_pd = fpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_memory_no_isolate(pmu_dev_t *hw, uint32_t no_iso)
|
||||
{
|
||||
hw->power.hp_pd[PMU_HP_PD_HPMEM].force_no_iso = no_iso;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_memory_power_up(pmu_dev_t *hw, uint32_t fpu)
|
||||
{
|
||||
hw->power.hp_pd[PMU_HP_PD_HPMEM].force_pu = fpu;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_enable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->wakeup.cntl0.sleep_req = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_reject_enable(pmu_dev_t *hw, uint32_t reject)
|
||||
{
|
||||
hw->wakeup.cntl1.sleep_reject_ena = reject;
|
||||
hw->wakeup.cntl1.slp_reject_en = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_reject_disable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->wakeup.cntl1.slp_reject_en = 0;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_wakeup_enable(pmu_dev_t *hw, uint32_t wakeup)
|
||||
{
|
||||
hw->wakeup.cntl2.wakeup_ena = wakeup;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_protect_mode(pmu_dev_t *hw, int mode)
|
||||
{
|
||||
hw->wakeup.cntl3.sleep_prt_sel = mode;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_min_sleep_cycle(pmu_dev_t *hw, uint32_t slow_clk_cycle)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wakeup.cntl3, hp_min_slp_val, slow_clk_cycle);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_clear_reject_cause(pmu_dev_t *hw)
|
||||
{
|
||||
hw->wakeup.cntl4.slp_reject_cause_clr = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_enable_sw_intr(pmu_dev_t *hw, bool enable)
|
||||
{
|
||||
hw->hp_ext.int_ena.sw = enable;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR bool pmu_ll_hp_is_sleep_wakeup(pmu_dev_t *hw)
|
||||
{
|
||||
return (hw->hp_ext.int_raw.wakeup == 1);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR bool pmu_ll_hp_is_sleep_reject(pmu_dev_t *hw)
|
||||
{
|
||||
return (hw->hp_ext.int_raw.reject == 1);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_trigger_sw_intr(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_lp_cpu_comm.lp_trigger_hp = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_trigger_sw_intr(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_lp_cpu_comm.hp_trigger_lp = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_clear_sw_intr_status(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_ext.int_clr.sw = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_clear_wakeup_intr_status(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_ext.int_clr.wakeup = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_clear_reject_intr_status(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_ext.int_clr.reject = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_wakeup_cause(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->wakeup.status0;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_reject_cause(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->wakeup.status1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_lite_wakeup_cause(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->wakeup.status2;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_min_sleep_cycle(pmu_dev_t *hw, uint32_t slow_clk_cycle)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wakeup.cntl3, lp_min_slp_val, slow_clk_cycle);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_modify_icg_cntl_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hp_ext.clk_cntl, modify_icg_cntl_wait, cycle);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_modify_icg_cntl_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return HAL_FORCE_READ_U32_REG_FIELD(hw->hp_ext.clk_cntl, modify_icg_cntl_wait);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_switch_icg_cntl_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hp_ext.clk_cntl, switch_icg_cntl_wait, cycle);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_switch_icg_cntl_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return HAL_FORCE_READ_U32_REG_FIELD(hw->hp_ext.clk_cntl, switch_icg_cntl_wait);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_digital_power_down_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
hw->power.wait_timer0.powerdown_timer = cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_digital_power_down_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->power.wait_timer0.powerdown_timer;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_digital_power_down_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
hw->power.wait_timer1.powerdown_timer = cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_digital_power_down_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->power.wait_timer1.powerdown_timer;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_analog_wait_target_cycle(pmu_dev_t *hw, uint32_t slow_clk_cycle)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wakeup.cntl5, lp_ana_wait_target, slow_clk_cycle);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_analog_wait_target_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return HAL_FORCE_READ_U32_REG_FIELD(hw->wakeup.cntl5, lp_ana_wait_target);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_set_xtal_stable_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->power.clk_wait, wait_xtal_stable, cycle);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_get_xtal_stable_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return HAL_FORCE_READ_U32_REG_FIELD(hw->power.clk_wait, wait_xtal_stable);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_set_pll_stable_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->power.clk_wait, wait_pll_stable, cycle);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_get_pll_stable_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return HAL_FORCE_READ_U32_REG_FIELD(hw->power.clk_wait, wait_pll_stable);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_digital_power_supply_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
hw->power.wait_timer1.wait_timer = cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_digital_power_supply_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->power.wait_timer1.wait_timer;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_digital_power_up_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
hw->power.wait_timer1.powerup_timer = cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_digital_power_up_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->power.wait_timer1.powerup_timer;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_analog_wait_target_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wakeup.cntl7, ana_wait_target, cycle);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_analog_wait_target_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return HAL_FORCE_READ_U32_REG_FIELD(hw->wakeup.cntl7, ana_wait_target);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_lite_wakeup_enable(pmu_dev_t *hw, bool wakeup_en)
|
||||
{
|
||||
hw->wakeup.cntl8.lp_lite_wakeup_ena = wakeup_en;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_digital_power_supply_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
hw->power.wait_timer0.wait_timer = cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_digital_power_supply_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->power.wait_timer0.wait_timer;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_digital_power_up_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
hw->power.wait_timer0.powerup_timer = cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_digital_power_up_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->power.wait_timer0.powerup_timer;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_set_dcdc_switch_force_power_up(pmu_dev_t *hw, bool fpu)
|
||||
{
|
||||
hw->power.dcdc_switch.force_pd = 0;
|
||||
hw->power.dcdc_switch.force_pu = fpu;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_set_dcdc_switch_force_power_down(pmu_dev_t *hw, bool fpd)
|
||||
{
|
||||
hw->power.dcdc_switch.force_pu = 0;
|
||||
hw->power.dcdc_switch.force_pd = fpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_set_dcdc_en(pmu_dev_t *hw, bool en)
|
||||
{
|
||||
if (en) {
|
||||
hw->dcm_ctrl.done_force = 0;
|
||||
hw->dcm_ctrl.on_req = 1;
|
||||
} else {
|
||||
hw->dcm_ctrl.off_req = 1;
|
||||
hw->dcm_ctrl.done_force = 1;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get ext1 wakeup source status
|
||||
* @return The lower 8 bits of the returned value are the bitmap of
|
||||
* the wakeup source status, bit 0~7 corresponds to LP_IO 0~7
|
||||
*/
|
||||
static inline uint32_t pmu_ll_ext1_get_wakeup_status(void)
|
||||
{
|
||||
return REG_GET_FIELD(PMU_EXT_WAKEUP_ST_REG, PMU_EXT_WAKEUP_STATUS);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear the ext1 wakeup source status
|
||||
*/
|
||||
static inline void pmu_ll_ext1_clear_wakeup_status(void)
|
||||
{
|
||||
REG_SET_BIT(PMU_EXT_WAKEUP_CNTL_REG, PMU_EXT_WAKEUP_STATUS_CLR);
|
||||
REG_CLR_BIT(PMU_EXT_WAKEUP_CNTL_REG, PMU_EXT_WAKEUP_STATUS_CLR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the wake-up LP_IO of the ext1 wake-up source
|
||||
* @param io_mask wakeup LP_IO bitmap, bit 0~7 corresponds to LP_IO 0~7
|
||||
* @param level_mask 0: Wake the chip when all selected GPIOs go low
|
||||
* 1: Wake the chip when any of the selected GPIOs go high
|
||||
*/
|
||||
static inline void pmu_ll_ext1_set_wakeup_pins(uint32_t io_mask, int level_mask)
|
||||
{
|
||||
REG_SET_FIELD(PMU_EXT_WAKEUP_SEL_REG, PMU_EXT_WAKEUP_SEL, io_mask);
|
||||
REG_SET_FIELD(PMU_EXT_WAKEUP_LV_REG, PMU_EXT_WAKEUP_LV, level_mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear all ext1 wakup-source setting
|
||||
*/
|
||||
static inline void pmu_ll_ext1_clear_wakeup_pins(void)
|
||||
{
|
||||
REG_SET_FIELD(PMU_EXT_WAKEUP_SEL_REG, PMU_EXT_WAKEUP_SEL, 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get ext1 wakeup source setting
|
||||
* @return The lower 8 bits of the returned value are the bitmap of
|
||||
* the wakeup source status, bit 0~7 corresponds to LP_IO 0~7
|
||||
*/
|
||||
static inline uint32_t pmu_ll_ext1_get_wakeup_pins(void)
|
||||
{
|
||||
return REG_GET_FIELD(PMU_EXT_WAKEUP_SEL_REG, PMU_EXT_WAKEUP_SEL);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,50 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The HAL layer for PMU (ESP32-P4 specific part)
|
||||
|
||||
#include "soc/soc.h"
|
||||
#include "esp_attr.h"
|
||||
#include "hal/pmu_hal.h"
|
||||
#include "hal/pmu_types.h"
|
||||
|
||||
void IRAM_ATTR pmu_hal_hp_set_digital_power_up_wait_cycle(pmu_hal_context_t *hal, uint32_t power_supply_wait_cycle, uint32_t power_up_wait_cycle)
|
||||
{
|
||||
pmu_ll_hp_set_digital_power_supply_wait_cycle(hal->dev, power_supply_wait_cycle);
|
||||
pmu_ll_hp_set_digital_power_up_wait_cycle(hal->dev, power_up_wait_cycle);
|
||||
}
|
||||
|
||||
uint32_t IRAM_ATTR pmu_hal_hp_get_digital_power_up_wait_cycle(pmu_hal_context_t *hal)
|
||||
{
|
||||
uint32_t power_supply_wait_cycle = pmu_ll_hp_get_digital_power_supply_wait_cycle(hal->dev);
|
||||
uint32_t power_up_wait_cycle = pmu_ll_hp_get_digital_power_up_wait_cycle(hal->dev);
|
||||
return power_supply_wait_cycle + power_up_wait_cycle;
|
||||
}
|
||||
|
||||
void IRAM_ATTR pmu_hal_lp_set_digital_power_up_wait_cycle(pmu_hal_context_t *hal, uint32_t power_supply_wait_cycle, uint32_t power_up_wait_cycle)
|
||||
{
|
||||
pmu_ll_lp_set_digital_power_supply_wait_cycle(hal->dev, power_supply_wait_cycle);
|
||||
pmu_ll_lp_set_digital_power_up_wait_cycle(hal->dev, power_up_wait_cycle);
|
||||
}
|
||||
|
||||
uint32_t IRAM_ATTR pmu_hal_lp_get_digital_power_up_wait_cycle(pmu_hal_context_t *hal)
|
||||
{
|
||||
uint32_t power_supply_wait_cycle = pmu_ll_lp_get_digital_power_supply_wait_cycle(hal->dev);
|
||||
uint32_t power_up_wait_cycle = pmu_ll_lp_get_digital_power_up_wait_cycle(hal->dev);
|
||||
return power_supply_wait_cycle + power_up_wait_cycle;
|
||||
}
|
||||
|
||||
void pmu_hal_hp_set_sleep_active_backup_enable(pmu_hal_context_t *hal)
|
||||
{
|
||||
pmu_ll_hp_set_active_to_sleep_backup_enable(hal->dev);
|
||||
pmu_ll_hp_set_sleep_to_active_backup_enable(hal->dev);
|
||||
}
|
||||
|
||||
void pmu_hal_hp_set_sleep_active_backup_disable(pmu_hal_context_t *hal)
|
||||
{
|
||||
pmu_ll_hp_set_sleep_to_active_backup_disable(hal->dev);
|
||||
pmu_ll_hp_set_active_to_sleep_backup_disable(hal->dev);
|
||||
}
|
||||
@@ -0,0 +1,103 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "soc/soc.h"
|
||||
#include "soc/rtc_cntl_reg.h"
|
||||
#include "esp_attr.h"
|
||||
#include "hal/assert.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
FORCE_INLINE_ATTR void rtc_cntl_ll_set_wakeup_timer(uint64_t t)
|
||||
{
|
||||
WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX);
|
||||
WRITE_PERI_REG(RTC_CNTL_SLP_TIMER1_REG, t >> 32);
|
||||
|
||||
SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG, RTC_CNTL_MAIN_TIMER_INT_CLR_M);
|
||||
SET_PERI_REG_MASK(RTC_CNTL_SLP_TIMER1_REG, RTC_CNTL_MAIN_TIMER_ALARM_EN_M);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void rtc_cntl_ll_ext1_clear_wakeup_status(void)
|
||||
{
|
||||
REG_SET_BIT(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_STATUS_CLR);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_ext1_get_wakeup_status(void)
|
||||
{
|
||||
return REG_GET_FIELD(RTC_CNTL_EXT_WAKEUP1_STATUS_REG, RTC_CNTL_EXT_WAKEUP1_STATUS);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void rtc_cntl_ll_ext1_set_wakeup_pins(uint32_t io_mask, uint32_t mode_mask)
|
||||
{
|
||||
// The target only supports a unified trigger mode among all EXT1 wakeup IOs
|
||||
HAL_ASSERT((io_mask & mode_mask) == io_mask || (io_mask & mode_mask) == 0);
|
||||
REG_SET_FIELD(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_SEL, io_mask);
|
||||
if ((io_mask & mode_mask) == io_mask) {
|
||||
SET_PERI_REG_BITS(RTC_CNTL_EXT_WAKEUP_CONF_REG, 0x1,
|
||||
1, RTC_CNTL_EXT_WAKEUP1_LV_S);
|
||||
} else {
|
||||
SET_PERI_REG_BITS(RTC_CNTL_EXT_WAKEUP_CONF_REG, 0x1,
|
||||
0, RTC_CNTL_EXT_WAKEUP1_LV_S);
|
||||
}
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void rtc_cntl_ll_ext1_clear_wakeup_pins(void)
|
||||
{
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_SEL_M);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_ext1_get_wakeup_pins(void)
|
||||
{
|
||||
return REG_GET_FIELD(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_SEL);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void rtc_cntl_ll_ulp_int_clear(void)
|
||||
{
|
||||
REG_SET_BIT(RTC_CNTL_INT_CLR_REG, RTC_CNTL_ULP_CP_INT_CLR);
|
||||
REG_SET_BIT(RTC_CNTL_INT_CLR_REG, RTC_CNTL_COCPU_INT_CLR);
|
||||
REG_SET_BIT(RTC_CNTL_INT_CLR_REG, RTC_CNTL_COCPU_TRAP_INT_CLR);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void rtc_cntl_ll_timer2_set_touch_wait_cycle(uint32_t wait_cycle)
|
||||
{
|
||||
REG_SET_FIELD(RTC_CNTL_TIMER2_REG, RTC_CNTL_ULPCP_TOUCH_START_WAIT, wait_cycle);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void rtc_cntl_ll_reset_system(void)
|
||||
{
|
||||
REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void rtc_cntl_ll_reset_cpu(int cpu_no)
|
||||
{
|
||||
REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_PROCPU_RST);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void rtc_cntl_ll_sleep_enable(void)
|
||||
{
|
||||
SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_SLEEP_EN);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_get_rtc_time(void)
|
||||
{
|
||||
SET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_UPDATE);
|
||||
uint64_t t = READ_PERI_REG(RTC_CNTL_TIME0_REG);
|
||||
t |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME1_REG)) << 32;
|
||||
return t;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_get_wakeup_cause(void)
|
||||
{
|
||||
return REG_GET_FIELD(RTC_CNTL_SLP_WAKEUP_CAUSE_REG, RTC_CNTL_WAKEUP_CAUSE);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,184 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "soc/soc.h"
|
||||
#include "soc/rtc_cntl_reg.h"
|
||||
#include "soc/syscon_reg.h"
|
||||
#include "esp_attr.h"
|
||||
#include "hal/assert.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define RTC_CNTL_LL_RETENTION_TARGET_CPU (BIT(0))
|
||||
#define RTC_CNTL_LL_RETENTION_TARGET_TAGMEM (BIT(1))
|
||||
|
||||
FORCE_INLINE_ATTR void rtc_cntl_ll_set_wakeup_timer(uint64_t t)
|
||||
{
|
||||
WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX);
|
||||
WRITE_PERI_REG(RTC_CNTL_SLP_TIMER1_REG, t >> 32);
|
||||
|
||||
SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG, RTC_CNTL_MAIN_TIMER_INT_CLR_M);
|
||||
SET_PERI_REG_MASK(RTC_CNTL_SLP_TIMER1_REG, RTC_CNTL_MAIN_TIMER_ALARM_EN_M);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void rtc_cntl_ll_ext1_clear_wakeup_status(void)
|
||||
{
|
||||
REG_SET_BIT(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_STATUS_CLR);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_ext1_get_wakeup_status(void)
|
||||
{
|
||||
return REG_GET_FIELD(RTC_CNTL_EXT_WAKEUP1_STATUS_REG, RTC_CNTL_EXT_WAKEUP1_STATUS);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void rtc_cntl_ll_ext1_set_wakeup_pins(uint32_t io_mask, uint32_t mode_mask)
|
||||
{
|
||||
// The target only supports a unified trigger mode among all EXT1 wakeup IOs
|
||||
HAL_ASSERT((io_mask & mode_mask) == io_mask || (io_mask & mode_mask) == 0);
|
||||
REG_SET_FIELD(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_SEL, io_mask);
|
||||
if ((io_mask & mode_mask) == io_mask) {
|
||||
SET_PERI_REG_BITS(RTC_CNTL_EXT_WAKEUP_CONF_REG, 0x1,
|
||||
1, RTC_CNTL_EXT_WAKEUP1_LV_S);
|
||||
} else {
|
||||
SET_PERI_REG_BITS(RTC_CNTL_EXT_WAKEUP_CONF_REG, 0x1,
|
||||
0, RTC_CNTL_EXT_WAKEUP1_LV_S);
|
||||
}
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void rtc_cntl_ll_ext1_clear_wakeup_pins(void)
|
||||
{
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_SEL_M);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_ext1_get_wakeup_pins(void)
|
||||
{
|
||||
return REG_GET_FIELD(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_SEL);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void rtc_cntl_ll_set_tagmem_retention_link_addr(uint32_t link_addr)
|
||||
{
|
||||
REG_SET_FIELD(SYSCON_RETENTION_CTRL1_REG, SYSCON_RETENTION_TAG_LINK_ADDR, link_addr);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void rtc_cntl_ll_enable_tagmem_retention(void)
|
||||
{
|
||||
/* Enable i/d-cache tagmem retenttion. cpu: 1, tagmem: 2, cpu + tagmem: 3 */
|
||||
uint32_t target = REG_GET_FIELD(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_TARGET);
|
||||
REG_SET_FIELD(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_TARGET, (target | RTC_CNTL_LL_RETENTION_TARGET_TAGMEM));
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void rtc_cntl_ll_enable_icache_tagmem_retention(uint32_t start_point, uint32_t vld_size, uint32_t size)
|
||||
{
|
||||
REG_SET_FIELD(SYSCON_RETENTION_CTRL2_REG, SYSCON_RET_ICACHE_START_POINT, start_point);
|
||||
REG_SET_FIELD(SYSCON_RETENTION_CTRL2_REG, SYSCON_RET_ICACHE_VLD_SIZE, vld_size);
|
||||
REG_SET_FIELD(SYSCON_RETENTION_CTRL2_REG, SYSCON_RET_ICACHE_SIZE, size);
|
||||
REG_SET_BIT(SYSCON_RETENTION_CTRL2_REG, SYSCON_RET_ICACHE_ENABLE);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void rtc_cntl_ll_enable_dcache_tagmem_retention(uint32_t start_point, uint32_t vld_size, uint32_t size)
|
||||
{
|
||||
REG_SET_FIELD(SYSCON_RETENTION_CTRL3_REG, SYSCON_RET_DCACHE_START_POINT, start_point);
|
||||
REG_SET_FIELD(SYSCON_RETENTION_CTRL3_REG, SYSCON_RET_DCACHE_VLD_SIZE, vld_size);
|
||||
REG_SET_FIELD(SYSCON_RETENTION_CTRL3_REG, SYSCON_RET_DCACHE_SIZE, size);
|
||||
REG_SET_BIT(SYSCON_RETENTION_CTRL3_REG, SYSCON_RET_DCACHE_ENABLE);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void rtc_cntl_ll_disable_tagmem_retention(void)
|
||||
{
|
||||
/* Enable i/d-cache tagmem retenttion. cpu: 1, tagmem: 2, cpu + tagmem: 3 */
|
||||
uint32_t target = REG_GET_FIELD(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_TARGET);
|
||||
REG_SET_FIELD(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_TARGET, (target & ~RTC_CNTL_LL_RETENTION_TARGET_TAGMEM));
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void rtc_cntl_ll_disable_icache_tagmem_retention(void)
|
||||
{
|
||||
REG_CLR_BIT(SYSCON_RETENTION_CTRL2_REG, SYSCON_RET_ICACHE_ENABLE);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void rtc_cntl_ll_disable_dcache_tagmem_retention(void)
|
||||
{
|
||||
REG_CLR_BIT(SYSCON_RETENTION_CTRL3_REG, SYSCON_RET_DCACHE_ENABLE);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void rtc_cntl_ll_set_cpu_retention_link_addr(uint32_t link_addr)
|
||||
{
|
||||
REG_SET_FIELD(SYSCON_RETENTION_CTRL_REG, SYSCON_RETENTION_CPU_LINK_ADDR, link_addr);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void rtc_cntl_ll_enable_cpu_retention_clock(void)
|
||||
{
|
||||
REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN); /* Enable internal 20 MHz clock */
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void rtc_cntl_ll_enable_cpu_retention(void)
|
||||
{
|
||||
uint32_t target = REG_GET_FIELD(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_TARGET);
|
||||
|
||||
REG_SET_FIELD(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_TARGET, (target | RTC_CNTL_LL_RETENTION_TARGET_CPU));
|
||||
/* Enable retention when cpu sleep enable */
|
||||
REG_SET_BIT(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_EN);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void rtc_cntl_ll_config_cpu_retention_timing(int wait, int clkoff_wait, int done_wait)
|
||||
{
|
||||
REG_SET_FIELD(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_WAIT, wait);
|
||||
REG_SET_FIELD(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_CLKOFF_WAIT, clkoff_wait);
|
||||
REG_SET_FIELD(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_DONE_WAIT, done_wait);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void rtc_cntl_ll_disable_cpu_retention(void)
|
||||
{
|
||||
REG_CLR_BIT(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_EN);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void rtc_cntl_ll_ulp_int_clear(void)
|
||||
{
|
||||
REG_SET_BIT(RTC_CNTL_INT_CLR_REG, RTC_CNTL_ULP_CP_INT_CLR);
|
||||
REG_SET_BIT(RTC_CNTL_INT_CLR_REG, RTC_CNTL_COCPU_INT_CLR);
|
||||
REG_SET_BIT(RTC_CNTL_INT_CLR_REG, RTC_CNTL_COCPU_TRAP_INT_CLR);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void rtc_cntl_ll_timer2_set_touch_wait_cycle(uint32_t wait_cycle)
|
||||
{
|
||||
REG_SET_FIELD(RTC_CNTL_TIMER2_REG, RTC_CNTL_ULPCP_TOUCH_START_WAIT, wait_cycle);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void rtc_cntl_ll_reset_system(void)
|
||||
{
|
||||
REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void rtc_cntl_ll_reset_cpu(int cpu_no)
|
||||
{
|
||||
uint32_t rtc_cntl_rst = (cpu_no == 0) ? RTC_CNTL_SW_PROCPU_RST : RTC_CNTL_SW_APPCPU_RST;
|
||||
REG_WRITE(RTC_CNTL_OPTIONS0_REG, rtc_cntl_rst);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void rtc_cntl_ll_sleep_enable(void)
|
||||
{
|
||||
SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_SLEEP_EN);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_get_rtc_time(void)
|
||||
{
|
||||
SET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_UPDATE);
|
||||
uint64_t t = READ_PERI_REG(RTC_CNTL_TIME0_REG);
|
||||
t |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME1_REG)) << 32;
|
||||
return t;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_get_wakeup_cause(void)
|
||||
{
|
||||
return REG_GET_FIELD(RTC_CNTL_SLP_WAKEUP_CAUSE_REG, RTC_CNTL_WAKEUP_CAUSE);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,155 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The HAL layer for RTC CNTL (common part)
|
||||
|
||||
#include "hal/rtc_hal.h"
|
||||
#include "soc/soc_caps.h"
|
||||
#include "esp32s3/rom/lldesc.h"
|
||||
#include "esp32s3/rom/cache.h"
|
||||
#include "hal/dma_types.h"
|
||||
#include "hal/assert.h"
|
||||
#include "esp_attr.h"
|
||||
|
||||
#define RTC_CNTL_HAL_LINK_BUF_SIZE_MIN (SOC_RTC_CNTL_CPU_PD_DMA_BLOCK_SIZE) /* The minimum size of dma link buffer */
|
||||
|
||||
typedef struct rtc_cntl_link_buf_conf {
|
||||
uint32_t cfg[4]; /* 4 word for dma link buffer configuration */
|
||||
} rtc_cntl_link_buf_conf_t;
|
||||
|
||||
void * rtc_cntl_hal_dma_link_init(void *elem, void *buff, int size, void *next)
|
||||
{
|
||||
HAL_ASSERT(elem != NULL);
|
||||
HAL_ASSERT(buff != NULL);
|
||||
HAL_ASSERT(size >= RTC_CNTL_HAL_LINK_BUF_SIZE_MIN);
|
||||
|
||||
lldesc_t *plink = (lldesc_t *)elem;
|
||||
|
||||
plink->eof = next ? 0 : 1;
|
||||
plink->owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA;
|
||||
plink->size = size >> 4; /* in unit of 16 bytes */
|
||||
plink->length = size >> 4;
|
||||
plink->buf = buff;
|
||||
plink->offset = 0;
|
||||
plink->sosf = 0;
|
||||
STAILQ_NEXT(plink, qe) = next;
|
||||
return (void *)plink;
|
||||
}
|
||||
|
||||
#if SOC_PM_SUPPORT_CPU_PD
|
||||
|
||||
#define DEFAULT_RETENTION_WAIT_CYCLES (0x7f)
|
||||
#define DEFAULT_RETENTION_CLKOFF_WAIT_CYCLES (0xf)
|
||||
#define DEFAULT_RETENTION_DONE_WAIT_CYCLES (0x7)
|
||||
|
||||
void rtc_cntl_hal_enable_cpu_retention(void *addr)
|
||||
{
|
||||
rtc_cntl_sleep_retent_t *retent = (rtc_cntl_sleep_retent_t *)addr;
|
||||
|
||||
if (addr) {
|
||||
if (retent->cpu_pd_mem) {
|
||||
lldesc_t *plink = (lldesc_t *)retent->cpu_pd_mem;
|
||||
|
||||
/* dma link buffer configure */
|
||||
rtc_cntl_link_buf_conf_t *pbuf = (rtc_cntl_link_buf_conf_t *)plink->buf;
|
||||
pbuf->cfg[0] = 0;
|
||||
pbuf->cfg[1] = 0;
|
||||
pbuf->cfg[2] = 0;
|
||||
pbuf->cfg[3] = 0xfffe0000;
|
||||
|
||||
rtc_cntl_ll_set_cpu_retention_link_addr((uint32_t)plink);
|
||||
rtc_cntl_ll_config_cpu_retention_timing(
|
||||
DEFAULT_RETENTION_WAIT_CYCLES,
|
||||
DEFAULT_RETENTION_CLKOFF_WAIT_CYCLES,
|
||||
DEFAULT_RETENTION_DONE_WAIT_CYCLES
|
||||
);
|
||||
rtc_cntl_ll_enable_cpu_retention_clock();
|
||||
rtc_cntl_ll_enable_cpu_retention();
|
||||
#if SOC_PM_SUPPORT_TAGMEM_PD
|
||||
if (!retent->tagmem.dcache.enable) {
|
||||
// Here we only need to care for the safety of the PSRAM data in the DCache.
|
||||
// Since only rodata, bss, heap data may be placed in PSRAM, and these data won't be
|
||||
// modified in the sleep process code after now, so it is safe to writeback here.
|
||||
Cache_WriteBack_All();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void IRAM_ATTR rtc_cntl_hal_disable_cpu_retention(void *addr)
|
||||
{
|
||||
rtc_cntl_sleep_retent_t *retent = (rtc_cntl_sleep_retent_t *)addr;
|
||||
|
||||
if (addr) {
|
||||
if (retent->cpu_pd_mem) {
|
||||
/* I/d-cache tagmem retention has not been included or not
|
||||
* been enabled, after the system wakes up, all the contents
|
||||
* of i/d-cache need to be invalidated. */
|
||||
#if SOC_PM_SUPPORT_TAGMEM_PD
|
||||
if (!retent->tagmem.icache.enable) {
|
||||
Cache_Invalidate_ICache_All();
|
||||
}
|
||||
if (!retent->tagmem.dcache.enable) {
|
||||
Cache_Invalidate_DCache_All();
|
||||
}
|
||||
#else
|
||||
Cache_Invalidate_ICache_All();
|
||||
Cache_Invalidate_DCache_All();
|
||||
#endif // SOC_PM_SUPPORT_TAGMEM_PD
|
||||
rtc_cntl_ll_disable_cpu_retention();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#endif // SOC_PM_SUPPORT_CPU_PD
|
||||
|
||||
#if SOC_PM_SUPPORT_TAGMEM_PD
|
||||
|
||||
void rtc_cntl_hal_enable_tagmem_retention(void *addr)
|
||||
{
|
||||
rtc_cntl_sleep_retent_t *retent = (rtc_cntl_sleep_retent_t *)addr;
|
||||
|
||||
if (addr) {
|
||||
if (retent->tagmem.link_addr) {
|
||||
rtc_cntl_ll_set_tagmem_retention_link_addr((uint32_t)(retent->tagmem.link_addr));
|
||||
rtc_cntl_ll_enable_tagmem_retention();
|
||||
if (retent->tagmem.icache.enable) {
|
||||
rtc_cntl_ll_enable_icache_tagmem_retention(
|
||||
retent->tagmem.icache.start_point,
|
||||
retent->tagmem.icache.vld_size,
|
||||
retent->tagmem.icache.size
|
||||
);
|
||||
}
|
||||
if (retent->tagmem.dcache.enable) {
|
||||
rtc_cntl_ll_enable_dcache_tagmem_retention(
|
||||
retent->tagmem.dcache.start_point,
|
||||
retent->tagmem.dcache.vld_size,
|
||||
retent->tagmem.dcache.size
|
||||
);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void IRAM_ATTR rtc_cntl_hal_disable_tagmem_retention(void *addr)
|
||||
{
|
||||
rtc_cntl_sleep_retent_t *retent = (rtc_cntl_sleep_retent_t *)addr;
|
||||
|
||||
if (addr) {
|
||||
if (retent->tagmem.link_addr) {
|
||||
rtc_cntl_ll_disable_tagmem_retention();
|
||||
if (retent->tagmem.icache.enable) {
|
||||
rtc_cntl_ll_disable_icache_tagmem_retention();
|
||||
}
|
||||
if (retent->tagmem.dcache.enable) {
|
||||
rtc_cntl_ll_disable_dcache_tagmem_retention();
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#endif // SOC_PM_SUPPORT_TAGMEM_PD
|
||||
@@ -0,0 +1,23 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The HAL layer for PMU
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "soc/soc_caps.h"
|
||||
#include "hal/pmu_ll.h"
|
||||
#include "hal/pmu_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
// TODO: ["ESP32S31"] IDF-14653
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,29 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The LL layer for ESP32-S31 PMU register operations
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <stdbool.h>
|
||||
#include "soc/soc.h"
|
||||
#include "esp_attr.h"
|
||||
#include "hal/assert.h"
|
||||
#include "soc/pmu_struct.h"
|
||||
#include "hal/pmu_types.h"
|
||||
#include "hal/misc.h"
|
||||
#include "hal/config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
// TODO: ["ESP32S31"] IDF-14653
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,9 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The HAL layer for PMU (ESP32-S31 specific part)
|
||||
|
||||
// TODO: ["ESP32S31"] IDF-14653
|
||||
@@ -0,0 +1,60 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/soc_caps.h"
|
||||
#include "hal/config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PMU modes of HP system
|
||||
*/
|
||||
typedef enum {
|
||||
PMU_MODE_HP_ACTIVE = 0, /*!< PMU in HP_ACTIVE mode */
|
||||
PMU_MODE_HP_MODEM, /*!< PMU in HP_MODEM mode */
|
||||
PMU_MODE_HP_SLEEP, /*!< PMU in HP_SLEEP mode */
|
||||
PMU_MODE_HP_MAX,
|
||||
} pmu_hp_mode_t;
|
||||
|
||||
/**
|
||||
* @brief PMU modes of LP system
|
||||
*/
|
||||
typedef enum {
|
||||
PMU_MODE_LP_ACTIVE = 0, /*!< PMU in LP_ACTIVE mode */
|
||||
PMU_MODE_LP_SLEEP, /*!< PMU in LP_SLEEP mode */
|
||||
PMU_MODE_LP_MAX,
|
||||
} pmu_lp_mode_t;
|
||||
|
||||
/**
|
||||
* @brief PMU power domain of HP system
|
||||
*/
|
||||
#if SOC_IS(ESP32P4)
|
||||
typedef enum {
|
||||
PMU_HP_PD_TOP = 0, /*!< Power domain of digital top */
|
||||
PMU_HP_PD_CNNT = 1, /*!< Power domain of high-speed IO peripherals such as USB/SDIO/Ethernet etc.*/
|
||||
PMU_HP_PD_HPMEM = 2,
|
||||
PMU_HP_PD_CPU = 3,
|
||||
} pmu_hp_power_domain_t;
|
||||
#else
|
||||
typedef enum {
|
||||
PMU_HP_PD_TOP = 0, /*!< Power domain of digital top */
|
||||
#if SOC_PM_SUPPORT_HP_AON_PD
|
||||
PMU_HP_PD_HP_AON = 1, /*!< Power domain of always-on */
|
||||
#endif
|
||||
PMU_HP_PD_CPU = 2, /*!< Power domain of HP CPU */
|
||||
PMU_HP_PD_RESERVED = 3, /*!< Reserved power domain */
|
||||
PMU_HP_PD_WIFI = 4, /*!< Power domain of WIFI */
|
||||
} pmu_hp_power_domain_t;
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,122 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/soc_caps.h"
|
||||
#include "hal/gpio_types.h"
|
||||
|
||||
#if SOC_IS(ESP32) || SOC_IS(ESP32C2) || SOC_IS(ESP32C3) || SOC_IS(ESP32S2) || SOC_IS(ESP32S3)
|
||||
#include "hal/rtc_cntl_ll.h"
|
||||
#endif
|
||||
|
||||
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
|
||||
#include "hal/rtc_io_ll.h"
|
||||
#endif
|
||||
|
||||
#if SOC_LP_AON_SUPPORTED
|
||||
#include "hal/lp_aon_ll.h"
|
||||
#endif
|
||||
|
||||
#if SOC_PM_EXT1_WAKEUP_BY_PMU
|
||||
#include "hal/pmu_ll.h"
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if SOC_PM_SUPPORT_TAGMEM_PD
|
||||
typedef struct rtc_cntl_sleep_cache_tag_retent {
|
||||
void *link_addr; /* Internal ram address for tagmem retention */
|
||||
struct {
|
||||
uint32_t start_point: 8, /* the row of start for i-cache tag memory */
|
||||
vld_size: 8, /* valid size of i-cache tag memory, unit: 4 i-cache tagmem blocks */
|
||||
size: 8, /* i-cache tag memory size, unit: 4 i-cache tagmem blocks */
|
||||
enable: 1; /* enable or disable i-cache tagmem retention */
|
||||
} icache;
|
||||
struct {
|
||||
uint32_t start_point: 9, /* the row of start for d-cache tag memory */
|
||||
vld_size: 9, /* valid size of d-cache tag memory, unit: 4 d-cache tagmem blocks */
|
||||
size: 9, /* d-cache tag memory size, unit: 4 d-cache tagmem blocks */
|
||||
enable: 1; /* enable or disable d-cache tagmem retention */
|
||||
} dcache;
|
||||
} rtc_cntl_sleep_cache_tag_retent_t;
|
||||
#endif
|
||||
|
||||
typedef struct rtc_cntl_sleep_retent {
|
||||
#if SOC_PM_SUPPORT_CPU_PD
|
||||
void *cpu_pd_mem; /* Internal ram address for cpu retention */
|
||||
#endif // SOC_PM_SUPPORT_CPU_PD
|
||||
#if SOC_PM_SUPPORT_TAGMEM_PD
|
||||
rtc_cntl_sleep_cache_tag_retent_t tagmem; /* I/D Cache tag memory retention information */
|
||||
#endif // SOC_PM_SUPPORT_TAGMEM_PD
|
||||
} rtc_cntl_sleep_retent_t;
|
||||
|
||||
#define RTC_HAL_DMA_LINK_NODE_SIZE (16)
|
||||
|
||||
#if SOC_PM_SUPPORT_EXT1_WAKEUP
|
||||
|
||||
#if SOC_LP_AON_SUPPORTED
|
||||
#define rtc_hal_ext1_get_wakeup_status() lp_aon_ll_ext1_get_wakeup_status()
|
||||
#define rtc_hal_ext1_clear_wakeup_status() lp_aon_ll_ext1_clear_wakeup_status()
|
||||
#define rtc_hal_ext1_set_wakeup_pins(io_mask, mode_mask) lp_aon_ll_ext1_set_wakeup_pins(io_mask, mode_mask)
|
||||
#define rtc_hal_ext1_clear_wakeup_pins() lp_aon_ll_ext1_clear_wakeup_pins()
|
||||
#define rtc_hal_ext1_get_wakeup_pins() lp_aon_ll_ext1_get_wakeup_pins()
|
||||
#elif SOC_PM_EXT1_WAKEUP_BY_PMU
|
||||
#define rtc_hal_ext1_get_wakeup_status() pmu_ll_ext1_get_wakeup_status()
|
||||
#define rtc_hal_ext1_clear_wakeup_status() pmu_ll_ext1_clear_wakeup_status()
|
||||
#define rtc_hal_ext1_set_wakeup_pins(io_mask, mode_mask) pmu_ll_ext1_set_wakeup_pins(io_mask, mode_mask)
|
||||
#define rtc_hal_ext1_clear_wakeup_pins() pmu_ll_ext1_clear_wakeup_pins()
|
||||
#define rtc_hal_ext1_get_wakeup_pins() pmu_ll_ext1_get_wakeup_pins()
|
||||
#else
|
||||
#define rtc_hal_ext1_get_wakeup_status() rtc_cntl_ll_ext1_get_wakeup_status()
|
||||
#define rtc_hal_ext1_clear_wakeup_status() rtc_cntl_ll_ext1_clear_wakeup_status()
|
||||
#define rtc_hal_ext1_set_wakeup_pins(io_mask, mode_mask) rtc_cntl_ll_ext1_set_wakeup_pins(io_mask, mode_mask)
|
||||
#define rtc_hal_ext1_clear_wakeup_pins() rtc_cntl_ll_ext1_clear_wakeup_pins()
|
||||
#define rtc_hal_ext1_get_wakeup_pins() rtc_cntl_ll_ext1_get_wakeup_pins()
|
||||
#endif
|
||||
#endif // SOC_PM_SUPPORT_EXT1_WAKEUP
|
||||
|
||||
#if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP && (SOC_RTCIO_PIN_COUNT == 0) && SOC_DEEP_SLEEP_SUPPORTED
|
||||
|
||||
#define rtc_hal_gpio_get_wakeup_status() rtc_cntl_ll_gpio_get_wakeup_status()
|
||||
|
||||
#define rtc_hal_gpio_clear_wakeup_status() rtc_cntl_ll_gpio_clear_wakeup_status()
|
||||
|
||||
#endif
|
||||
|
||||
#define rtc_hal_set_wakeup_timer(ticks) rtc_cntl_ll_set_wakeup_timer(ticks)
|
||||
|
||||
void * rtc_cntl_hal_dma_link_init(void *elem, void *buff, int size, void *next);
|
||||
|
||||
#if SOC_PM_SUPPORT_CPU_PD
|
||||
|
||||
void rtc_cntl_hal_enable_cpu_retention(void *addr);
|
||||
|
||||
void rtc_cntl_hal_disable_cpu_retention(void *addr);
|
||||
|
||||
#endif
|
||||
|
||||
#if SOC_PM_SUPPORT_TAGMEM_PD
|
||||
|
||||
void rtc_cntl_hal_enable_tagmem_retention(void *addr);
|
||||
|
||||
void rtc_cntl_hal_disable_tagmem_retention(void *addr);
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Enable wakeup from ULP coprocessor.
|
||||
*/
|
||||
#define rtc_hal_ulp_wakeup_enable() rtc_cntl_ll_ulp_wakeup_enable()
|
||||
|
||||
#define rtc_hal_ulp_int_clear() rtc_cntl_ll_ulp_int_clear()
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,5 @@
|
||||
[mapping:esp_hal_pmu]
|
||||
archive: libesp_hal_pmu.a
|
||||
entries:
|
||||
if SOC_PMU_SUPPORTED = y:
|
||||
pmu_hal (noflash)
|
||||
Reference in New Issue
Block a user