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Merge branch 'fix/rmii_ref_ckl_v5.3' into 'release/v5.3'

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fix(esp_eth): fixed ESP32P4 EMAC REF RMII CLK output mode (v5.3)

See merge request espressif/esp-idf!38040
This commit is contained in:
Jiang Jiang Jian
2025-04-27 14:21:28 +08:00
parent 7ca3e628e5 babd94dd66
commit dcd92c96bf
17 changed files with 288 additions and 40 deletions
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components/soc/esp32p4/include/soc/clk_tree_defs.h
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@@ -145,6 +145,7 @@ typedef enum {
// For digital domain: peripherals
SOC_MOD_CLK_PLL_F20M, /*!< PLL_F20M_CLK is derived from SPLL (clock gating + default divider 24), its default frequency is 20MHz */
SOC_MOD_CLK_PLL_F25M, /*!< PLL_F25M_CLK is derived from MPLL (clock gating + configurable divider), it will have a frequency of 25MHz */
SOC_MOD_CLK_PLL_F50M, /*!< PLL_F50M_CLK is derived from MPLL (clock gating + configurable divider 10), it will have a frequency of 50MHz */
SOC_MOD_CLK_PLL_F80M, /*!< PLL_F80M_CLK is derived from SPLL (clock gating + default divider 6), its default frequency is 80MHz */
SOC_MOD_CLK_PLL_F160M, /*!< PLL_F160M_CLK is derived from SPLL (clock gating + default divider 3), its default frequency is 160MHz */
SOC_MOD_CLK_PLL_F240M, /*!< PLL_F240M_CLK is derived from SPLL (clock gating + default divider 2), its default frequency is 240MHz */