From 583f5b4de32f9aa90451065119dd1dcc83654619 Mon Sep 17 00:00:00 2001 From: gaoxu Date: Fri, 26 Jun 2026 10:55:15 +0800 Subject: [PATCH 1/3] feat(rng): basic rng support on ESP32-H21 --- .../src/bootloader_random_esp32h21.c | 18 ++++++++++++++++++ .../esp32h21/include/soc/Kconfig.soc_caps.in | 4 ++++ components/soc/esp32h21/include/soc/soc_caps.h | 2 +- 3 files changed, 23 insertions(+), 1 deletion(-) create mode 100644 components/bootloader_support/src/bootloader_random_esp32h21.c diff --git a/components/bootloader_support/src/bootloader_random_esp32h21.c b/components/bootloader_support/src/bootloader_random_esp32h21.c new file mode 100644 index 00000000000..071ea905cfc --- /dev/null +++ b/components/bootloader_support/src/bootloader_random_esp32h21.c @@ -0,0 +1,18 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "sdkconfig.h" +#include "bootloader_random.h" + + +void bootloader_random_enable(void) +{ + +} + +void bootloader_random_disable(void) +{ + +} diff --git a/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in index 8e8dce4b523..64dcec968de 100644 --- a/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in @@ -171,6 +171,10 @@ config SOC_SPI_EXTERNAL_NOR_FLASH_SUPPORTED bool default y +config SOC_RNG_SUPPORTED + bool + default y + config SOC_MODEM_CLOCK_SUPPORTED bool default y diff --git a/components/soc/esp32h21/include/soc/soc_caps.h b/components/soc/esp32h21/include/soc/soc_caps.h index 5ed34d361de..2311357e61c 100644 --- a/components/soc/esp32h21/include/soc/soc_caps.h +++ b/components/soc/esp32h21/include/soc/soc_caps.h @@ -71,7 +71,7 @@ #define SOC_RTC_WDT_SUPPORTED 1 #define SOC_SPI_FLASH_SUPPORTED 1 #define SOC_SPI_EXTERNAL_NOR_FLASH_SUPPORTED 1 -// #define SOC_RNG_SUPPORTED 1 //TODO: [ESP32H21] IDF-11503 +#define SOC_RNG_SUPPORTED 1 #define SOC_MODEM_CLOCK_SUPPORTED 1 #define SOC_REGI2C_SUPPORTED 1 #define SOC_PHY_SUPPORTED 1 From f704fbb5ecd719f23ec4fe5e9fea0d14a46d42e9 Mon Sep 17 00:00:00 2001 From: hongshuqing Date: Fri, 26 Jun 2026 19:08:10 +0800 Subject: [PATCH 2/3] update bootloader_random_enable and disbale api --- .../src/bootloader_random_esp32h21.c | 24 ++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/components/bootloader_support/src/bootloader_random_esp32h21.c b/components/bootloader_support/src/bootloader_random_esp32h21.c index 071ea905cfc..01612120702 100644 --- a/components/bootloader_support/src/bootloader_random_esp32h21.c +++ b/components/bootloader_support/src/bootloader_random_esp32h21.c @@ -5,14 +5,36 @@ */ #include "sdkconfig.h" #include "bootloader_random.h" +#include "soc/lpperi_reg.h" +#include "rom/ets_sys.h" +#include "rom/uart.h" void bootloader_random_enable(void) { + // Disable rtc_timer update for rng + SET_PERI_REG_BITS(LPPERI_RNG_CFG_REG, LPPERI_RTC_TIMER_EN, 0, LPPERI_RTC_TIMER_EN_S); + // Enable entropy source of ring + SET_PERI_REG_MASK(LPPERI_RNG_CFG_REG, LPPERI_RNG_SAMPLE_ENABLE); + //For dieharder test + ets_printf("H21: Random bytes (%s) follow:\n", "test"); + while (1) { + uint32_t w = READ_PERI_REG(LPPERI_RNG_DATA_SYNC_REG); + ets_printf("rng_data:%d\n", w); + uart_tx_wait_idle(0); + + // uart_tx_one_char(w >> 24); + // uart_tx_one_char(w >> 16); + // uart_tx_one_char(w >> 8); + // uart_tx_one_char(w); + } } void bootloader_random_disable(void) { - + // Disable rtc_timer update for rng + SET_PERI_REG_BITS(LPPERI_RNG_CFG_REG, LPPERI_RTC_TIMER_EN, 0, LPPERI_RTC_TIMER_EN_S); + // Disable entropy source of ring + CLEAR_PERI_REG_MASK(LPPERI_RNG_CFG_REG, LPPERI_RNG_SAMPLE_ENABLE); } From d31a63d246b4111f1902f0692e142e095d57d000 Mon Sep 17 00:00:00 2001 From: gaoxu Date: Mon, 20 Jul 2026 17:15:26 +0800 Subject: [PATCH 3/3] feat(rng): refactor rng bootloader to rng ll API --- .../src/bootloader_random_esp32h21.c | 28 +------- components/hal/esp32h21/include/hal/rng_ll.h | 68 ++++++++++++++++++- .../soc/esp32h21/include/soc/wdev_reg.h | 2 +- 3 files changed, 70 insertions(+), 28 deletions(-) diff --git a/components/bootloader_support/src/bootloader_random_esp32h21.c b/components/bootloader_support/src/bootloader_random_esp32h21.c index 01612120702..4b6f012b819 100644 --- a/components/bootloader_support/src/bootloader_random_esp32h21.c +++ b/components/bootloader_support/src/bootloader_random_esp32h21.c @@ -5,36 +5,14 @@ */ #include "sdkconfig.h" #include "bootloader_random.h" -#include "soc/lpperi_reg.h" -#include "rom/ets_sys.h" -#include "rom/uart.h" - +#include "hal/rng_ll.h" void bootloader_random_enable(void) { - // Disable rtc_timer update for rng - SET_PERI_REG_BITS(LPPERI_RNG_CFG_REG, LPPERI_RTC_TIMER_EN, 0, LPPERI_RTC_TIMER_EN_S); - // Enable entropy source of ring - SET_PERI_REG_MASK(LPPERI_RNG_CFG_REG, LPPERI_RNG_SAMPLE_ENABLE); - - //For dieharder test - ets_printf("H21: Random bytes (%s) follow:\n", "test"); - while (1) { - uint32_t w = READ_PERI_REG(LPPERI_RNG_DATA_SYNC_REG); - ets_printf("rng_data:%d\n", w); - uart_tx_wait_idle(0); - - // uart_tx_one_char(w >> 24); - // uart_tx_one_char(w >> 16); - // uart_tx_one_char(w >> 8); - // uart_tx_one_char(w); - } + rng_ll_enable(); } void bootloader_random_disable(void) { - // Disable rtc_timer update for rng - SET_PERI_REG_BITS(LPPERI_RNG_CFG_REG, LPPERI_RTC_TIMER_EN, 0, LPPERI_RTC_TIMER_EN_S); - // Disable entropy source of ring - CLEAR_PERI_REG_MASK(LPPERI_RNG_CFG_REG, LPPERI_RNG_SAMPLE_ENABLE); + rng_ll_disable(); } diff --git a/components/hal/esp32h21/include/hal/rng_ll.h b/components/hal/esp32h21/include/hal/rng_ll.h index 9846d7e6080..b3d6f42a38f 100644 --- a/components/hal/esp32h21/include/hal/rng_ll.h +++ b/components/hal/esp32h21/include/hal/rng_ll.h @@ -6,26 +6,90 @@ #pragma once +#include #include #include "soc/soc.h" #include "soc/lpperi_reg.h" +#include "soc/wdev_reg.h" +#include "soc/lpperi_struct.h" +#include "hal/lp_clkrst_ll.h" #ifdef __cplusplus extern "C" { #endif +/** + * @brief Read random data from RNG + * + * @return 32-bit random data + */ static inline uint32_t rng_ll_read_data(void) { - return REG_READ(LPPERI_RNG_DATA_REG); + return REG_READ(WDEV_RND_REG); } -/* For compatibility. */ +/** + * @brief Enable or disable RNG sampling. + * + * @param enable True to enable, False to disable + */ +static inline void rng_ll_enable_sample(bool enable) +{ + LPPERI.rng_cfg.rng_sample_enable = enable; +} + +/** + * @brief Enable or disable rng xor rtc timer. + * + * @param enable True to enable, False to disable + */ +static inline void rng_ll_enable_rtc_timer(bool enable) +{ + LPPERI.rng_cfg.rtc_timer_en = enable ? 0x3 : 0x0; +} + +/** + * @brief Enable or disable rng xor async rng timer. + * + * @param enable True to enable, False to disable + */ +static inline void rng_ll_enable_rng_timer(bool enable) +{ + LPPERI.rng_cfg.rng_timer_en = enable; +} + +/** + * @brief Reset RNG. + */ +static inline void rng_ll_reset(void) +{ + // ESP32-H21 does not expose a dedicated RNG reset bit. +} + +/** + * @brief Enable RNG module + * + * TODO: unify in rng_hal.c + */ static inline void rng_ll_enable(void) { + _lp_clkrst_ll_enable_rng_clock(true); + rng_ll_enable_sample(true); + rng_ll_enable_rtc_timer(false); + rng_ll_enable_rng_timer(false); } +/** + * @brief Disable RNG module + * + * TODO: unify in rng_hal.c + */ static inline void rng_ll_disable(void) { + rng_ll_enable_sample(false); + rng_ll_enable_rtc_timer(false); + rng_ll_enable_rng_timer(false); + _lp_clkrst_ll_enable_rng_clock(false); } #ifdef __cplusplus diff --git a/components/soc/esp32h21/include/soc/wdev_reg.h b/components/soc/esp32h21/include/soc/wdev_reg.h index 182395e64fe..3e111df8053 100644 --- a/components/soc/esp32h21/include/soc/wdev_reg.h +++ b/components/soc/esp32h21/include/soc/wdev_reg.h @@ -10,4 +10,4 @@ #include "soc/lpperi_reg.h" /* Hardware random number generator register */ -#define WDEV_RND_REG LPPERI_RNG_DATA_REG +#define WDEV_RND_REG LPPERI_RNG_DATA_SYNC_REG