Merge branch 'feat/basic_rng_support_h4' into 'master'

RNG support and refactor on ESP32-H4

Closes IDF-12265

See merge request espressif/esp-idf!45361

components/bootloader_support/src/bootloader_random_esp32.c

@@ -5,6 +5,7 @@
  */
 #include "sdkconfig.h"
 #include "bootloader_random.h"
+#include "hal/rng_ll.h"
 #include "soc/rtc_periph.h"
 #include "soc/sens_reg.h"
 #include "soc/syscon_reg.h"
@@ -74,10 +75,13 @@ void bootloader_random_enable(void)
     SET_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_DATA_ENABLE);
     SET_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_DATA_ENABLE_TEST_EN);
     SET_PERI_REG_MASK(I2S_CONF_REG(0), I2S_RX_START);
+    rng_ll_enable();
 }
 
 void bootloader_random_disable(void)
 {
+    rng_ll_disable();
+
     /* Reset some i2s configuration (possibly redundant as we reset entire
        I2S peripheral further down). */
     CLEAR_PERI_REG_MASK(I2S_CONF_REG(0), I2S_RX_START);

components/bootloader_support/src/bootloader_random_esp32c2.c

@@ -5,6 +5,7 @@
  */
 #include "sdkconfig.h"
 #include "bootloader_random.h"
+#include "hal/rng_ll.h"
 #include "esp_log.h"
 #include "soc/syscon_reg.h"
 #include "soc/rtc_cntl_reg.h"
@@ -56,10 +57,13 @@ void bootloader_random_enable(void)
     adc_ll_digi_convert_limit_enable(false);
     adc_ll_digi_dma_enable();
     adc_ll_digi_trigger_enable();
+    rng_ll_enable();
 }
 
 void bootloader_random_disable(void)
 {
+    rng_ll_disable();
+
     _adc_ll_enable_bus_clock(false);
     adc_ll_digi_trigger_disable();
     adc_ll_digi_reset_pattern_table();

components/bootloader_support/src/bootloader_random_esp32c3.c

@@ -5,6 +5,7 @@
  */
 #include "sdkconfig.h"
 #include "bootloader_random.h"
+#include "hal/rng_ll.h"
 #include "soc/rtc_cntl_reg.h"
 #include "esp_private/regi2c_ctrl.h"
 #include "esp_private/sar_periph_ctrl.h"
@@ -62,10 +63,13 @@ void bootloader_random_enable(void)
     adc_ll_digi_set_clk_div(1);
     adc_ll_digi_set_trigger_interval(100);
     adc_ll_digi_trigger_enable();
+    rng_ll_enable();
 }
 
 void bootloader_random_disable(void)
 {
+    rng_ll_disable();
+
     _adc_ll_enable_bus_clock(false);
     adc_ll_digi_trigger_disable();
     adc_ll_digi_reset_pattern_table();

components/bootloader_support/src/bootloader_random_esp32c5.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -67,13 +67,12 @@ void bootloader_random_enable(void)
     adc_ll_digi_set_trigger_interval(200);
     adc_ll_digi_trigger_enable();
 
-    rng_ll_enable_sample(true);
+    rng_ll_enable();
-    rng_ll_enable_rtc_timer(true);
-    rng_ll_enable_rng_timer(true);
 }
 
 void bootloader_random_disable(void)
 {
+    rng_ll_disable();
     adc_ll_digi_trigger_disable();
     adc_ll_digi_reset_pattern_table();
     adc_ll_set_calibration_param(ADC_UNIT_1, 0x0);

components/bootloader_support/src/bootloader_random_esp32c6.c

@@ -5,6 +5,7 @@
  */
 #include "sdkconfig.h"
 #include "bootloader_random.h"
+#include "hal/rng_ll.h"
 #include "hal/regi2c_ctrl_ll.h"
 #include "hal/adc_ll.h"
 #include "hal/adc_types.h"
@@ -63,10 +64,13 @@ void bootloader_random_enable(void)
     adc_ll_digi_set_clk_div(15);
     adc_ll_digi_set_trigger_interval(200);
     adc_ll_digi_trigger_enable();
+    rng_ll_enable();
 }
 
 void bootloader_random_disable(void)
 {
+    rng_ll_disable();
+
     adc_ll_digi_trigger_disable();
     adc_ll_digi_reset_pattern_table();
     adc_ll_set_calibration_param(ADC_UNIT_1, 0x0);

components/bootloader_support/src/bootloader_random_esp32c61.c

@@ -5,6 +5,7 @@
  */
 #include "sdkconfig.h"
 #include "bootloader_random.h"
+#include "hal/rng_ll.h"
 #include "hal/regi2c_ctrl_ll.h"
 #include "hal/adc_ll.h"
 #include "hal/adc_types.h"
@@ -64,10 +65,13 @@ void bootloader_random_enable(void)
     adc_ll_digi_set_clk_div(15);
     adc_ll_digi_set_trigger_interval(200);
     adc_ll_digi_trigger_enable();
+    rng_ll_enable();
 }
 
 void bootloader_random_disable(void)
 {
+    rng_ll_disable();
+
     adc_ll_digi_trigger_disable();
     adc_ll_digi_reset_pattern_table();
     adc_ll_set_calibration_param(ADC_UNIT_1, 0x0);

components/bootloader_support/src/bootloader_random_esp32h2.c

@@ -5,6 +5,7 @@
  */
 #include "sdkconfig.h"
 #include "bootloader_random.h"
+#include "hal/rng_ll.h"
 #include "hal/regi2c_ctrl_ll.h"
 #include "hal/adc_ll.h"
 #include "hal/adc_types.h"
@@ -62,10 +63,13 @@ void bootloader_random_enable(void)
     adc_ll_digi_set_clk_div(15);
     adc_ll_digi_set_trigger_interval(200);
     adc_ll_digi_trigger_enable();
+    rng_ll_enable();
 }
 
 void bootloader_random_disable(void)
 {
+    rng_ll_disable();
+
     adc_ll_digi_trigger_disable();
     adc_ll_digi_reset_pattern_table();
     adc_ll_set_calibration_param(ADC_UNIT_1, 0x0);

components/bootloader_support/src/bootloader_random_esp32h4.c

@@ -0,0 +1,88 @@
+/*
+ * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "sdkconfig.h"
+#include "bootloader_random.h"
+#include "hal/regi2c_ctrl_ll.h"
+#include "hal/adc_ll.h"
+#include "hal/adc_types.h"
+#include "hal/rng_ll.h"
+#include "esp_private/regi2c_ctrl.h"
+#include "hal/temperature_sensor_ll.h"
+#include "esp_private/sar_periph_ctrl.h"
+
+#define I2C_SAR_ADC_INIT_CODE_VAL       2150
+#define ADC_RNG_CLKM_DIV_NUM            0
+#define ADC_RNG_CLKM_DIV_B              0
+#define ADC_RNG_CLKM_DIV_A              0
+
+void bootloader_random_enable(void)
+{
+#ifndef BOOTLOADER_BUILD
+    sar_periph_ctrl_adc_reset();
+#else
+    // Save temperature sensor related register values before ADC reset
+    tsens_ll_reg_values_t saved_tsens_regs = {};
+    tsens_ll_backup_registers(&saved_tsens_regs);
+    adc_ll_reset_register();
+    // Restore temperature sensor related register values after ADC reset
+    temperature_sensor_ll_reset_module();
+    tsens_ll_restore_registers(&saved_tsens_regs);
+#endif
+
+    adc_ll_enable_bus_clock(true);
+    adc_ll_enable_func_clock(false);
+    adc_ll_digi_clk_sel(ADC_DIGI_CLK_SRC_XTAL);
+    adc_ll_digi_controller_clk_div(ADC_RNG_CLKM_DIV_NUM, ADC_RNG_CLKM_DIV_B, ADC_RNG_CLKM_DIV_A);
+
+    // some ADC sensor registers are in power group PERIF_I2C and need to be enabled via PMU
+#ifndef BOOTLOADER_BUILD
+    regi2c_saradc_enable();
+#else
+    regi2c_ctrl_ll_i2c_sar_periph_enable();
+#endif
+
+    // enable analog i2c master clock for RNG runtime
+    ANALOG_CLOCK_ENABLE();
+
+    adc_ll_regi2c_init();
+    adc_ll_set_calibration_param(ADC_UNIT_1, I2C_SAR_ADC_INIT_CODE_VAL);
+    adc_ll_set_calibration_param(ADC_UNIT_2, I2C_SAR_ADC_INIT_CODE_VAL);
+
+    adc_digi_pattern_config_t pattern_config = {};
+    pattern_config.unit = ADC_UNIT_1;
+    pattern_config.atten = ADC_ATTEN_DB_12;
+    pattern_config.channel = ADC_CHANNEL_7;     // Use reserved channel to get internal voltage
+    adc_ll_digi_set_pattern_table(ADC_UNIT_1, 0, pattern_config);
+    pattern_config.unit = ADC_UNIT_2;
+    pattern_config.atten = ADC_ATTEN_DB_12;
+    pattern_config.channel = ADC_CHANNEL_1;     // Use reserved ADC2 and reserved channel to get internal voltage
+    adc_ll_digi_set_pattern_table(ADC_UNIT_2, 1, pattern_config);
+    adc_ll_digi_set_pattern_table_len(ADC_UNIT_1, 2);
+
+    adc_ll_digi_set_clk_div(15);
+    adc_ll_digi_set_trigger_interval(200);
+    adc_ll_digi_trigger_enable();
+
+    rng_ll_enable();
+}
+
+void bootloader_random_disable(void)
+{
+    rng_ll_disable();
+    adc_ll_digi_trigger_disable();
+    adc_ll_digi_reset_pattern_table();
+    adc_ll_set_calibration_param(ADC_UNIT_1, 0x0);
+    adc_ll_set_calibration_param(ADC_UNIT_2, 0x0);
+    adc_ll_regi2c_adc_deinit();
+#ifndef BOOTLOADER_BUILD
+    regi2c_saradc_disable();
+#endif
+
+    // disable analog i2c master clock
+    ANALOG_CLOCK_DISABLE();
+    adc_ll_digi_controller_clk_div(4, 0, 0);
+    adc_ll_digi_clk_sel(ADC_DIGI_CLK_SRC_XTAL);
+}

components/bootloader_support/src/bootloader_random_esp32p4.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -8,16 +8,12 @@
 #include "hal/regi2c_ctrl_ll.h"
 #include "hal/adc_ll.h"
 #include "hal/adc_types.h"
-#include "hal/config.h"
+#include "hal/rng_ll.h"
 
 #include "esp_private/periph_ctrl.h"
 #include "esp_private/adc_share_hw_ctrl.h"
 #include "esp_private/sar_periph_ctrl.h"
 
-#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
-#include "hal/trng_ll.h"
-#endif
-
 #define I2C_SAR_ADC_INIT_CODE_VAL       2166
 #define ADC_RNG_CLKM_DIV_NUM            0
 #define ADC_RNG_CLKM_DIV_B              0
@@ -65,13 +61,13 @@ void bootloader_random_enable(void)
     adc_ll_digi_set_clk_div(15);
     adc_ll_digi_set_trigger_interval(100);
     adc_ll_digi_trigger_enable();
-#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
+    rng_ll_enable();
-    trng_ll_enable();
-#endif
 }
 
 void bootloader_random_disable(void)
 {
+    rng_ll_disable();
+
     adc_ll_digi_trigger_disable();
     adc_ll_digi_reset_pattern_table();
     adc_ll_set_calibration_param(ADC_UNIT_1, 0x0);
@@ -88,8 +84,4 @@ void bootloader_random_disable(void)
     adc_ll_digi_clk_sel(ADC_DIGI_CLK_SRC_XTAL);
 
     adc_ll_set_controller(ADC_UNIT_1, ADC_LL_CTRL_ULP);
-
-#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
-    trng_ll_disable();
-#endif
 }

components/bootloader_support/src/bootloader_random_esp32s2.c

@@ -5,6 +5,7 @@
  */
 #include "sdkconfig.h"
 #include "bootloader_random.h"
+#include "hal/rng_ll.h"
 #include "soc/rtc_periph.h"
 #include "soc/sens_reg.h"
 #include "soc/dport_reg.h"
@@ -78,10 +79,13 @@ void bootloader_random_enable(void)
     adc_ll_digi_set_clk_div(4);
     adc_ll_digi_set_trigger_interval(100);
     adc_ll_digi_trigger_enable();
+    rng_ll_enable();
 }
 
 void bootloader_random_disable(void)
 {
+    rng_ll_disable();
+
     adc_ll_calibration_clear();
     _adc_ll_enable_bus_clock(false);
     adc_ll_digi_trigger_disable();

components/bootloader_support/src/bootloader_random_esp32s3.c

@@ -5,6 +5,7 @@
  */
 #include "sdkconfig.h"
 #include "bootloader_random.h"
+#include "hal/rng_ll.h"
 #include "soc/syscon_reg.h"
 #include "esp_private/regi2c_ctrl.h"
 #include "esp_private/sar_periph_ctrl.h"
@@ -62,10 +63,13 @@ void bootloader_random_enable(void)
     adc_ll_digi_set_clk_div(3);
     adc_ll_digi_set_trigger_interval(70);
     adc_ll_digi_trigger_enable();
+    rng_ll_enable();
 }
 
 void bootloader_random_disable(void)
 {
+   rng_ll_disable();
+
    adc_ll_digi_trigger_disable();
    adc_ll_digi_reset_pattern_table();
 

components/bootloader_support/src/bootloader_random_esp32s31.c

@@ -5,14 +5,14 @@
  */
 #include "sdkconfig.h"
 #include "bootloader_random.h"
-#include "hal/trng_ll.h"
+#include "hal/rng_ll.h"
 
 void bootloader_random_enable(void)
 {
-    trng_ll_enable();
+    rng_ll_enable();
 }
 
 void bootloader_random_disable(void)
 {
-    trng_ll_disable();
+    rng_ll_disable();
 }

components/esp_hal_ana_conv/esp32h4/include/hal/adc_ll.h

@@ -727,8 +727,11 @@ static inline void adc_ll_set_ent_param(uint32_t param)
 __attribute__((always_inline))
 static inline void adc_ll_enable_tout_bus(adc_unit_t adc_n, bool en)
 {
-    HAL_ASSERT(adc_n == ADC_UNIT_1);
+    if (adc_n == ADC_UNIT_1) {
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_EN_TOUT_SAR1_BUS, en);
+        REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_SAR1_EN_TOUT, en);
+    } else {
+        REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_SAR2_EN_TOUT, en);
+    }
 }
 
 /**
@@ -740,6 +743,7 @@ static inline void adc_ll_regi2c_init(void)
     adc_ll_set_dtest_param(0);
     adc_ll_set_ent_param(1);
     adc_ll_enable_tout_bus(ADC_UNIT_1, true);
+    adc_ll_enable_tout_bus(ADC_UNIT_2, true);
 }
 
 /**
@@ -751,6 +755,7 @@ static inline void adc_ll_regi2c_adc_deinit(void)
     adc_ll_set_dtest_param(0);
     adc_ll_set_ent_param(0);
     adc_ll_enable_tout_bus(ADC_UNIT_1, false);
+    adc_ll_enable_tout_bus(ADC_UNIT_2, false);
 }
 
 /*---------------------------------------------------------------

components/esp_hal_regi2c/test_apps/.build-test-rules.yml

@@ -3,3 +3,5 @@ components/esp_hal_regi2c/test_apps:
     - if: SOC_REGI2C_SUPPORTED == 1
   depends_components:
     - esp_hal_regi2c
+  depends_filepatterns:
+    - components/soc/esp32*/include/soc/regi2c_saradc_*.h

components/esp_hw_support/hw_random.c

@@ -22,10 +22,6 @@
 
 #include "hal/rtc_timer_hal.h"
 
-#if SOC_RNG_CLOCK_IS_INDEPENDENT
-#include "hal/lp_clkrst_ll.h"
-#endif
-
 #if defined CONFIG_IDF_TARGET_ESP32S3
 #define APB_CYCLE_WAIT_NUM (1778) /* If APB clock is 80 MHz, the maximum sampling frequency is around 45 KHz*/
                                   /* 45 KHz reading frequency is the maximum we have tested so far on S3 */
@@ -113,11 +109,7 @@ void esp_fill_random(void *buf, size_t len)
 #if SOC_RNG_CLOCK_IS_INDEPENDENT && !ESP_TEE_BUILD
 ESP_SYSTEM_INIT_FN(init_rng, SECONDARY, BIT(0), 102)
 {
-#if SOC_RNG_BUF_CHAIN_ENTROPY_SOURCE || SOC_RNG_RTC_TIMER_ENTROPY_SOURCE
     rng_ll_enable();
-#else
-    _lp_clkrst_ll_enable_rng_clock(true);
-#endif
     return ESP_OK;
 }
 #endif

components/esp_hw_support/sleep_modes.c

@@ -42,7 +42,7 @@
 #include "hal/rtc_io_hal.h"
 #include "hal/clk_tree_hal.h"
 
-#if SOC_IS(ESP32C5) // Remove after all chips rng_ll.h implemented
+#if RNG_LL_NEEDS_RESET_WHEN_WAKEUP
 #include "hal/rng_ll.h"
 #endif
 
@@ -755,7 +755,7 @@ static SLEEP_FN_ATTR void misc_modules_wake_prepare(uint32_t sleep_flags)
 #if SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION
     temperature_sensor_hal_i2c_saradc_reg_restore();
 #endif
-#if RNG_LL_DEPENDS_ON_LP_PERIPH
+#if RNG_LL_NEEDS_RESET_WHEN_WAKEUP
     if (sleep_flags & PMU_SLEEP_PD_LP_PERIPH) {
         // Re-enable the RNG module.
         rng_ll_reset();

components/hal/esp32/include/hal/rng_ll.h

@@ -19,6 +19,15 @@ static inline uint32_t rng_ll_read_data(void)
     return REG_READ(WDEV_RND_REG);
 }
 
+/* For compatibility. */
+static inline void rng_ll_enable(void)
+{
+}
+
+static inline void rng_ll_disable(void)
+{
+}
+
 #ifdef __cplusplus
 }
 #endif

components/hal/esp32c2/include/hal/rng_ll.h

@@ -19,6 +19,15 @@ static inline uint32_t rng_ll_read_data(void)
     return REG_READ(RNG_DATA_REG);
 }
 
+/* For compatibility. */
+static inline void rng_ll_enable(void)
+{
+}
+
+static inline void rng_ll_disable(void)
+{
+}
+
 #ifdef __cplusplus
 }
 #endif

components/hal/esp32c3/include/hal/rng_ll.h

@@ -19,6 +19,15 @@ static inline uint32_t rng_ll_read_data(void)
     return REG_READ(RNG_DATA_REG);
 }
 
+/* For compatibility. */
+static inline void rng_ll_enable(void)
+{
+}
+
+static inline void rng_ll_disable(void)
+{
+}
+
 #ifdef __cplusplus
 }
 #endif

components/hal/esp32c5/include/hal/rng_ll.h

@@ -13,7 +13,8 @@
 #include "soc/lpperi_struct.h"
 #include "hal/lp_clkrst_ll.h"
 
-#define RNG_LL_DEPENDS_ON_LP_PERIPH 1
+//For ESP32C5, RNG needs to be reset and enabled again when wakeup from sleep
+#define RNG_LL_NEEDS_RESET_WHEN_WAKEUP 1
 
 #ifdef __cplusplus
 extern "C" {

components/hal/esp32c6/include/hal/rng_ll.h

@@ -9,6 +9,7 @@
 #include <stdint.h>
 #include "soc/soc.h"
 #include "soc/lpperi_reg.h"
+#include "hal/lp_clkrst_ll.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -19,6 +20,16 @@ static inline uint32_t rng_ll_read_data(void)
     return REG_READ(LPPERI_RNG_DATA_REG);
 }
 
+static inline void rng_ll_enable(void)
+{
+    _lp_clkrst_ll_enable_rng_clock(true);
+}
+
+static inline void rng_ll_disable(void)
+{
+    _lp_clkrst_ll_enable_rng_clock(false);
+}
+
 #ifdef __cplusplus
 }
 #endif

components/hal/esp32c61/include/hal/rng_ll.h

@@ -19,6 +19,15 @@ static inline uint32_t rng_ll_read_data(void)
     return REG_READ(LPPERI_RNG_DATA_SYNC_REG);
 }
 
+/* For compatibility. */
+static inline void rng_ll_enable(void)
+{
+}
+
+static inline void rng_ll_disable(void)
+{
+}
+
 #ifdef __cplusplus
 }
 #endif

components/hal/esp32h2/include/hal/rng_ll.h

@@ -9,6 +9,7 @@
 #include <stdint.h>
 #include "soc/soc.h"
 #include "soc/lpperi_reg.h"
+#include "hal/lp_clkrst_ll.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -19,6 +20,16 @@ static inline uint32_t rng_ll_read_data(void)
     return REG_READ(LPPERI_RNG_DATA_REG);
 }
 
+static inline void rng_ll_enable(void)
+{
+    _lp_clkrst_ll_enable_rng_clock(true);
+}
+
+static inline void rng_ll_disable(void)
+{
+    _lp_clkrst_ll_enable_rng_clock(false);
+}
+
 #ifdef __cplusplus
 }
 #endif

components/hal/esp32h21/include/hal/rng_ll.h

@@ -19,6 +19,15 @@ static inline uint32_t rng_ll_read_data(void)
     return REG_READ(LPPERI_RNG_DATA_REG);
 }
 
+/* For compatibility. */
+static inline void rng_ll_enable(void)
+{
+}
+
+static inline void rng_ll_disable(void)
+{
+}
+
 #ifdef __cplusplus
 }
 #endif

components/hal/esp32h4/include/hal/lp_clkrst_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -61,6 +61,19 @@ static inline void lp_clkrst_ll_select_modem_32k_clock_source(lp_clkrst_dev_t *h
     hw->lpperi.lp_bletimer_32k_sel = src;
 }
 
+__attribute__((always_inline))
+static inline void _lp_clkrst_ll_enable_rng_clock(bool en)
+{
+    LPPERI.clk_en.rng_apb_ck_en = en;
+    LPPERI.clk_en.rng_ck_en = en;
+}
+
+/// LPPERI.clk_en is a shared register, so this function must be used in an atomic way
+#define lp_clkrst_ll_enable_rng_clock(...) do { \
+        (void)__DECLARE_RCC_ATOMIC_ENV; \
+        _lp_clkrst_ll_enable_rng_clock(__VA_ARGS__); \
+    } while(0)
+
 #ifdef __cplusplus
 }
 #endif

components/hal/esp32h4/include/hal/rng_ll.h

@@ -6,18 +6,91 @@
 
 #pragma once
 
+#include <stdbool.h>
 #include <stdint.h>
 #include "soc/soc.h"
+#include "soc/rng_reg.h"
 #include "soc/wdev_reg.h"
+#include "soc/lpperi_struct.h"
+#include "hal/lp_clkrst_ll.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+/**
+ * @brief Read random data from RNG
+ *
+ * @return 32-bit random data
+ */
 static inline uint32_t rng_ll_read_data(void)
 {
-    // return REG_READ(WDEV_RND_REG); // TODO: IDF-12265
+    return REG_READ(WDEV_RND_REG);
-    return 0;
+}
+
+/**
+ * @brief Enable or disable RNG sampling.
+ *
+ * @param enable True to enable, False to disable
+ */
+static inline void rng_ll_enable_sample(bool enable)
+{
+    REG_SET_FIELD(RNG_CFG_REG, RNG_SAMPLE_ENABLE, enable);
+}
+
+/**
+ * @brief Enable or disable rng xor rtc timer.
+ *
+ * @param enable True to enable, False to disable
+ */
+static inline void rng_ll_enable_rtc_timer(bool enable)
+{
+    REG_SET_FIELD(RNG_CFG_REG, RNG_RTC_TIMER_EN, enable ? 0x3 : 0x0);
+}
+
+/**
+ * @brief Enable or disable rng xor async rng timer.
+ *
+ * @param enable True to enable, False to disable
+ */
+static inline void rng_ll_enable_rng_timer(bool enable)
+{
+    REG_SET_FIELD(RNG_CFG_REG, RNG_TIMER_EN, enable);
+}
+
+/**
+ * @brief Reset RNG.
+ */
+static inline void rng_ll_reset(void)
+{
+    LPPERI.reset_en.lp_rng_apb_reset_en = 1;
+    LPPERI.reset_en.lp_rng_apb_reset_en = 0;
+}
+
+/**
+ * @brief Enable RNG module
+ *
+ * TODO: unify in rng_hal.c
+ */
+static inline void rng_ll_enable(void)
+{
+    _lp_clkrst_ll_enable_rng_clock(true);
+    rng_ll_enable_sample(true);
+    rng_ll_enable_rtc_timer(true);
+    rng_ll_enable_rng_timer(true);
+}
+
+/**
+ * @brief Disable RNG module
+ *
+ * TODO: unify in rng_hal.c
+ */
+static inline void rng_ll_disable(void)
+{
+    rng_ll_enable_sample(false);
+    rng_ll_enable_rtc_timer(false);
+    rng_ll_enable_rng_timer(false);
+    _lp_clkrst_ll_enable_rng_clock(false);
 }
 
 #ifdef __cplusplus

components/hal/esp32p4/include/hal/rng_ll.h

@@ -6,14 +6,15 @@
 
 #pragma once
 
+#include <stdbool.h>
 #include <stdint.h>
 #include "hal/config.h"
 #include "soc/soc.h"
-#include "soc/lp_system_reg.h"
 #if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
-    #include "soc/trng_reg.h"
+#include "soc/trng_reg.h"
+#include "soc/trng_struct.h"
 #else
-    #include "soc/lp_system_reg.h"
+#include "soc/lp_system_reg.h"
 #endif
 
 #ifdef __cplusplus
@@ -29,6 +30,116 @@ static inline uint32_t rng_ll_read_data(void)
 #endif
 }
 
+/**
+ * @brief Enable or disable RNG clock
+ *
+ * @param enable true to enable, false to disable
+ */
+static inline void rng_ll_enable_clock(bool enable)
+{
+#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
+    LP_TRNG.date.clk_en = enable;
+#else
+    (void) enable;
+#endif
+}
+
+/**
+ * @brief Reset RNG module
+ */
+static inline void rng_ll_reset(void)
+{
+#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
+    LP_TRNG.rstn.rstn = 0;
+    LP_TRNG.rstn.rstn = 1;
+#endif
+}
+
+/**
+ * @brief Enable or disable RNG sampling
+ *
+ * @param enable true to enable, false to disable
+ */
+static inline void rng_ll_enable_sample(bool enable)
+{
+#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
+    LP_TRNG.cfg.sample_enable = enable;
+#else
+    (void) enable;
+#endif
+}
+
+/**
+ * @brief Set RNG timer prescaler
+ *
+ * @param prescaler Timer prescaler value (0-255)
+ */
+static inline void rng_ll_set_timer_prescaler(uint8_t prescaler)
+{
+#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
+    LP_TRNG.cfg.timer_pscale = prescaler;
+#else
+    (void) prescaler;
+#endif
+}
+
+/**
+ * @brief Enable or disable RNG timer XOR
+ *
+ * @param enable true to enable, false to disable
+ */
+static inline void rng_ll_enable_timer(bool enable)
+{
+#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
+    LP_TRNG.cfg.timer_en = enable;
+#else
+    (void) enable;
+#endif
+}
+
+/**
+ * @brief Get RNG sample count
+ *
+ * @return Current sample count (0-255)
+ */
+static inline uint8_t rng_ll_get_sample_count(void)
+{
+#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
+    return (uint8_t)LP_TRNG.cfg.sample_cnt;
+#else
+    return 0;
+#endif
+}
+
+/**
+ * @brief Enable RNG module
+ *
+ * TODO: unify in rng_hal.c
+ */
+static inline void rng_ll_enable(void)
+{
+#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
+    rng_ll_enable_clock(true);
+    rng_ll_reset();
+    rng_ll_enable_timer(true);
+    rng_ll_enable_sample(true);
+#endif
+}
+
+/**
+ * @brief Disable RNG module
+ *
+ * TODO: unify in rng_hal.c
+ */
+static inline void rng_ll_disable(void)
+{
+#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
+    rng_ll_enable_sample(false);
+    rng_ll_enable_timer(false);
+    rng_ll_enable_clock(false);
+#endif
+}
+
 #ifdef __cplusplus
 }
 #endif

components/hal/esp32p4/include/hal/trng_ll.h

@@ -1,116 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-#include <stdbool.h>
-#include <stdint.h>
-#include "soc/soc.h"
-#include "soc/trng_struct.h"
-#include "hal/config.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @brief Enable or disable TRNG clock
- *
- * @param enable true to enable, false to disable
- */
-static inline void trng_ll_enable_clock(bool enable)
-{
-    LP_TRNG.date.clk_en = enable;
-}
-
-/**
- * @brief Reset TRNG module
- */
-static inline void trng_ll_reset(void)
-{
-    LP_TRNG.rstn.rstn = 0;
-    LP_TRNG.rstn.rstn = 1;
-}
-
-/**
- * @brief Enable or disable TRNG sampling
- *
- * @param enable true to enable, false to disable
- */
-static inline void trng_ll_enable_sample(bool enable)
-{
-    LP_TRNG.cfg.sample_enable = enable;
-}
-
-/**
- * @brief Set TRNG timer prescaler
- *
- * @param prescaler Timer prescaler value (0-255)
- */
-static inline void trng_ll_set_timer_prescaler(uint8_t prescaler)
-{
-    LP_TRNG.cfg.timer_pscale = prescaler;
-}
-
-/**
- * @brief Enable or disable TRNG timer XOR
- *
- * @param enable true to enable, false to disable
- */
-static inline void trng_ll_enable_timer(bool enable)
-{
-    LP_TRNG.cfg.timer_en = enable;
-}
-
-/**
- * @brief Get TRNG sample count
- *
- * @return Current sample count (0-255)
- */
-static inline uint8_t trng_ll_get_sample_count(void)
-{
-    return (uint8_t)LP_TRNG.cfg.sample_cnt;
-}
-
-/**
- * @brief Read random data from TRNG
- *
- * @return 32-bit random data
- */
-static inline uint32_t trng_ll_read_data(void)
-{
-    return LP_TRNG.data.data;
-}
-
-/**
- * @brief Enable TRNG module
- *
- * TODO: unify in trng_hal.c
- */
-static inline void trng_ll_enable(void)
-{
-    trng_ll_enable_clock(true);
-    trng_ll_reset();
-    trng_ll_enable_timer(true);
-    trng_ll_enable_sample(true);
-}
-
-/**
- * @brief Disable TRNG module
- *
- * TODO: unify in trng_hal.c
- */
-static inline void trng_ll_disable(void)
-{
-    trng_ll_enable_sample(false);
-    trng_ll_enable_timer(false);
-    trng_ll_enable_clock(false);
-}
-
-
-#ifdef __cplusplus
-}
-#endif

components/hal/esp32s2/include/hal/rng_ll.h

@@ -19,6 +19,15 @@ static inline uint32_t rng_ll_read_data(void)
     return REG_READ(WDEV_RND_REG);
 }
 
+/* For compatibility. */
+static inline void rng_ll_enable(void)
+{
+}
+
+static inline void rng_ll_disable(void)
+{
+}
+
 #ifdef __cplusplus
 }
 #endif

components/hal/esp32s3/include/hal/rng_ll.h

@@ -19,6 +19,15 @@ static inline uint32_t rng_ll_read_data(void)
     return REG_READ(WDEV_RND_REG);
 }
 
+/* For compatibility. */
+static inline void rng_ll_enable(void)
+{
+}
+
+static inline void rng_ll_disable(void)
+{
+}
+
 #ifdef __cplusplus
 }
 #endif

components/hal/esp32s31/include/hal/rng_ll.h

@@ -6,9 +6,12 @@
 
 #pragma once
 
+#include <stdbool.h>
 #include <stdint.h>
 #include "soc/soc.h"
 #include "soc/trng_reg.h"
+#include "soc/trng_struct.h"
+#include "soc/lp_peri_clkrst_struct.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -19,6 +22,80 @@ static inline uint32_t rng_ll_read_data(void)
     return REG_READ(TRNG_CRC_SYNC_DATA_REG);
 }
 
+/**
+ * @brief Enable LP RNG bus clock
+ */
+static inline void rng_ll_enable_bus_clock(bool enable)
+{
+    LP_PERI_CLKRST.rng_ctrl.lp_rng_clk_en = enable;
+}
+
+/**
+ * @brief Reset LP RNG bus clock
+ */
+static inline void rng_ll_reset(void)
+{
+    LP_PERI_CLKRST.rng_ctrl.lp_rng_rst_en = 1;
+    LP_PERI_CLKRST.rng_ctrl.lp_rng_rst_en = 0;
+}
+
+/**
+ * @brief Enable or disable RNG module clock
+ *
+ * @param enable true to enable, false to disable
+ */
+static inline void rng_ll_enable_clock(bool enable)
+{
+    LP_TRNG.date.clk_en = enable;
+}
+
+/**
+ * @brief Enable or disable RNG sampling
+ *
+ * @param enable true to enable, false to disable
+ */
+static inline void rng_ll_enable_sample(bool enable)
+{
+    LP_TRNG.conf.sample_enable = enable;
+}
+
+/**
+ * @brief Enable or disable CRC RNG source
+ *
+ * @param enable true to enable CRC RNG, false to disable
+ */
+static inline void rng_ll_enable_noise_crc(bool enable)
+{
+    LP_TRNG.conf.noise_crc_en = enable;
+}
+
+/**
+ * @brief Enable RNG module
+ *
+ * TODO: unify in rng_hal.c
+ */
+static inline void rng_ll_enable(void)
+{
+    rng_ll_enable_bus_clock(true);
+    rng_ll_reset();
+    rng_ll_enable_clock(true);
+    rng_ll_enable_sample(true);
+    rng_ll_enable_noise_crc(true);
+}
+
+/**
+ * @brief Disable RNG module
+ *
+ * TODO: unify in rng_hal.c
+ */
+static inline void rng_ll_disable(void)
+{
+    rng_ll_enable_sample(false);
+    rng_ll_enable_noise_crc(false);
+    rng_ll_enable_clock(false);
+    rng_ll_enable_bus_clock(false);
+}
+
 #ifdef __cplusplus
 }
 #endif

components/hal/esp32s31/include/hal/trng_ll.h

@@ -1,104 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-#include <stdbool.h>
-#include <stdint.h>
-#include "soc/soc.h"
-#include "soc/trng_struct.h"
-#include "soc/lp_peri_clkrst_struct.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @brief Enable LP TRNG bus clock
- */
-static inline void trng_ll_enable_bus_clock(bool enable)
-{
-    LP_PERI_CLKRST.rng_ctrl.lp_rng_clk_en = enable;
-}
-
-/**
- * @brief Reset LP TRNG bus clock
- *
- */
-static inline void trng_ll_reset(void)
-{
-    LP_PERI_CLKRST.rng_ctrl.lp_rng_rst_en = 1;
-    LP_PERI_CLKRST.rng_ctrl.lp_rng_rst_en = 0;
-}
-
-/**
- * @brief Enable or disable TRNG module clock
- *
- * @param enable true to enable, false to disable
- */
-static inline void trng_ll_enable_clock(bool enable)
-{
-    LP_TRNG.date.clk_en = enable;
-}
-
-/**
- * @brief Enable or disable TRNG sampling
- *
- * @param enable true to enable, false to disable
- */
-static inline void trng_ll_enable_sample(bool enable)
-{
-    LP_TRNG.conf.sample_enable = enable;
-}
-
-/**
- * @brief Enable or disable CRC RNG source
- *
- * @param enable true to enable CRC RNG, false to disable
- */
-static inline void trng_ll_enable_noise_crc(bool enable)
-{
-    LP_TRNG.conf.noise_crc_en = enable;
-}
-
-/**
- * @brief Read random data from TRNG
- */
-static inline uint32_t trng_ll_read_data(void)
-{
-    return LP_TRNG.crc_sync_data.sw_crc_random_data_sync;
-}
-
-/**
- * @brief Enable TRNG module
- *
- * TODO: unify in trng_hal.c
- */
-static inline void trng_ll_enable(void)
-{
-    trng_ll_enable_bus_clock(true);
-    trng_ll_reset();
-    trng_ll_enable_clock(true);
-    trng_ll_enable_sample(true);
-    trng_ll_enable_noise_crc(true);
-}
-
-/**
- * @brief Disable TRNG module
- *
- * TODO: unify in trng_hal.c
- */
-static inline void trng_ll_disable(void)
-{
-    trng_ll_enable_sample(false);
-    trng_ll_enable_noise_crc(false);
-    trng_ll_enable_clock(false);
-    trng_ll_enable_bus_clock(false);
-}
-
-#ifdef __cplusplus
-}
-#endif

components/soc/esp32c5/include/soc/Kconfig.soc_caps.in

@@ -1255,14 +1255,6 @@ config SOC_CRYPTO_DPA_PROTECTION_SUPPORTED
     bool
     default y
 
-config SOC_RNG_BUF_CHAIN_ENTROPY_SOURCE
-    bool
-    default y
-
-config SOC_RNG_RTC_TIMER_ENTROPY_SOURCE
-    bool
-    default y
-
 config SOC_UART_NUM
     int
     default 3

components/soc/esp32c5/include/soc/soc_caps.h

@@ -512,10 +512,6 @@
 /*------------------------ Anti DPA (Security) CAPS --------------------------*/
 #define SOC_CRYPTO_DPA_PROTECTION_SUPPORTED     1
 
-/*-------------------------- RNG CAPS ---------------------------------------*/
-#define SOC_RNG_BUF_CHAIN_ENTROPY_SOURCE 1
-#define SOC_RNG_RTC_TIMER_ENTROPY_SOURCE 1
-
 /*-------------------------- UART CAPS ---------------------------------------*/
 // ESP32-C5 has 3 UARTs (2 HP UART, and 1 LP UART)
 #define SOC_UART_NUM                       (3)

components/soc/esp32h4/include/soc/Kconfig.soc_caps.in

@@ -127,6 +127,10 @@ config SOC_I2C_SUPPORTED
     bool
     default y
 
+config SOC_RNG_SUPPORTED
+    bool
+    default y
+
 config SOC_SYSTIMER_SUPPORTED
     bool
     default y
@@ -1239,6 +1243,10 @@ config SOC_MODEM_CLOCK_IS_INDEPENDENT
     bool
     default y
 
+config SOC_RNG_CLOCK_IS_INDEPENDENT
+    bool
+    default y
+
 config SOC_CLK_XTAL32K_SUPPORTED
     bool
     default y

components/soc/esp32h4/include/soc/regi2c_saradc.h

@@ -1,58 +1,57 @@
 /*
  * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
- *
+*
- * SPDX-License-Identifier: Apache-2.0 OR MIT
+* SPDX-License-Identifier: Apache-2.0 OR MIT
- */
+*/
-
 #pragma once
 
-#define I2C_SAR_ADC                             0x69
+#define I2C_SAR_ADC                              0x69
-#define I2C_SAR_ADC_HOSTID                      0
+#define I2C_SAR_ADC_HOSTID                       0
 
-#define ADC_SAR1_INITIAL_CODE_LOW_ADDR          0x0
+#define ADC_SAR1_INITIAL_CODE_LOW_ADDR           0x0
-#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_MSB      0x7
+#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_MSB       0x7
-#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_LSB      0x0
+#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_LSB       0x0
 
-#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR         0x1
+#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR          0x1
-#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_MSB     0x3
+#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_MSB      0x3
-#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_LSB     0x0
+#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_LSB      0x0
 
-#define ADC_SAR1_SAMPLE_CYCLE_ADDR              0x2
+#define ADC_SAR1_SAMPLE_CYCLE_ADDR               0x2
-#define ADC_SAR1_SAMPLE_CYCLE_ADDR_MSB          0x2
+#define ADC_SAR1_SAMPLE_CYCLE_ADDR_MSB           0x2
-#define ADC_SAR1_SAMPLE_CYCLE_ADDR_LSB          0x0
+#define ADC_SAR1_SAMPLE_CYCLE_ADDR_LSB           0x0
 
-#define ADC_SAR1_DREF_ADDR                      0x2
+#define ADC_SAR1_DREF_ADDR                       0x2
-#define ADC_SAR1_DREF_ADDR_MSB                  0x6
+#define ADC_SAR1_DREF_ADDR_MSB                   0x6
-#define ADC_SAR1_DREF_ADDR_LSB                  0x4
+#define ADC_SAR1_DREF_ADDR_LSB                   0x4
 
-#define ADC_SAR2_INITIAL_CODE_LOW_ADDR          0x3
+#define ADC_SAR2_INITIAL_CODE_LOW_ADDR           0x3
-#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_MSB      0x7
+#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_MSB       0x7
-#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_LSB      0x0
+#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_LSB       0x0
 
-#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR         0x4
+#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR          0x4
-#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_MSB     0x3
+#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_MSB      0x3
-#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_LSB     0x0
+#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_LSB      0x0
 
-#define I2C_SARADC_DTEST                        0x7
+#define I2C_SARADC_TSENS_DAC                     0x6
-#define I2C_SARADC_DTEST_MSB                    0x1
+#define I2C_SARADC_TSENS_DAC_MSB                 0x3
-#define I2C_SARADC_DTEST_LSB                    0x0
+#define I2C_SARADC_TSENS_DAC_LSB                 0x0
 
-#define I2C_SARADC_ENT_SAR                      0x7
+#define I2C_SARADC_DTEST                         0x7
-#define I2C_SARADC_ENT_SAR_MSB                  0x3
+#define I2C_SARADC_DTEST_MSB                     0x1
-#define I2C_SARADC_ENT_SAR_LSB                  0x2
+#define I2C_SARADC_DTEST_LSB                     0x0
 
-#define I2C_SARADC_EN_TOUT_SAR1_BUS             0x7
+#define I2C_SARADC_ENT_SAR                       0x7
-#define I2C_SARADC_EN_TOUT_SAR1_BUS_MSB         0x5
+#define I2C_SARADC_ENT_SAR_MSB                   0x3
-#define I2C_SARADC_EN_TOUT_SAR1_BUS_LSB         0x5
+#define I2C_SARADC_ENT_SAR_LSB                   0x2
 
-#define I2C_SARADC_EN_TOUT_SAR2_BUS             0x7
+#define I2C_SARADC_SAR1_EN_TOUT                  0x8
-#define I2C_SARADC_EN_TOUT_SAR2_BUS_MSB         0x6
+#define I2C_SARADC_SAR1_EN_TOUT_MSB              0x0
-#define I2C_SARADC_EN_TOUT_SAR2_BUS_LSB         0x6
+#define I2C_SARADC_SAR1_EN_TOUT_LSB              0x0
 
-#define ADC_SAR1_ENCAL_GND_ADDR                 0x8
+#define ADC_SAR1_ENCAL_GND_ADDR                  0x8
-#define ADC_SAR1_ENCAL_GND_ADDR_MSB             0x1
+#define ADC_SAR1_ENCAL_GND_ADDR_MSB              0x1
-#define ADC_SAR1_ENCAL_GND_ADDR_LSB             0x1
+#define ADC_SAR1_ENCAL_GND_ADDR_LSB              0x1
 
-#define I2C_SARADC_TSENS_DAC                    0x6
+#define I2C_SARADC_SAR2_EN_TOUT                  0x8
-#define I2C_SARADC_TSENS_DAC_MSB                0x3
+#define I2C_SARADC_SAR2_EN_TOUT_MSB              0x2
-#define I2C_SARADC_TSENS_DAC_LSB                0x0
+#define I2C_SARADC_SAR2_EN_TOUT_LSB              0x2

components/soc/esp32h4/include/soc/soc_caps.h

@@ -64,6 +64,7 @@
 #define SOC_GPSPI_SUPPORTED             1
 #define SOC_LEDC_SUPPORTED              1
 #define SOC_I2C_SUPPORTED               1
+#define SOC_RNG_SUPPORTED               1
 #define SOC_SYSTIMER_SUPPORTED          1
 // #define SOC_SUPPORT_COEXISTENCE         1    // TODO: [ESP32H4] IDF-12251 IDF-12252 IDF-12253
 #define SOC_AES_SUPPORTED               1
@@ -523,6 +524,7 @@
 #define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION       (1)
 
 #define SOC_MODEM_CLOCK_IS_INDEPENDENT            (1)
+#define SOC_RNG_CLOCK_IS_INDEPENDENT              (1)
 
 #define SOC_CLK_XTAL32K_SUPPORTED                 (1)     /*!< Support to connect an external low frequency crystal */
 #define SOC_CLK_OSC_SLOW_SUPPORTED                (1)     /*!< Support to connect an external oscillator, not a crystal */

components/soc/esp32h4/include/soc/wdev_reg.h

@@ -9,7 +9,5 @@
 #include "soc.h"
 #include "soc/lpperi_reg.h"
 
-// TODO: [ESP32H4] IDF-12265 inherit from verify code, need check
-
 /* Hardware random number generator register */
-#define WDEV_RND_REG 0x600B0800
+#define WDEV_RND_REG RNG_DATA_SYNC_REG