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Merge branch 'feat/basic_rng_support_h4' into 'master'

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RNG support and refactor on ESP32-H4

Closes IDF-12265

See merge request espressif/esp-idf!45361
This commit is contained in:
Gao Xu
2026-05-27 11:14:38 +08:00
parent 5bcaf281e2 43317018d1
commit db3d01d412
38 changed files with 561 additions and 316 deletions
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components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
-8
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@@ -1255,14 +1255,6 @@ config SOC_CRYPTO_DPA_PROTECTION_SUPPORTED
bool
default y
config SOC_RNG_BUF_CHAIN_ENTROPY_SOURCE
bool
default y
config SOC_RNG_RTC_TIMER_ENTROPY_SOURCE
bool
default y
config SOC_UART_NUM
int
default 3
components/soc/esp32c5/include/soc/soc_caps.h
-4
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@@ -512,10 +512,6 @@
/*------------------------ Anti DPA (Security) CAPS --------------------------*/
#define SOC_CRYPTO_DPA_PROTECTION_SUPPORTED 1
/*-------------------------- RNG CAPS ---------------------------------------*/
#define SOC_RNG_BUF_CHAIN_ENTROPY_SOURCE 1
#define SOC_RNG_RTC_TIMER_ENTROPY_SOURCE 1
/*-------------------------- UART CAPS ---------------------------------------*/
// ESP32-C5 has 3 UARTs (2 HP UART, and 1 LP UART)
#define SOC_UART_NUM (3)
components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
+8
View File
@@ -127,6 +127,10 @@ config SOC_I2C_SUPPORTED
bool
default y
config SOC_RNG_SUPPORTED
bool
default y
config SOC_SYSTIMER_SUPPORTED
bool
default y
@@ -1239,6 +1243,10 @@ config SOC_MODEM_CLOCK_IS_INDEPENDENT
bool
default y
config SOC_RNG_CLOCK_IS_INDEPENDENT
bool
default y
config SOC_CLK_XTAL32K_SUPPORTED
bool
default y
components/soc/esp32h4/include/soc/regi2c_saradc.h
+41 -42
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@@ -1,58 +1,57 @@
/*
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
*/
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
*/
#pragma once
#define I2C_SAR_ADC 0x69
#define I2C_SAR_ADC_HOSTID 0
#define I2C_SAR_ADC 0x69
#define I2C_SAR_ADC_HOSTID 0
#define ADC_SAR1_INITIAL_CODE_LOW_ADDR 0x0
#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_MSB 0x7
#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_LSB 0x0
#define ADC_SAR1_INITIAL_CODE_LOW_ADDR 0x0
#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_MSB 0x7
#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_LSB 0x0
#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR 0x1
#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_MSB 0x3
#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_LSB 0x0
#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR 0x1
#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_MSB 0x3
#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_LSB 0x0
#define ADC_SAR1_SAMPLE_CYCLE_ADDR 0x2
#define ADC_SAR1_SAMPLE_CYCLE_ADDR_MSB 0x2
#define ADC_SAR1_SAMPLE_CYCLE_ADDR_LSB 0x0
#define ADC_SAR1_SAMPLE_CYCLE_ADDR 0x2
#define ADC_SAR1_SAMPLE_CYCLE_ADDR_MSB 0x2
#define ADC_SAR1_SAMPLE_CYCLE_ADDR_LSB 0x0
#define ADC_SAR1_DREF_ADDR 0x2
#define ADC_SAR1_DREF_ADDR_MSB 0x6
#define ADC_SAR1_DREF_ADDR_LSB 0x4
#define ADC_SAR1_DREF_ADDR 0x2
#define ADC_SAR1_DREF_ADDR_MSB 0x6
#define ADC_SAR1_DREF_ADDR_LSB 0x4
#define ADC_SAR2_INITIAL_CODE_LOW_ADDR 0x3
#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_MSB 0x7
#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_LSB 0x0
#define ADC_SAR2_INITIAL_CODE_LOW_ADDR 0x3
#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_MSB 0x7
#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_LSB 0x0
#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR 0x4
#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_MSB 0x3
#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_LSB 0x0
#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR 0x4
#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_MSB 0x3
#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_LSB 0x0
#define I2C_SARADC_DTEST 0x7
#define I2C_SARADC_DTEST_MSB 0x1
#define I2C_SARADC_DTEST_LSB 0x0
#define I2C_SARADC_TSENS_DAC 0x6
#define I2C_SARADC_TSENS_DAC_MSB 0x3
#define I2C_SARADC_TSENS_DAC_LSB 0x0
#define I2C_SARADC_ENT_SAR 0x7
#define I2C_SARADC_ENT_SAR_MSB 0x3
#define I2C_SARADC_ENT_SAR_LSB 0x2
#define I2C_SARADC_DTEST 0x7
#define I2C_SARADC_DTEST_MSB 0x1
#define I2C_SARADC_DTEST_LSB 0x0
#define I2C_SARADC_EN_TOUT_SAR1_BUS 0x7
#define I2C_SARADC_EN_TOUT_SAR1_BUS_MSB 0x5
#define I2C_SARADC_EN_TOUT_SAR1_BUS_LSB 0x5
#define I2C_SARADC_ENT_SAR 0x7
#define I2C_SARADC_ENT_SAR_MSB 0x3
#define I2C_SARADC_ENT_SAR_LSB 0x2
#define I2C_SARADC_EN_TOUT_SAR2_BUS 0x7
#define I2C_SARADC_EN_TOUT_SAR2_BUS_MSB 0x6
#define I2C_SARADC_EN_TOUT_SAR2_BUS_LSB 0x6
#define I2C_SARADC_SAR1_EN_TOUT 0x8
#define I2C_SARADC_SAR1_EN_TOUT_MSB 0x0
#define I2C_SARADC_SAR1_EN_TOUT_LSB 0x0
#define ADC_SAR1_ENCAL_GND_ADDR 0x8
#define ADC_SAR1_ENCAL_GND_ADDR_MSB 0x1
#define ADC_SAR1_ENCAL_GND_ADDR_LSB 0x1
#define ADC_SAR1_ENCAL_GND_ADDR 0x8
#define ADC_SAR1_ENCAL_GND_ADDR_MSB 0x1
#define ADC_SAR1_ENCAL_GND_ADDR_LSB 0x1
#define I2C_SARADC_TSENS_DAC 0x6
#define I2C_SARADC_TSENS_DAC_MSB 0x3
#define I2C_SARADC_TSENS_DAC_LSB 0x0
#define I2C_SARADC_SAR2_EN_TOUT 0x8
#define I2C_SARADC_SAR2_EN_TOUT_MSB 0x2
#define I2C_SARADC_SAR2_EN_TOUT_LSB 0x2
components/soc/esp32h4/include/soc/soc_caps.h
+2
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@@ -64,6 +64,7 @@
#define SOC_GPSPI_SUPPORTED 1
#define SOC_LEDC_SUPPORTED 1
#define SOC_I2C_SUPPORTED 1
#define SOC_RNG_SUPPORTED 1
#define SOC_SYSTIMER_SUPPORTED 1
// #define SOC_SUPPORT_COEXISTENCE 1 // TODO: [ESP32H4] IDF-12251 IDF-12252 IDF-12253
#define SOC_AES_SUPPORTED 1
@@ -523,6 +524,7 @@
#define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION (1)
#define SOC_MODEM_CLOCK_IS_INDEPENDENT (1)
#define SOC_RNG_CLOCK_IS_INDEPENDENT (1)
#define SOC_CLK_XTAL32K_SUPPORTED (1) /*!< Support to connect an external low frequency crystal */
#define SOC_CLK_OSC_SLOW_SUPPORTED (1) /*!< Support to connect an external oscillator, not a crystal */
components/soc/esp32h4/include/soc/wdev_reg.h
+1 -3
View File
@@ -9,7 +9,5 @@
#include "soc.h"
#include "soc/lpperi_reg.h"
// TODO: [ESP32H4] IDF-12265 inherit from verify code, need check
/* Hardware random number generator register */
#define WDEV_RND_REG 0x600B0800
#define WDEV_RND_REG RNG_DATA_SYNC_REG