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fix(esp_rom): fix RTC_SLEEP_MODE_REG addr mismatch

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This commit is contained in:
hebinglin
2026-05-21 15:31:34 +08:00
parent 8f3d8b41c3
commit db3cf7c792
3 changed files with 7 additions and 7 deletions
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components/esp_rom/esp32c5/include/esp32c5/rom/rtc.h
+2 -2
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@@ -50,8 +50,8 @@ extern "C" {
* LP_AON_STORE5_REG FAST_RTC_MEMORY_LENGTH * LP_AON_STORE5_REG FAST_RTC_MEMORY_LENGTH
* LP_AON_STORE6_REG FAST_RTC_MEMORY_ENTRY * LP_AON_STORE6_REG FAST_RTC_MEMORY_ENTRY
* LP_AON_STORE7_REG FAST_RTC_MEMORY_CRC * LP_AON_STORE7_REG FAST_RTC_MEMORY_CRC
* LP_AON_STORE8_REG Store light sleep wake stub addr * LP_AON_STORE8_REG Store light sleep wake stub addr (mask bit[1:0])
* LP_AON_STORE9_REG Store the sleep mode at bit[0] (0:light sleep 1:deep sleep) * LP_AON_STORE8_REG Store the sleep mode at bit[0] (0:light sleep 1:deep sleep)
************************************************************************************* *************************************************************************************
*/ */
components/esp_rom/esp32c61/include/esp32c61/rom/rtc.h
+2 -2
View File
@@ -51,8 +51,8 @@ extern "C" {
* LP_AON_STORE5_REG FAST_RTC_MEMORY_LENGTH * LP_AON_STORE5_REG FAST_RTC_MEMORY_LENGTH
* LP_AON_STORE6_REG FAST_RTC_MEMORY_ENTRY * LP_AON_STORE6_REG FAST_RTC_MEMORY_ENTRY
* LP_AON_STORE7_REG RTC fix us, low 32 bits * LP_AON_STORE7_REG RTC fix us, low 32 bits
* LP_AON_STORE8_REG Store light sleep wake stub addr * LP_AON_STORE8_REG Store light sleep wake stub addr (mask bit[1:0])
* LP_AON_STORE9_REG Store the sleep mode at bit[0] (0:light sleep 1:deep sleep) * LP_AON_STORE8_REG Store the sleep mode at bit[0] (0:light sleep 1:deep sleep)
************************************************************************************* *************************************************************************************
* *
* Since esp32c61 does not support RTC mem, so use LP_AON store regs to record rtc time: * Since esp32c61 does not support RTC mem, so use LP_AON store regs to record rtc time:
components/esp_rom/esp32h4/include/esp32h4/rom/rtc.h
+3 -3
View File
@@ -50,8 +50,8 @@ extern "C" {
* LP_AON_STORE5_REG FAST_RTC_MEMORY_LENGTH * LP_AON_STORE5_REG FAST_RTC_MEMORY_LENGTH
* LP_AON_STORE6_REG FAST_RTC_MEMORY_ENTRY * LP_AON_STORE6_REG FAST_RTC_MEMORY_ENTRY
* LP_AON_STORE7_REG RTC fix us, low 32 bits * LP_AON_STORE7_REG RTC fix us, low 32 bits
* LP_AON_STORE8_REG Store light sleep wake stub addr * LP_AON_STORE8_REG Store light sleep wake stub addr (mask bit[1:0])
* LP_AON_STORE9_REG Store the sleep mode at bit[0] (0:light sleep 1:deep sleep) * LP_AON_STORE8_REG Store the sleep mode at bit[0] (0:light sleep 1:deep sleep)
************************************************************************************* *************************************************************************************
* *
* Since esp32h4 does not support RTC mem, so use LP_AON store regs to record rtc time: * Since esp32h4 does not support RTC mem, so use LP_AON store regs to record rtc time:
@@ -70,7 +70,7 @@ extern "C" {
#define RTC_RESET_CAUSE_REG LP_AON_STORE6_REG #define RTC_RESET_CAUSE_REG LP_AON_STORE6_REG
#define RTC_FIX_US_LOW_REG LP_AON_STORE7_REG #define RTC_FIX_US_LOW_REG LP_AON_STORE7_REG
#define RTC_SLEEP_WAKE_STUB_ADDR_REG LP_AON_STORE8_REG #define RTC_SLEEP_WAKE_STUB_ADDR_REG LP_AON_STORE8_REG
#define RTC_SLEEP_MODE_REG LP_AON_STORE9_REG #define RTC_SLEEP_MODE_REG LP_AON_STORE8_REG
#define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) //!< Disable logging from the ROM code. #define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) //!< Disable logging from the ROM code.