diff --git a/components/esp_driver_mcpwm/CMakeLists.txt b/components/esp_driver_mcpwm/CMakeLists.txt index 59ca835ce91..dac9ef409af 100644 --- a/components/esp_driver_mcpwm/CMakeLists.txt +++ b/components/esp_driver_mcpwm/CMakeLists.txt @@ -11,6 +11,9 @@ if(CONFIG_SOC_MCPWM_SUPPORTED) "src/mcpwm_oper.c" "src/mcpwm_sync.c" "src/mcpwm_timer.c") + if(CONFIG_SOC_PAU_SUPPORTED AND CONFIG_SOC_MCPWM_SUPPORT_SLEEP_RETENTION) + list(APPEND srcs "${target}/mcpwm_retention.c") + endif() if(CONFIG_SOC_MCPWM_SUPPORT_ETM) list(APPEND srcs "src/mcpwm_etm.c") endif() @@ -25,7 +28,8 @@ endif() idf_component_register(SRCS ${srcs} INCLUDE_DIRS ${public_include} + PRIV_INCLUDE_DIRS "src" REQUIRES "${requires}" PRIV_REQUIRES "${priv_requires}" LDFRAGMENTS "linker.lf" - ) + ) diff --git a/components/esp_driver_mcpwm/esp32c5/mcpwm_retention.c b/components/esp_driver_mcpwm/esp32c5/mcpwm_retention.c new file mode 100644 index 00000000000..64253fa239e --- /dev/null +++ b/components/esp_driver_mcpwm/esp32c5/mcpwm_retention.c @@ -0,0 +1,57 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/soc.h" +#include "soc/mcpwm_reg.h" +#include "mcpwm_private.h" + +/** + * MCPWM Registers to be saved during sleep retention + * - Timer Configuration registers, e.g.: MCPWM_TIMER_SYNCI_CFG_REG, MCPWM_TIMER0_CFG0_REG, MCPWM_TIMER0_CFG1_REG + * - Operator Configuration registers, e.g.: MCPWM_OPERATOR_TIMERSEL_REG + * |- Generator Configuration registers, e.g.: MCPWM_GEN0_STMP_CFG_REG, MCPWM_GEN0_TSTMP_A_REG, MCPWM_GEN0_TSTMP_B_REG, MCPWM_GEN0_CFG0_REG, MCPWM_GEN0_FORCE_REG, MCPWM_GEN0_A_REG, MCPWM_GEN0_B_REG + * |- Dead Time Configuration registers, e.g.: MCPWM_DT0_CFG_REG, MCPWM_DT0_FED_CFG_REG, MCPWM_DT0_RED_CFG_REG + * |- Carrier Configuration registers, e.g.: MCPWM_CARRIER0_CFG_REG + * └- Fault Handle Configuration registers, e.g.: MCPWM_FAULT_DETECT_REG, MCPWM_FH0_CFG0_REG, MCPWM_FH0_CFG1_REG + * - Capture Timer Configuration registers, e.g.: MCPWM_CAP_TIMER_CFG_REG, MCPWM_CAP_TIMER_PHASE_REG, MCPWM_CAP_CH0_CFG_REG, MCPWM_CAP_CH1_CFG_REG, MCPWM_CAP_CH2_CFG_REG + * - Interrupt enable registers, e.g.: MCPWM_INT_ENA_REG + * - ETM Configurations, e.g.: MCPWM_EVT_EN_REG, MCPWM_EVT_EN2_REG, MCPWM_TASK_EN_REG, MCPWM_OP0_TSTMP_E1_REG, MCPWM_OP0_TSTMP_E2_REG, MCPWM_OP1_TSTMP_E1_REG, MCPWM_OP1_TSTMP_E2_REG, MCPWM_OP2_TSTMP_E1_REG, MCPWM_OP2_TSTMP_E2_REG + * - Misc Configurations, e.g.: MCPWM_UPDATE_CFG_REG + */ +#define MCPWM_RETENTION_REGS_CNT 67 +#define MCPWM_RETENTION_REGS_BASE (DR_REG_MCPWM_BASE + 0x4) +static const uint32_t mcpwm_regs_map[4] = {0xf7fff777, 0x3f7ffdff, 0xff8c, 0x0}; +static const regdma_entries_config_t mcpwm_regs_retention[] = { + // backup stage: save configuration registers + // restore stage: restore the configuration registers + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_MCPWM_LINK(0x00), + MCPWM_RETENTION_REGS_BASE, MCPWM_RETENTION_REGS_BASE, + MCPWM_RETENTION_REGS_CNT, 0, 0, + mcpwm_regs_map[0], mcpwm_regs_map[1], + mcpwm_regs_map[2], mcpwm_regs_map[3]), + .owner = ENTRY(0) | ENTRY(2) + }, + // restore stage: trigger a forced update of all active registers + [1] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x01), + MCPWM_UPDATE_CFG_REG(0), MCPWM_GLOBAL_FORCE_UP, MCPWM_GLOBAL_FORCE_UP_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [2] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x02), + MCPWM_UPDATE_CFG_REG(0), 0, MCPWM_GLOBAL_FORCE_UP_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, +}; + +const mcpwm_retention_desc_t mcpwm_retention_infos[1] = { + [0] = { + .regdma_entry_array = mcpwm_regs_retention, + .array_size = ARRAY_SIZE(mcpwm_regs_retention), + .retention_module = SLEEP_RETENTION_MODULE_MCPWM0 + }, +}; diff --git a/components/esp_driver_mcpwm/esp32c6/mcpwm_retention.c b/components/esp_driver_mcpwm/esp32c6/mcpwm_retention.c new file mode 100644 index 00000000000..405a71b3a42 --- /dev/null +++ b/components/esp_driver_mcpwm/esp32c6/mcpwm_retention.c @@ -0,0 +1,57 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/soc.h" +#include "soc/mcpwm_reg.h" +#include "mcpwm_private.h" + +/** + * MCPWM Registers to be saved during sleep retention + * - Timer Configuration registers, e.g.: MCPWM_TIMER_SYNCI_CFG_REG, MCPWM_TIMER0_CFG0_REG, MCPWM_TIMER0_CFG1_REG + * - Operator Configuration registers, e.g.: MCPWM_OPERATOR_TIMERSEL_REG + * |- Generator Configuration registers, e.g.: MCPWM_GEN0_STMP_CFG_REG, MCPWM_GEN0_TSTMP_A_REG, MCPWM_GEN0_TSTMP_B_REG, MCPWM_GEN0_CFG0_REG, MCPWM_GEN0_FORCE_REG, MCPWM_GEN0_A_REG, MCPWM_GEN0_B_REG + * |- Dead Time Configuration registers, e.g.: MCPWM_DT0_CFG_REG, MCPWM_DT0_FED_CFG_REG, MCPWM_DT0_RED_CFG_REG + * |- Carrier Configuration registers, e.g.: MCPWM_CARRIER0_CFG_REG + * └- Fault Handle Configuration registers, e.g.: MCPWM_FAULT_DETECT_REG, MCPWM_FH0_CFG0_REG, MCPWM_FH0_CFG1_REG + * - Capture Timer Configuration registers, e.g.: MCPWM_CAP_TIMER_CFG_REG, MCPWM_CAP_TIMER_PHASE_REG, MCPWM_CAP_CH0_CFG_REG, MCPWM_CAP_CH1_CFG_REG, MCPWM_CAP_CH2_CFG_REG + * - Interrupt enable registers, e.g.: MCPWM_INT_ENA_REG + * - ETM Configurations, e.g.: MCPWM_EVT_EN_REG, MCPWM_TASK_EN_REG + * - Misc Configurations, e.g.: MCPWM_UPDATE_CFG_REG + */ +#define MCPWM_RETENTION_REGS_CNT 60 +#define MCPWM_RETENTION_REGS_BASE (DR_REG_MCPWM_BASE + 0x4) +static const uint32_t mcpwm_regs_map[4] = {0xf7fff777, 0x3f7ffdff, 0x18c, 0x0}; +static const regdma_entries_config_t mcpwm_regs_retention[] = { + // backup stage: save configuration registers + // restore stage: restore the configuration registers + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_MCPWM_LINK(0x00), + MCPWM_RETENTION_REGS_BASE, MCPWM_RETENTION_REGS_BASE, + MCPWM_RETENTION_REGS_CNT, 0, 0, + mcpwm_regs_map[0], mcpwm_regs_map[1], + mcpwm_regs_map[2], mcpwm_regs_map[3]), + .owner = ENTRY(0) | ENTRY(2) + }, + // restore stage: trigger a forced update of all active registers + [1] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x01), + MCPWM_UPDATE_CFG_REG(0), MCPWM_GLOBAL_FORCE_UP, MCPWM_GLOBAL_FORCE_UP_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [2] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x02), + MCPWM_UPDATE_CFG_REG(0), 0, MCPWM_GLOBAL_FORCE_UP_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, +}; + +const mcpwm_retention_desc_t mcpwm_retention_infos[1] = { + [0] = { + .regdma_entry_array = mcpwm_regs_retention, + .array_size = ARRAY_SIZE(mcpwm_regs_retention), + .retention_module = SLEEP_RETENTION_MODULE_MCPWM0 + }, +}; diff --git a/components/esp_driver_mcpwm/esp32h2/mcpwm_retention.c b/components/esp_driver_mcpwm/esp32h2/mcpwm_retention.c new file mode 100644 index 00000000000..a6a925e2e00 --- /dev/null +++ b/components/esp_driver_mcpwm/esp32h2/mcpwm_retention.c @@ -0,0 +1,56 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/mcpwm_reg.h" +#include "mcpwm_private.h" + +/** + * MCPWM Registers to be saved during sleep retention + * - Timer Configuration registers, e.g.: MCPWM_TIMER_SYNCI_CFG_REG, MCPWM_TIMER0_CFG0_REG, MCPWM_TIMER0_CFG1_REG + * - Operator Configuration registers, e.g.: MCPWM_OPERATOR_TIMERSEL_REG + * |- Generator Configuration registers, e.g.: MCPWM_GEN0_STMP_CFG_REG, MCPWM_GEN0_TSTMP_A_REG, MCPWM_GEN0_TSTMP_B_REG, MCPWM_GEN0_CFG0_REG, MCPWM_GEN0_FORCE_REG, MCPWM_GEN0_A_REG, MCPWM_GEN0_B_REG + * |- Dead Time Configuration registers, e.g.: MCPWM_DT0_CFG_REG, MCPWM_DT0_FED_CFG_REG, MCPWM_DT0_RED_CFG_REG + * |- Carrier Configuration registers, e.g.: MCPWM_CARRIER0_CFG_REG + * └- Fault Handle Configuration registers, e.g.: MCPWM_FAULT_DETECT_REG, MCPWM_FH0_CFG0_REG, MCPWM_FH0_CFG1_REG + * - Capture Timer Configuration registers, e.g.: MCPWM_CAP_TIMER_CFG_REG, MCPWM_CAP_TIMER_PHASE_REG, MCPWM_CAP_CH0_CFG_REG, MCPWM_CAP_CH1_CFG_REG, MCPWM_CAP_CH2_CFG_REG + * - Interrupt enable registers, e.g.: MCPWM_INT_ENA_REG + * - ETM Configurations, e.g.: MCPWM_EVT_EN_REG, MCPWM_TASK_EN_REG + * - Misc Configurations, e.g.: MCPWM_UPDATE_CFG_REG + */ +#define MCPWM_RETENTION_REGS_CNT 60 +#define MCPWM_RETENTION_REGS_BASE (DR_REG_MCPWM_BASE + 0x4) +static const uint32_t mcpwm_regs_map[4] = {0xf7fff777, 0x3f7ffdff, 0x18c, 0x0}; +static const regdma_entries_config_t mcpwm_regs_retention[] = { + // backup stage: save configuration registers + // restore stage: restore the configuration registers + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_MCPWM_LINK(0x00), + MCPWM_RETENTION_REGS_BASE, MCPWM_RETENTION_REGS_BASE, + MCPWM_RETENTION_REGS_CNT, 0, 0, + mcpwm_regs_map[0], mcpwm_regs_map[1], + mcpwm_regs_map[2], mcpwm_regs_map[3]), + .owner = ENTRY(0) | ENTRY(2) + }, + // restore stage: trigger a forced update of all active registers + [1] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x01), + MCPWM_UPDATE_CFG_REG, MCPWM_GLOBAL_FORCE_UP, MCPWM_GLOBAL_FORCE_UP_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [2] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x02), + MCPWM_UPDATE_CFG_REG, 0, MCPWM_GLOBAL_FORCE_UP_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, +}; + +const mcpwm_retention_desc_t mcpwm_retention_infos[1] = { + [0] = { + .regdma_entry_array = mcpwm_regs_retention, + .array_size = ARRAY_SIZE(mcpwm_regs_retention), + .retention_module = SLEEP_RETENTION_MODULE_MCPWM0 + }, +}; diff --git a/components/esp_driver_mcpwm/esp32h21/mcpwm_retention.c b/components/esp_driver_mcpwm/esp32h21/mcpwm_retention.c new file mode 100644 index 00000000000..a6a925e2e00 --- /dev/null +++ b/components/esp_driver_mcpwm/esp32h21/mcpwm_retention.c @@ -0,0 +1,56 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/mcpwm_reg.h" +#include "mcpwm_private.h" + +/** + * MCPWM Registers to be saved during sleep retention + * - Timer Configuration registers, e.g.: MCPWM_TIMER_SYNCI_CFG_REG, MCPWM_TIMER0_CFG0_REG, MCPWM_TIMER0_CFG1_REG + * - Operator Configuration registers, e.g.: MCPWM_OPERATOR_TIMERSEL_REG + * |- Generator Configuration registers, e.g.: MCPWM_GEN0_STMP_CFG_REG, MCPWM_GEN0_TSTMP_A_REG, MCPWM_GEN0_TSTMP_B_REG, MCPWM_GEN0_CFG0_REG, MCPWM_GEN0_FORCE_REG, MCPWM_GEN0_A_REG, MCPWM_GEN0_B_REG + * |- Dead Time Configuration registers, e.g.: MCPWM_DT0_CFG_REG, MCPWM_DT0_FED_CFG_REG, MCPWM_DT0_RED_CFG_REG + * |- Carrier Configuration registers, e.g.: MCPWM_CARRIER0_CFG_REG + * └- Fault Handle Configuration registers, e.g.: MCPWM_FAULT_DETECT_REG, MCPWM_FH0_CFG0_REG, MCPWM_FH0_CFG1_REG + * - Capture Timer Configuration registers, e.g.: MCPWM_CAP_TIMER_CFG_REG, MCPWM_CAP_TIMER_PHASE_REG, MCPWM_CAP_CH0_CFG_REG, MCPWM_CAP_CH1_CFG_REG, MCPWM_CAP_CH2_CFG_REG + * - Interrupt enable registers, e.g.: MCPWM_INT_ENA_REG + * - ETM Configurations, e.g.: MCPWM_EVT_EN_REG, MCPWM_TASK_EN_REG + * - Misc Configurations, e.g.: MCPWM_UPDATE_CFG_REG + */ +#define MCPWM_RETENTION_REGS_CNT 60 +#define MCPWM_RETENTION_REGS_BASE (DR_REG_MCPWM_BASE + 0x4) +static const uint32_t mcpwm_regs_map[4] = {0xf7fff777, 0x3f7ffdff, 0x18c, 0x0}; +static const regdma_entries_config_t mcpwm_regs_retention[] = { + // backup stage: save configuration registers + // restore stage: restore the configuration registers + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_MCPWM_LINK(0x00), + MCPWM_RETENTION_REGS_BASE, MCPWM_RETENTION_REGS_BASE, + MCPWM_RETENTION_REGS_CNT, 0, 0, + mcpwm_regs_map[0], mcpwm_regs_map[1], + mcpwm_regs_map[2], mcpwm_regs_map[3]), + .owner = ENTRY(0) | ENTRY(2) + }, + // restore stage: trigger a forced update of all active registers + [1] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x01), + MCPWM_UPDATE_CFG_REG, MCPWM_GLOBAL_FORCE_UP, MCPWM_GLOBAL_FORCE_UP_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, + [2] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x02), + MCPWM_UPDATE_CFG_REG, 0, MCPWM_GLOBAL_FORCE_UP_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2) + }, +}; + +const mcpwm_retention_desc_t mcpwm_retention_infos[1] = { + [0] = { + .regdma_entry_array = mcpwm_regs_retention, + .array_size = ARRAY_SIZE(mcpwm_regs_retention), + .retention_module = SLEEP_RETENTION_MODULE_MCPWM0 + }, +}; diff --git a/components/esp_driver_mcpwm/esp32h4/mcpwm_retention.c b/components/esp_driver_mcpwm/esp32h4/mcpwm_retention.c new file mode 100644 index 00000000000..69a7a4a6bdb --- /dev/null +++ b/components/esp_driver_mcpwm/esp32h4/mcpwm_retention.c @@ -0,0 +1,85 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/mcpwm_reg.h" +#include "mcpwm_private.h" + +/** + * MCPWM Registers to be saved during sleep retention + * - Timer Configuration registers, e.g.: MCPWM_TIMER_SYNCI_CFG_REG, MCPWM_TIMER0_CFG0_REG, MCPWM_TIMER0_CFG1_REG，MCPWM_TIMER0_SYNC_REG + * - Operator Configuration registers, e.g.: MCPWM_OPERATOR_TIMERSEL_REG + * |- Generator Configuration registers, e.g.: MCPWM_GEN0_STMP_CFG_REG, MCPWM_GEN0_TSTMP_A_REG, MCPWM_GEN0_TSTMP_B_REG, MCPWM_GEN0_CFG0_REG, MCPWM_GEN0_FORCE_REG, MCPWM_GEN0_A_REG, MCPWM_GEN0_B_REG + * |- Dead Time Configuration registers, e.g.: MCPWM_DT0_CFG_REG, MCPWM_DT0_FED_CFG_REG, MCPWM_DT0_RED_CFG_REG + * |- Carrier Configuration registers, e.g.: MCPWM_CARRIER0_CFG_REG + * └- Fault Handle Configuration registers, e.g.: MCPWM_FAULT_DETECT_REG, MCPWM_FH0_CFG0_REG, MCPWM_FH0_CFG1_REG + * - Capture Timer Configuration registers, e.g.: MCPWM_CAP_TIMER_CFG_REG, MCPWM_CAP_TIMER_PHASE_REG, MCPWM_CAP_CH0_CFG_REG, MCPWM_CAP_CH1_CFG_REG, MCPWM_CAP_CH2_CFG_REG + * - Interrupt enable registers, e.g.: MCPWM_INT_ENA_REG + * - ETM Configurations, e.g.: MCPWM_EVT_EN_REG, MCPWM_EVT_EN2_REG, MCPWM_TASK_EN_REG, MCPWM_OP0_TSTMP_E1_REG, MCPWM_OP0_TSTMP_E2_REG, MCPWM_OP1_TSTMP_E1_REG, MCPWM_OP1_TSTMP_E2_REG, MCPWM_OP2_TSTMP_E1_REG, MCPWM_OP2_TSTMP_E2_REG + * - Misc Configurations, e.g.: MCPWM_UPDATE_CFG_REG + */ + +#define MCPWM_RETENTION_REGS_CNT 67 +#define MCPWM_RETENTION_REGS_BASE(i) DR_REG_MCPWM_BASE(i) +static const uint32_t mcpwm_regs_map[4] = {0xf7fff777, 0x3f7ffdff, 0xff8c, 0x0}; +static const regdma_entries_config_t mcpwm0_regdma_entries[] = { + // backup stage: save configuration registers + // restore stage: restore the configuration registers + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_MCPWM_LINK(0x00), + MCPWM_RETENTION_REGS_BASE(0), MCPWM_RETENTION_REGS_BASE(0), + MCPWM_RETENTION_REGS_CNT, 0, 0, + mcpwm_regs_map[0], mcpwm_regs_map[1], + mcpwm_regs_map[2], mcpwm_regs_map[3]), + .owner = ENTRY(0) | ENTRY(2), + }, + // restore stage: trigger a forced update of all active registers + [1] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x01), + MCPWM_UPDATE_CFG_REG(0), MCPWM_GLOBAL_FORCE_UP, MCPWM_GLOBAL_FORCE_UP_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2), + }, + [2] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x02), + MCPWM_UPDATE_CFG_REG(0), 0, MCPWM_GLOBAL_FORCE_UP_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2), + }, +}; +static const regdma_entries_config_t mcpwm1_regdma_entries[] = { + // backup stage: save configuration registers + // restore stage: restore the configuration registers + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_MCPWM_LINK(0x00), + MCPWM_RETENTION_REGS_BASE(1), MCPWM_RETENTION_REGS_BASE(1), + MCPWM_RETENTION_REGS_CNT, 0, 0, + mcpwm_regs_map[0], mcpwm_regs_map[1], + mcpwm_regs_map[2], mcpwm_regs_map[3]), + .owner = ENTRY(0) | ENTRY(2), + }, + // restore stage: trigger a forced update of all active registers + [1] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x01), + MCPWM_UPDATE_CFG_REG(1), MCPWM_GLOBAL_FORCE_UP, MCPWM_GLOBAL_FORCE_UP_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2), + }, + [2] = { + .config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x02), + MCPWM_UPDATE_CFG_REG(1), 0, MCPWM_GLOBAL_FORCE_UP_M, 1, 0), + .owner = ENTRY(0) | ENTRY(2), + }, +}; + +const mcpwm_retention_desc_t mcpwm_retention_infos[2] = { + [0] = { + .regdma_entry_array = mcpwm0_regdma_entries, + .array_size = ARRAY_SIZE(mcpwm0_regdma_entries), + .retention_module = SLEEP_RETENTION_MODULE_MCPWM0 + }, + [1] = { + .regdma_entry_array = mcpwm1_regdma_entries, + .array_size = ARRAY_SIZE(mcpwm1_regdma_entries), + .retention_module = SLEEP_RETENTION_MODULE_MCPWM1 + }, +}; diff --git a/components/esp_driver_mcpwm/esp32p4/mcpwm_retention.c b/components/esp_driver_mcpwm/esp32p4/mcpwm_retention.c new file mode 100644 index 00000000000..83301c60e92 --- /dev/null +++ b/components/esp_driver_mcpwm/esp32p4/mcpwm_retention.c @@ -0,0 +1,61 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/soc.h" +#include "soc/mcpwm_reg.h" +#include "mcpwm_private.h" + +/** + * MCPWM Registers to be saved during sleep retention + * - Timer Configuration registers, e.g.: MCPWM_TIMER_SYNCI_CFG_REG, MCPWM_TIMER0_CFG0_REG, MCPWM_TIMER0_CFG1_REG + * - Operator Configuration registers, e.g.: MCPWM_OPERATOR_TIMERSEL_REG + * |- Generator Configuration registers, e.g.: MCPWM_GEN0_STMP_CFG_REG, MCPWM_GEN0_TSTMP_A_REG, MCPWM_GEN0_TSTMP_B_REG, MCPWM_GEN0_CFG0_REG, MCPWM_GEN0_FORCE_REG, MCPWM_GEN0_A_REG, MCPWM_GEN0_B_REG + * |- Dead Time Configuration registers, e.g.: MCPWM_DT0_CFG_REG, MCPWM_DT0_FED_CFG_REG, MCPWM_DT0_RED_CFG_REG + * |- Carrier Configuration registers, e.g.: MCPWM_CARRIER0_CFG_REG + * └- Fault Handle Configuration registers, e.g.: MCPWM_FAULT_DETECT_REG, MCPWM_FH0_CFG0_REG, MCPWM_FH0_CFG1_REG + * - Capture Timer Configuration registers, e.g.: MCPWM_CAP_TIMER_CFG_REG, MCPWM_CAP_TIMER_PHASE_REG, MCPWM_CAP_CH0_CFG_REG, MCPWM_CAP_CH1_CFG_REG, MCPWM_CAP_CH2_CFG_REG + * - Interrupt enable registers, e.g.: MCPWM_INT_ENA_REG + * - ETM Configurations, e.g.: MCPWM_EVT_EN_REG, MCPWM_TASK_EN_REG + * - Misc Configurations, e.g.: MCPWM_UPDATE_CFG_REG + */ +#define MCPWM_RETENTION_REGS_CNT 67 +#define MCPWM_RETENTION_REGS_BASE(i) (REG_MCPWM_BASE(i) + 0x4) +static const uint32_t mcpwm_regs_map[4] = {0xf7fff777, 0x3f7ffdff, 0xff8c, 0x0}; +#define MCPWM_SLEEP_RETENTION_ENTRIES(mcpwm_port) { \ + /* backup stage: save configuration registers \ + restore stage: restore the configuration registers */ \ + [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT( \ + REGDMA_MCPWM_LINK(0x00), \ + MCPWM_RETENTION_REGS_BASE(mcpwm_port), \ + MCPWM_RETENTION_REGS_BASE(mcpwm_port), \ + MCPWM_RETENTION_REGS_CNT, 0, 0, \ + mcpwm_regs_map[0], mcpwm_regs_map[1], \ + mcpwm_regs_map[2], mcpwm_regs_map[3]), \ + .owner = ENTRY(0)}, \ + /* restore stage: trigger a forced update of all active registers*/ \ + [1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x01), \ + MCPWM_UPDATE_CFG_REG(mcpwm_port), MCPWM_GLOBAL_FORCE_UP, MCPWM_GLOBAL_FORCE_UP_M, 1, 0), \ + .owner = ENTRY(0) }, \ + [2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x02), \ + MCPWM_UPDATE_CFG_REG(mcpwm_port), 0, MCPWM_GLOBAL_FORCE_UP_M, 1, 0), \ + .owner = ENTRY(0) }, \ +}; + +static const regdma_entries_config_t mcpwm0_regs_retention[] = MCPWM_SLEEP_RETENTION_ENTRIES(0); +static const regdma_entries_config_t mcpwm1_regs_retention[] = MCPWM_SLEEP_RETENTION_ENTRIES(1); + +const mcpwm_retention_desc_t mcpwm_retention_infos[2] = { + [0] = { + .regdma_entry_array = mcpwm0_regs_retention, + .array_size = ARRAY_SIZE(mcpwm0_regs_retention), + .retention_module = SLEEP_RETENTION_MODULE_MCPWM0 + }, + [1] = { + .regdma_entry_array = mcpwm1_regs_retention, + .array_size = ARRAY_SIZE(mcpwm1_regs_retention), + .retention_module = SLEEP_RETENTION_MODULE_MCPWM1 + }, +}; diff --git a/components/esp_driver_mcpwm/esp32s31/mcpwm_retention.c b/components/esp_driver_mcpwm/esp32s31/mcpwm_retention.c new file mode 100644 index 00000000000..b2705970f4e --- /dev/null +++ b/components/esp_driver_mcpwm/esp32s31/mcpwm_retention.c @@ -0,0 +1,73 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/soc.h" +#include "soc/mcpwm_reg.h" +#include "mcpwm_private.h" + +/** + * MCPWM Registers to be saved during sleep retention + * - Timer Configuration registers, e.g.: MCPWM_TIMER_SYNCI_CFG_REG, MCPWM_TIMER0_CFG0_REG, MCPWM_TIMER0_CFG1_REG, MCPWM_TIMER0_CFG2_REG, MCPWM_TIMER0_CFG3_REG + * - Operator Configuration registers, e.g.: MCPWM_OPERATOR_TIMERSEL_REG + * |- Generator Configuration registers, e.g.: MCPWM_GEN0_STMP_CFG_REG, MCPWM_GEN0_TSTMP_A_REG, MCPWM_GEN0_TSTMP_B_REG, MCPWM_GEN0_CFG0_REG, MCPWM_GEN0_FORCE_REG, MCPWM_GEN0_A_REG, MCPWM_GEN0_B_REG + * |- Dead Time Configuration registers, e.g.: MCPWM_DT0_CFG_REG, MCPWM_DT0_FED_CFG_REG, MCPWM_DT0_RED_CFG_REG + * |- Carrier Configuration registers, e.g.: MCPWM_CARRIER0_CFG_REG + * └- Fault Handle Configuration registers, e.g.: MCPWM_FAULT_DETECT_REG, MCPWM_FH0_CFG0_REG, MCPWM_FH0_CFG1_REG + * - Capture Timer Configuration registers, e.g.: MCPWM_CAP_TIMER_CFG_REG, MCPWM_CAP_TIMER_PHASE_REG, MCPWM_CAP_CH0_CFG_REG, MCPWM_CAP_CH1_CFG_REG, MCPWM_CAP_CH2_CFG_REG + * - Interrupt enable registers, e.g.: MCPWM_INT_ENA_REG + * - ETM Configurations, e.g.: MCPWM_EVT_EN_REG, MCPWM_TASK_EN_REG + * - Misc Configurations, e.g.: MCPWM_UPDATE_CFG_REG + */ +#define MCPWM_RETENTION_REGS_CNT 73 +#define MCPWM_RETENTION_REGS_BASE(i) REG_MCPWM_BASE(i) +static const uint32_t mcpwm_regs_map[4] = {0xf7fff777, 0x3f7ffdff, 0x1f8ff8c, 0x0}; +#define MCPWM_SLEEP_RETENTION_ENTRIES(mcpwm_port) { \ + /* backup stage: save configuration registers \ + restore stage: restore the configuration registers */ \ + [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT( \ + REGDMA_MCPWM_LINK(0x00), \ + MCPWM_RETENTION_REGS_BASE(mcpwm_port), \ + MCPWM_RETENTION_REGS_BASE(mcpwm_port), \ + MCPWM_RETENTION_REGS_CNT, 0, 0, \ + mcpwm_regs_map[0], mcpwm_regs_map[1], \ + mcpwm_regs_map[2], mcpwm_regs_map[3]), \ + .owner = ENTRY(0) | ENTRY(2)}, \ + /* restore stage: trigger a forced update of all active registers*/ \ + [1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x01), \ + MCPWM_UPDATE_CFG_REG(mcpwm_port), MCPWM_GLOBAL_FORCE_UP, MCPWM_GLOBAL_FORCE_UP_M, 1, 0), \ + .owner = ENTRY(0) | ENTRY(2) }, \ + [2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x02), \ + MCPWM_UPDATE_CFG_REG(mcpwm_port), 0, MCPWM_GLOBAL_FORCE_UP_M, 1, 0), \ + .owner = ENTRY(0) | ENTRY(2) }, \ +}; + +static const regdma_entries_config_t mcpwm0_regs_retention[] = MCPWM_SLEEP_RETENTION_ENTRIES(0); +static const regdma_entries_config_t mcpwm1_regs_retention[] = MCPWM_SLEEP_RETENTION_ENTRIES(1); +static const regdma_entries_config_t mcpwm2_regs_retention[] = MCPWM_SLEEP_RETENTION_ENTRIES(2); +static const regdma_entries_config_t mcpwm3_regs_retention[] = MCPWM_SLEEP_RETENTION_ENTRIES(3); + +const mcpwm_retention_desc_t mcpwm_retention_infos[4] = { + [0] = { + .regdma_entry_array = mcpwm0_regs_retention, + .array_size = ARRAY_SIZE(mcpwm0_regs_retention), + .retention_module = SLEEP_RETENTION_MODULE_MCPWM0 + }, + [1] = { + .regdma_entry_array = mcpwm1_regs_retention, + .array_size = ARRAY_SIZE(mcpwm1_regs_retention), + .retention_module = SLEEP_RETENTION_MODULE_MCPWM1 + }, + [2] = { + .regdma_entry_array = mcpwm2_regs_retention, + .array_size = ARRAY_SIZE(mcpwm2_regs_retention), + .retention_module = SLEEP_RETENTION_MODULE_MCPWM2 + }, + [3] = { + .regdma_entry_array = mcpwm3_regs_retention, + .array_size = ARRAY_SIZE(mcpwm3_regs_retention), + .retention_module = SLEEP_RETENTION_MODULE_MCPWM3 + }, +}; diff --git a/components/esp_driver_mcpwm/src/mcpwm_com.c b/components/esp_driver_mcpwm/src/mcpwm_com.c index 2c186c726b6..3c4ccb69cbe 100644 --- a/components/esp_driver_mcpwm/src/mcpwm_com.c +++ b/components/esp_driver_mcpwm/src/mcpwm_com.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -37,7 +37,7 @@ mcpwm_group_t *mcpwm_acquire_group_handle(int group_id) group->group_id = group_id; group->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED; #if MCPWM_USE_RETENTION_LINK - sleep_retention_module_t module = mcpwm_reg_retention_info[group_id].retention_module; + sleep_retention_module_t module = mcpwm_retention_infos[group_id].retention_module; sleep_retention_module_init_param_t init_param = { .cbs = { .create = { @@ -113,7 +113,7 @@ void mcpwm_release_group_handle(mcpwm_group_t *group) } #endif #if MCPWM_USE_RETENTION_LINK - const periph_retention_module_t module_id = mcpwm_reg_retention_info[group_id].retention_module; + const periph_retention_module_t module_id = mcpwm_retention_infos[group_id].retention_module; if (sleep_retention_is_module_created(module_id)) { sleep_retention_module_free(module_id); } @@ -248,16 +248,16 @@ static esp_err_t mcpwm_create_sleep_retention_link_cb(void *arg) { mcpwm_group_t *group = (mcpwm_group_t *)arg; int group_id = group->group_id; - sleep_retention_module_t module_id = mcpwm_reg_retention_info[group_id].retention_module; - esp_err_t err = sleep_retention_entries_create(mcpwm_reg_retention_info[group_id].regdma_entry_array, - mcpwm_reg_retention_info[group_id].array_size, + sleep_retention_module_t module_id = mcpwm_retention_infos[group_id].retention_module; + esp_err_t err = sleep_retention_entries_create(mcpwm_retention_infos[group_id].regdma_entry_array, + mcpwm_retention_infos[group_id].array_size, REGDMA_LINK_PRI_MCPWM, module_id); return err; } void mcpwm_create_retention_module(mcpwm_group_t *group) { int group_id = group->group_id; - sleep_retention_module_t module_id = mcpwm_reg_retention_info[group_id].retention_module; + sleep_retention_module_t module_id = mcpwm_retention_infos[group_id].retention_module; _lock_acquire(&s_platform.mutex); if (sleep_retention_is_module_inited(module_id) && !sleep_retention_is_module_created(module_id)) { if (sleep_retention_module_allocate(module_id) != ESP_OK) { diff --git a/components/esp_driver_mcpwm/src/mcpwm_private.h b/components/esp_driver_mcpwm/src/mcpwm_private.h index 20b82a59110..7f3079e159d 100644 --- a/components/esp_driver_mcpwm/src/mcpwm_private.h +++ b/components/esp_driver_mcpwm/src/mcpwm_private.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -50,6 +50,16 @@ extern "C" { // Use retention link only when the target supports sleep retention is enabled #define MCPWM_USE_RETENTION_LINK (SOC_MCPWM_SUPPORT_SLEEP_RETENTION && CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP) +#if SOC_MCPWM_SUPPORT_SLEEP_RETENTION +typedef struct { + const regdma_entries_config_t *regdma_entry_array; + uint32_t array_size; + const periph_retention_module_t retention_module; +} mcpwm_retention_desc_t; + +extern const mcpwm_retention_desc_t mcpwm_retention_infos[MCPWM_LL_GET(GROUP_NUM)]; +#endif // SOC_MCPWM_SUPPORT_SLEEP_RETENTION + #define MCPWM_ALLOW_INTR_PRIORITY_MASK ESP_INTR_FLAG_LOWMED #define MCPWM_GROUP_CLOCK_DEFAULT_PRESCALE 1 diff --git a/components/esp_hal_mcpwm/esp32/mcpwm_periph.c b/components/esp_hal_mcpwm/esp32/mcpwm_periph.c index 12bf896c679..05b3dd78300 100644 --- a/components/esp_hal_mcpwm/esp32/mcpwm_periph.c +++ b/components/esp_hal_mcpwm/esp32/mcpwm_periph.c @@ -1,13 +1,12 @@ /* - * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -#include "soc/soc.h" -#include "hal/mcpwm_ll.h" #include "hal/mcpwm_periph.h" #include "soc/gpio_sig_map.h" +#include "soc/interrupts.h" const soc_mcpwm_signal_desc_t soc_mcpwm_signals[2] = { { diff --git a/components/esp_hal_mcpwm/esp32c5/mcpwm_periph.c b/components/esp_hal_mcpwm/esp32c5/mcpwm_periph.c index 0b93feefa58..c41e961ed53 100644 --- a/components/esp_hal_mcpwm/esp32c5/mcpwm_periph.c +++ b/components/esp_hal_mcpwm/esp32c5/mcpwm_periph.c @@ -1,13 +1,12 @@ /* - * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -#include "soc/soc.h" #include "hal/mcpwm_periph.h" -#include "soc/mcpwm_reg.h" #include "soc/gpio_sig_map.h" +#include "soc/interrupts.h" const soc_mcpwm_signal_desc_t soc_mcpwm_signals[1] = { { @@ -81,51 +80,3 @@ const soc_mcpwm_signal_desc_t soc_mcpwm_signals[1] = { } }; - -/** - * MCPWM Registers to be saved during sleep retention - * - Timer Configuration registers, e.g.: MCPWM_TIMER_SYNCI_CFG_REG, MCPWM_TIMER0_CFG0_REG, MCPWM_TIMER0_CFG1_REG - * - Operator Configuration registers, e.g.: MCPWM_OPERATOR_TIMERSEL_REG - * |- Generator Configuration registers, e.g.: MCPWM_GEN0_STMP_CFG_REG, MCPWM_GEN0_TSTMP_A_REG, MCPWM_GEN0_TSTMP_B_REG, MCPWM_GEN0_CFG0_REG, MCPWM_GEN0_FORCE_REG, MCPWM_GEN0_A_REG, MCPWM_GEN0_B_REG - * |- Dead Time Configuration registers, e.g.: MCPWM_DT0_CFG_REG, MCPWM_DT0_FED_CFG_REG, MCPWM_DT0_RED_CFG_REG - * |- Carrier Configuration registers, e.g.: MCPWM_CARRIER0_CFG_REG - * └- Fault Handle Configuration registers, e.g.: MCPWM_FAULT_DETECT_REG, MCPWM_FH0_CFG0_REG, MCPWM_FH0_CFG1_REG - * - Capture Timer Configuration registers, e.g.: MCPWM_CAP_TIMER_CFG_REG, MCPWM_CAP_TIMER_PHASE_REG, MCPWM_CAP_CH0_CFG_REG, MCPWM_CAP_CH1_CFG_REG, MCPWM_CAP_CH2_CFG_REG - * - Interrupt enable registers, e.g.: MCPWM_INT_ENA_REG - * - ETM Configurations, e.g.: MCPWM_EVT_EN_REG, MCPWM_EVT_EN2_REG, MCPWM_TASK_EN_REG, MCPWM_OP0_TSTMP_E1_REG, MCPWM_OP0_TSTMP_E2_REG, MCPWM_OP1_TSTMP_E1_REG, MCPWM_OP1_TSTMP_E2_REG, MCPWM_OP2_TSTMP_E1_REG, MCPWM_OP2_TSTMP_E2_REG - * - Misc Configurations, e.g.: MCPWM_UPDATE_CFG_REG -*/ -#define MCPWM_RETENTION_REGS_CNT 67 -#define MCPWM_RETENTION_REGS_BASE (DR_REG_MCPWM_BASE + 0x4) -static const uint32_t mcpwm_regs_map[4] = {0xf7fff777, 0x3f7ffdff, 0xff8c, 0x0}; -static const regdma_entries_config_t mcpwm_regs_retention[] = { - // backup stage: save configuration registers - // restore stage: restore the configuration registers - [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_MCPWM_LINK(0x00), - MCPWM_RETENTION_REGS_BASE, MCPWM_RETENTION_REGS_BASE, - MCPWM_RETENTION_REGS_CNT, 0, 0, - mcpwm_regs_map[0], mcpwm_regs_map[1], - mcpwm_regs_map[2], mcpwm_regs_map[3]), - .owner = ENTRY(0) | ENTRY(2) - }, - // restore stage: trigger a forced update of all active registers - [1] = { - .config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x01), - MCPWM_UPDATE_CFG_REG(0), MCPWM_GLOBAL_FORCE_UP, MCPWM_GLOBAL_FORCE_UP_M, 1, 0), - .owner = ENTRY(0) | ENTRY(2) - }, - [2] = { - .config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x02), - MCPWM_UPDATE_CFG_REG(0), 0, MCPWM_GLOBAL_FORCE_UP_M, 1, 0), - .owner = ENTRY(0) | ENTRY(2) - }, -}; - -const mcpwm_reg_retention_info_t mcpwm_reg_retention_info[1] = { - [0] = { - .regdma_entry_array = mcpwm_regs_retention, - .array_size = ARRAY_SIZE(mcpwm_regs_retention), - .retention_module = SLEEP_RETENTION_MODULE_MCPWM0 - }, -}; diff --git a/components/esp_hal_mcpwm/esp32c6/mcpwm_periph.c b/components/esp_hal_mcpwm/esp32c6/mcpwm_periph.c index 7075283d1bd..1da0e10b28e 100644 --- a/components/esp_hal_mcpwm/esp32c6/mcpwm_periph.c +++ b/components/esp_hal_mcpwm/esp32c6/mcpwm_periph.c @@ -1,13 +1,12 @@ /* - * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -#include "soc/soc.h" #include "hal/mcpwm_periph.h" -#include "soc/mcpwm_reg.h" #include "soc/gpio_sig_map.h" +#include "soc/interrupts.h" const soc_mcpwm_signal_desc_t soc_mcpwm_signals[1] = { { @@ -80,51 +79,3 @@ const soc_mcpwm_signal_desc_t soc_mcpwm_signals[1] = { } } }; - -/** - * MCPWM Registers to be saved during sleep retention - * - Timer Configuration registers, e.g.: MCPWM_TIMER_SYNCI_CFG_REG, MCPWM_TIMER0_CFG0_REG, MCPWM_TIMER0_CFG1_REG - * - Operator Configuration registers, e.g.: MCPWM_OPERATOR_TIMERSEL_REG - * |- Generator Configuration registers, e.g.: MCPWM_GEN0_STMP_CFG_REG, MCPWM_GEN0_TSTMP_A_REG, MCPWM_GEN0_TSTMP_B_REG, MCPWM_GEN0_CFG0_REG, MCPWM_GEN0_FORCE_REG, MCPWM_GEN0_A_REG, MCPWM_GEN0_B_REG - * |- Dead Time Configuration registers, e.g.: MCPWM_DT0_CFG_REG, MCPWM_DT0_FED_CFG_REG, MCPWM_DT0_RED_CFG_REG - * |- Carrier Configuration registers, e.g.: MCPWM_CARRIER0_CFG_REG - * └- Fault Handle Configuration registers, e.g.: MCPWM_FAULT_DETECT_REG, MCPWM_FH0_CFG0_REG, MCPWM_FH0_CFG1_REG - * - Capture Timer Configuration registers, e.g.: MCPWM_CAP_TIMER_CFG_REG, MCPWM_CAP_TIMER_PHASE_REG, MCPWM_CAP_CH0_CFG_REG, MCPWM_CAP_CH1_CFG_REG, MCPWM_CAP_CH2_CFG_REG - * - Interrupt enable registers, e.g.: MCPWM_INT_ENA_REG - * - ETM Configurations, e.g.: MCPWM_EVT_EN_REG, MCPWM_TASK_EN_REG - * - Misc Configurations, e.g.: MCPWM_UPDATE_CFG_REG -*/ -#define MCPWM_RETENTION_REGS_CNT 60 -#define MCPWM_RETENTION_REGS_BASE (DR_REG_MCPWM_BASE + 0x4) -static const uint32_t mcpwm_regs_map[4] = {0xf7fff777, 0x3f7ffdff, 0x18c, 0x0}; -static const regdma_entries_config_t mcpwm_regs_retention[] = { - // backup stage: save configuration registers - // restore stage: restore the configuration registers - [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_MCPWM_LINK(0x00), - MCPWM_RETENTION_REGS_BASE, MCPWM_RETENTION_REGS_BASE, - MCPWM_RETENTION_REGS_CNT, 0, 0, - mcpwm_regs_map[0], mcpwm_regs_map[1], - mcpwm_regs_map[2], mcpwm_regs_map[3]), - .owner = ENTRY(0) | ENTRY(2) - }, - // restore stage: trigger a forced update of all active registers - [1] = { - .config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x01), - MCPWM_UPDATE_CFG_REG(0), MCPWM_GLOBAL_FORCE_UP, MCPWM_GLOBAL_FORCE_UP_M, 1, 0), - .owner = ENTRY(0) | ENTRY(2) - }, - [2] = { - .config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x02), - MCPWM_UPDATE_CFG_REG(0), 0, MCPWM_GLOBAL_FORCE_UP_M, 1, 0), - .owner = ENTRY(0) | ENTRY(2) - }, -}; - -const mcpwm_reg_retention_info_t mcpwm_reg_retention_info[1] = { - [0] = { - .regdma_entry_array = mcpwm_regs_retention, - .array_size = ARRAY_SIZE(mcpwm_regs_retention), - .retention_module = SLEEP_RETENTION_MODULE_MCPWM0 - }, -}; diff --git a/components/esp_hal_mcpwm/esp32h2/mcpwm_periph.c b/components/esp_hal_mcpwm/esp32h2/mcpwm_periph.c index 4d2752c18cf..1da0e10b28e 100644 --- a/components/esp_hal_mcpwm/esp32h2/mcpwm_periph.c +++ b/components/esp_hal_mcpwm/esp32h2/mcpwm_periph.c @@ -1,12 +1,12 @@ /* - * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #include "hal/mcpwm_periph.h" -#include "soc/mcpwm_reg.h" #include "soc/gpio_sig_map.h" +#include "soc/interrupts.h" const soc_mcpwm_signal_desc_t soc_mcpwm_signals[1] = { { @@ -79,51 +79,3 @@ const soc_mcpwm_signal_desc_t soc_mcpwm_signals[1] = { } } }; - -/** - * MCPWM Registers to be saved during sleep retention - * - Timer Configuration registers, e.g.: MCPWM_TIMER_SYNCI_CFG_REG, MCPWM_TIMER0_CFG0_REG, MCPWM_TIMER0_CFG1_REG - * - Operator Configuration registers, e.g.: MCPWM_OPERATOR_TIMERSEL_REG - * |- Generator Configuration registers, e.g.: MCPWM_GEN0_STMP_CFG_REG, MCPWM_GEN0_TSTMP_A_REG, MCPWM_GEN0_TSTMP_B_REG, MCPWM_GEN0_CFG0_REG, MCPWM_GEN0_FORCE_REG, MCPWM_GEN0_A_REG, MCPWM_GEN0_B_REG - * |- Dead Time Configuration registers, e.g.: MCPWM_DT0_CFG_REG, MCPWM_DT0_FED_CFG_REG, MCPWM_DT0_RED_CFG_REG - * |- Carrier Configuration registers, e.g.: MCPWM_CARRIER0_CFG_REG - * └- Fault Handle Configuration registers, e.g.: MCPWM_FAULT_DETECT_REG, MCPWM_FH0_CFG0_REG, MCPWM_FH0_CFG1_REG - * - Capture Timer Configuration registers, e.g.: MCPWM_CAP_TIMER_CFG_REG, MCPWM_CAP_TIMER_PHASE_REG, MCPWM_CAP_CH0_CFG_REG, MCPWM_CAP_CH1_CFG_REG, MCPWM_CAP_CH2_CFG_REG - * - Interrupt enable registers, e.g.: MCPWM_INT_ENA_REG - * - ETM Configurations, e.g.: MCPWM_EVT_EN_REG, MCPWM_TASK_EN_REG - * - Misc Configurations, e.g.: MCPWM_UPDATE_CFG_REG -*/ -#define MCPWM_RETENTION_REGS_CNT 60 -#define MCPWM_RETENTION_REGS_BASE (DR_REG_MCPWM_BASE + 0x4) -static const uint32_t mcpwm_regs_map[4] = {0xf7fff777, 0x3f7ffdff, 0x18c, 0x0}; -static const regdma_entries_config_t mcpwm_regs_retention[] = { - // backup stage: save configuration registers - // restore stage: restore the configuration registers - [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_MCPWM_LINK(0x00), - MCPWM_RETENTION_REGS_BASE, MCPWM_RETENTION_REGS_BASE, - MCPWM_RETENTION_REGS_CNT, 0, 0, - mcpwm_regs_map[0], mcpwm_regs_map[1], - mcpwm_regs_map[2], mcpwm_regs_map[3]), - .owner = ENTRY(0) | ENTRY(2) - }, - // restore stage: trigger a forced update of all active registers - [1] = { - .config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x01), - MCPWM_UPDATE_CFG_REG, MCPWM_GLOBAL_FORCE_UP, MCPWM_GLOBAL_FORCE_UP_M, 1, 0), - .owner = ENTRY(0) | ENTRY(2) - }, - [2] = { - .config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x02), - MCPWM_UPDATE_CFG_REG, 0, MCPWM_GLOBAL_FORCE_UP_M, 1, 0), - .owner = ENTRY(0) | ENTRY(2) - }, -}; - -const mcpwm_reg_retention_info_t mcpwm_reg_retention_info[1] = { - [0] = { - .regdma_entry_array = mcpwm_regs_retention, - .array_size = ARRAY_SIZE(mcpwm_regs_retention), - .retention_module = SLEEP_RETENTION_MODULE_MCPWM0 - }, -}; diff --git a/components/esp_hal_mcpwm/esp32h21/mcpwm_periph.c b/components/esp_hal_mcpwm/esp32h21/mcpwm_periph.c index df73fd37a84..39ee9fcb4d0 100644 --- a/components/esp_hal_mcpwm/esp32h21/mcpwm_periph.c +++ b/components/esp_hal_mcpwm/esp32h21/mcpwm_periph.c @@ -1,12 +1,12 @@ /* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #include "hal/mcpwm_periph.h" -#include "soc/mcpwm_reg.h" #include "soc/gpio_sig_map.h" +#include "soc/interrupts.h" const soc_mcpwm_signal_desc_t soc_mcpwm_signals[1] = { { @@ -79,51 +79,3 @@ const soc_mcpwm_signal_desc_t soc_mcpwm_signals[1] = { } } }; - -/** - * MCPWM Registers to be saved during sleep retention - * - Timer Configuration registers, e.g.: MCPWM_TIMER_SYNCI_CFG_REG, MCPWM_TIMER0_CFG0_REG, MCPWM_TIMER0_CFG1_REG - * - Operator Configuration registers, e.g.: MCPWM_OPERATOR_TIMERSEL_REG - * |- Generator Configuration registers, e.g.: MCPWM_GEN0_STMP_CFG_REG, MCPWM_GEN0_TSTMP_A_REG, MCPWM_GEN0_TSTMP_B_REG, MCPWM_GEN0_CFG0_REG, MCPWM_GEN0_FORCE_REG, MCPWM_GEN0_A_REG, MCPWM_GEN0_B_REG - * |- Dead Time Configuration registers, e.g.: MCPWM_DT0_CFG_REG, MCPWM_DT0_FED_CFG_REG, MCPWM_DT0_RED_CFG_REG - * |- Carrier Configuration registers, e.g.: MCPWM_CARRIER0_CFG_REG - * └- Fault Handle Configuration registers, e.g.: MCPWM_FAULT_DETECT_REG, MCPWM_FH0_CFG0_REG, MCPWM_FH0_CFG1_REG - * - Capture Timer Configuration registers, e.g.: MCPWM_CAP_TIMER_CFG_REG, MCPWM_CAP_TIMER_PHASE_REG, MCPWM_CAP_CH0_CFG_REG, MCPWM_CAP_CH1_CFG_REG, MCPWM_CAP_CH2_CFG_REG - * - Interrupt enable registers, e.g.: MCPWM_INT_ENA_REG - * - ETM Configurations, e.g.: MCPWM_EVT_EN_REG, MCPWM_TASK_EN_REG - * - Misc Configurations, e.g.: MCPWM_UPDATE_CFG_REG -*/ -#define MCPWM_RETENTION_REGS_CNT 60 -#define MCPWM_RETENTION_REGS_BASE (DR_REG_MCPWM_BASE + 0x4) -static const uint32_t mcpwm_regs_map[4] = {0xf7fff777, 0x3f7ffdff, 0x18c, 0x0}; -static const regdma_entries_config_t mcpwm_regs_retention[] = { - // backup stage: save configuration registers - // restore stage: restore the configuration registers - [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_MCPWM_LINK(0x00), - MCPWM_RETENTION_REGS_BASE, MCPWM_RETENTION_REGS_BASE, - MCPWM_RETENTION_REGS_CNT, 0, 0, - mcpwm_regs_map[0], mcpwm_regs_map[1], - mcpwm_regs_map[2], mcpwm_regs_map[3]), - .owner = ENTRY(0) | ENTRY(2) - }, - // restore stage: trigger a forced update of all active registers - [1] = { - .config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x01), - MCPWM_UPDATE_CFG_REG, MCPWM_GLOBAL_FORCE_UP, MCPWM_GLOBAL_FORCE_UP_M, 1, 0), - .owner = ENTRY(0) | ENTRY(2) - }, - [2] = { - .config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x02), - MCPWM_UPDATE_CFG_REG, 0, MCPWM_GLOBAL_FORCE_UP_M, 1, 0), - .owner = ENTRY(0) | ENTRY(2) - }, -}; - -const mcpwm_reg_retention_info_t mcpwm_reg_retention_info[1] = { - [0] = { - .regdma_entry_array = mcpwm_regs_retention, - .array_size = ARRAY_SIZE(mcpwm_regs_retention), - .retention_module = SLEEP_RETENTION_MODULE_MCPWM0 - }, -}; diff --git a/components/esp_hal_mcpwm/esp32h4/mcpwm_periph.c b/components/esp_hal_mcpwm/esp32h4/mcpwm_periph.c index 073f6393cba..960865ac469 100644 --- a/components/esp_hal_mcpwm/esp32h4/mcpwm_periph.c +++ b/components/esp_hal_mcpwm/esp32h4/mcpwm_periph.c @@ -6,7 +6,6 @@ #include "soc/interrupts.h" #include "hal/mcpwm_periph.h" -#include "soc/mcpwm_reg.h" #include "soc/gpio_sig_map.h" const soc_mcpwm_signal_desc_t soc_mcpwm_signals[2] = { @@ -149,82 +148,3 @@ const soc_mcpwm_signal_desc_t soc_mcpwm_signals[2] = { } } }; - -#if SOC_MCPWM_SUPPORT_SLEEP_RETENTION -/** - * MCPWM Registers to be saved during sleep retention - * - Timer Configuration registers, e.g.: MCPWM_TIMER_SYNCI_CFG_REG, MCPWM_TIMER0_CFG0_REG, MCPWM_TIMER0_CFG1_REG，MCPWM_TIMER0_SYNC_REG - * - Operator Configuration registers, e.g.: MCPWM_OPERATOR_TIMERSEL_REG - * |- Generator Configuration registers, e.g.: MCPWM_GEN0_STMP_CFG_REG, MCPWM_GEN0_TSTMP_A_REG, MCPWM_GEN0_TSTMP_B_REG, MCPWM_GEN0_CFG0_REG, MCPWM_GEN0_FORCE_REG, MCPWM_GEN0_A_REG, MCPWM_GEN0_B_REG - * |- Dead Time Configuration registers, e.g.: MCPWM_DT0_CFG_REG, MCPWM_DT0_FED_CFG_REG, MCPWM_DT0_RED_CFG_REG - * |- Carrier Configuration registers, e.g.: MCPWM_CARRIER0_CFG_REG - * └- Fault Handle Configuration registers, e.g.: MCPWM_FAULT_DETECT_REG, MCPWM_FH0_CFG0_REG, MCPWM_FH0_CFG1_REG - * - Capture Timer Configuration registers, e.g.: MCPWM_CAP_TIMER_CFG_REG, MCPWM_CAP_TIMER_PHASE_REG, MCPWM_CAP_CH0_CFG_REG, MCPWM_CAP_CH1_CFG_REG, MCPWM_CAP_CH2_CFG_REG - * - Interrupt enable registers, e.g.: MCPWM_INT_ENA_REG - * - ETM Configurations, e.g.: MCPWM_EVT_EN_REG, MCPWM_EVT_EN2_REG, MCPWM_TASK_EN_REG, MCPWM_OP0_TSTMP_E1_REG, MCPWM_OP0_TSTMP_E2_REG, MCPWM_OP1_TSTMP_E1_REG, MCPWM_OP1_TSTMP_E2_REG, MCPWM_OP2_TSTMP_E1_REG, MCPWM_OP2_TSTMP_E2_REG - * - Misc Configurations, e.g.: MCPWM_UPDATE_CFG_REG -*/ - -#define MCPWM_RETENTION_REGS_CNT 67 -#define MCPWM_RETENTION_REGS_BASE(i) DR_REG_MCPWM_BASE(i) -static const uint32_t mcpwm_regs_map[4] = {0xf7fff777, 0x3f7ffdff, 0xff8c, 0x0}; -static const regdma_entries_config_t mcpwm0_regdma_entries[] = { - // backup stage: save configuration registers - // restore stage: restore the configuration registers - [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_MCPWM_LINK(0x00), - MCPWM_RETENTION_REGS_BASE(0), MCPWM_RETENTION_REGS_BASE(0), - MCPWM_RETENTION_REGS_CNT, 0, 0, - mcpwm_regs_map[0], mcpwm_regs_map[1], - mcpwm_regs_map[2], mcpwm_regs_map[3]), - .owner = ENTRY(0) | ENTRY(2), - }, - // restore stage: trigger a forced update of all active registers - [1] = { - .config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x01), - MCPWM_UPDATE_CFG_REG(0), MCPWM_GLOBAL_FORCE_UP, MCPWM_GLOBAL_FORCE_UP_M, 1, 0), - .owner = ENTRY(0) | ENTRY(2), - }, - [2] = { - .config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x02), - MCPWM_UPDATE_CFG_REG(0), 0, MCPWM_GLOBAL_FORCE_UP_M, 1, 0), - .owner = ENTRY(0) | ENTRY(2), - }, -}; -static const regdma_entries_config_t mcpwm1_regdma_entries[] = { - // backup stage: save configuration registers - // restore stage: restore the configuration registers - [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_MCPWM_LINK(0x00), - MCPWM_RETENTION_REGS_BASE(1), MCPWM_RETENTION_REGS_BASE(1), - MCPWM_RETENTION_REGS_CNT, 0, 0, - mcpwm_regs_map[0], mcpwm_regs_map[1], - mcpwm_regs_map[2], mcpwm_regs_map[3]), - .owner = ENTRY(0) | ENTRY(2), - }, - // restore stage: trigger a forced update of all active registers - [1] = { - .config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x01), - MCPWM_UPDATE_CFG_REG(1), MCPWM_GLOBAL_FORCE_UP, MCPWM_GLOBAL_FORCE_UP_M, 1, 0), - .owner = ENTRY(0) | ENTRY(2), - }, - [2] = { - .config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x02), - MCPWM_UPDATE_CFG_REG(1), 0, MCPWM_GLOBAL_FORCE_UP_M, 1, 0), - .owner = ENTRY(0) | ENTRY(2), - }, -}; - -const mcpwm_reg_retention_info_t mcpwm_reg_retention_info[2] = { - [0] = { - .regdma_entry_array = mcpwm0_regdma_entries, - .array_size = ARRAY_SIZE(mcpwm0_regdma_entries), - .retention_module = SLEEP_RETENTION_MODULE_MCPWM0 - }, - [1] = { - .regdma_entry_array = mcpwm1_regdma_entries, - .array_size = ARRAY_SIZE(mcpwm1_regdma_entries), - .retention_module = SLEEP_RETENTION_MODULE_MCPWM1 - }, -}; -#endif // SOC_MCPWM_SUPPORT_SLEEP_RETENTION diff --git a/components/esp_hal_mcpwm/esp32p4/mcpwm_periph.c b/components/esp_hal_mcpwm/esp32p4/mcpwm_periph.c index c76f1c1b292..3fe94772f21 100644 --- a/components/esp_hal_mcpwm/esp32p4/mcpwm_periph.c +++ b/components/esp_hal_mcpwm/esp32p4/mcpwm_periph.c @@ -1,13 +1,12 @@ /* - * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -#include "soc/soc.h" #include "hal/mcpwm_periph.h" -#include "soc/mcpwm_reg.h" #include "soc/gpio_sig_map.h" +#include "soc/interrupts.h" const soc_mcpwm_signal_desc_t soc_mcpwm_signals[2] = { { @@ -149,57 +148,3 @@ const soc_mcpwm_signal_desc_t soc_mcpwm_signals[2] = { } } }; - -#if SOC_MCPWM_SUPPORT_SLEEP_RETENTION -/** - * MCPWM Registers to be saved during sleep retention - * - Timer Configuration registers, e.g.: MCPWM_TIMER_SYNCI_CFG_REG, MCPWM_TIMER0_CFG0_REG, MCPWM_TIMER0_CFG1_REG - * - Operator Configuration registers, e.g.: MCPWM_OPERATOR_TIMERSEL_REG - * |- Generator Configuration registers, e.g.: MCPWM_GEN0_STMP_CFG_REG, MCPWM_GEN0_TSTMP_A_REG, MCPWM_GEN0_TSTMP_B_REG, MCPWM_GEN0_CFG0_REG, MCPWM_GEN0_FORCE_REG, MCPWM_GEN0_A_REG, MCPWM_GEN0_B_REG - * |- Dead Time Configuration registers, e.g.: MCPWM_DT0_CFG_REG, MCPWM_DT0_FED_CFG_REG, MCPWM_DT0_RED_CFG_REG - * |- Carrier Configuration registers, e.g.: MCPWM_CARRIER0_CFG_REG - * └- Fault Handle Configuration registers, e.g.: MCPWM_FAULT_DETECT_REG, MCPWM_FH0_CFG0_REG, MCPWM_FH0_CFG1_REG - * - Capture Timer Configuration registers, e.g.: MCPWM_CAP_TIMER_CFG_REG, MCPWM_CAP_TIMER_PHASE_REG, MCPWM_CAP_CH0_CFG_REG, MCPWM_CAP_CH1_CFG_REG, MCPWM_CAP_CH2_CFG_REG - * - Interrupt enable registers, e.g.: MCPWM_INT_ENA_REG - * - ETM Configurations, e.g.: MCPWM_EVT_EN_REG, MCPWM_TASK_EN_REG - * - Misc Configurations, e.g.: MCPWM_UPDATE_CFG_REG -*/ -#define MCPWM_RETENTION_REGS_CNT 67 -#define MCPWM_RETENTION_REGS_BASE(i) (REG_MCPWM_BASE(i) + 0x4) -static const uint32_t mcpwm_regs_map[4] = {0xf7fff777, 0x3f7ffdff, 0xff8c, 0x0}; -#define MCPWM_SLEEP_RETENTION_ENTRIES(mcpwm_port) { \ - /* backup stage: save configuration registers \ - restore stage: restore the configuration registers */ \ - [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT( \ - REGDMA_MCPWM_LINK(0x00), \ - MCPWM_RETENTION_REGS_BASE(mcpwm_port), \ - MCPWM_RETENTION_REGS_BASE(mcpwm_port), \ - MCPWM_RETENTION_REGS_CNT, 0, 0, \ - mcpwm_regs_map[0], mcpwm_regs_map[1], \ - mcpwm_regs_map[2], mcpwm_regs_map[3]), \ - .owner = ENTRY(0)}, \ - /* restore stage: trigger a forced update of all active registers*/ \ - [1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x01), \ - MCPWM_UPDATE_CFG_REG(mcpwm_port), MCPWM_GLOBAL_FORCE_UP, MCPWM_GLOBAL_FORCE_UP_M, 1, 0), \ - .owner = ENTRY(0) }, \ - [2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x02), \ - MCPWM_UPDATE_CFG_REG(mcpwm_port), 0, MCPWM_GLOBAL_FORCE_UP_M, 1, 0), \ - .owner = ENTRY(0) }, \ -}; - -static const regdma_entries_config_t mcpwm0_regs_retention[] = MCPWM_SLEEP_RETENTION_ENTRIES(0); -static const regdma_entries_config_t mcpwm1_regs_retention[] = MCPWM_SLEEP_RETENTION_ENTRIES(1); - -const mcpwm_reg_retention_info_t mcpwm_reg_retention_info[2] = { - [0] = { - .regdma_entry_array = mcpwm0_regs_retention, - .array_size = ARRAY_SIZE(mcpwm0_regs_retention), - .retention_module = SLEEP_RETENTION_MODULE_MCPWM0 - }, - [1] = { - .regdma_entry_array = mcpwm1_regs_retention, - .array_size = ARRAY_SIZE(mcpwm1_regs_retention), - .retention_module = SLEEP_RETENTION_MODULE_MCPWM1 - }, -}; -#endif //SOC_MCPWM_SUPPORT_SLEEP_RETENTION diff --git a/components/esp_hal_mcpwm/esp32s3/mcpwm_periph.c b/components/esp_hal_mcpwm/esp32s3/mcpwm_periph.c index e722d13e160..05b3dd78300 100644 --- a/components/esp_hal_mcpwm/esp32s3/mcpwm_periph.c +++ b/components/esp_hal_mcpwm/esp32s3/mcpwm_periph.c @@ -1,12 +1,12 @@ /* - * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -#include "soc/soc.h" #include "hal/mcpwm_periph.h" #include "soc/gpio_sig_map.h" +#include "soc/interrupts.h" const soc_mcpwm_signal_desc_t soc_mcpwm_signals[2] = { { diff --git a/components/esp_hal_mcpwm/esp32s31/mcpwm_periph.c b/components/esp_hal_mcpwm/esp32s31/mcpwm_periph.c index 93b2366e438..05a92148ab7 100644 --- a/components/esp_hal_mcpwm/esp32s31/mcpwm_periph.c +++ b/components/esp_hal_mcpwm/esp32s31/mcpwm_periph.c @@ -4,10 +4,9 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include "soc/soc.h" #include "hal/mcpwm_periph.h" -#include "soc/mcpwm_reg.h" #include "soc/gpio_sig_map.h" +#include "soc/interrupts.h" const soc_mcpwm_signal_desc_t soc_mcpwm_signals[4] = { { @@ -287,69 +286,3 @@ const soc_mcpwm_signal_desc_t soc_mcpwm_signals[4] = { } } }; - -#if SOC_MCPWM_SUPPORT_SLEEP_RETENTION -/** - * MCPWM Registers to be saved during sleep retention - * - Timer Configuration registers, e.g.: MCPWM_TIMER_SYNCI_CFG_REG, MCPWM_TIMER0_CFG0_REG, MCPWM_TIMER0_CFG1_REG, MCPWM_TIMER0_CFG2_REG, MCPWM_TIMER0_CFG3_REG - * - Operator Configuration registers, e.g.: MCPWM_OPERATOR_TIMERSEL_REG - * |- Generator Configuration registers, e.g.: MCPWM_GEN0_STMP_CFG_REG, MCPWM_GEN0_TSTMP_A_REG, MCPWM_GEN0_TSTMP_B_REG, MCPWM_GEN0_CFG0_REG, MCPWM_GEN0_FORCE_REG, MCPWM_GEN0_A_REG, MCPWM_GEN0_B_REG - * |- Dead Time Configuration registers, e.g.: MCPWM_DT0_CFG_REG, MCPWM_DT0_FED_CFG_REG, MCPWM_DT0_RED_CFG_REG - * |- Carrier Configuration registers, e.g.: MCPWM_CARRIER0_CFG_REG - * └- Fault Handle Configuration registers, e.g.: MCPWM_FAULT_DETECT_REG, MCPWM_FH0_CFG0_REG, MCPWM_FH0_CFG1_REG - * - Capture Timer Configuration registers, e.g.: MCPWM_CAP_TIMER_CFG_REG, MCPWM_CAP_TIMER_PHASE_REG, MCPWM_CAP_CH0_CFG_REG, MCPWM_CAP_CH1_CFG_REG, MCPWM_CAP_CH2_CFG_REG - * - Interrupt enable registers, e.g.: MCPWM_INT_ENA_REG - * - ETM Configurations, e.g.: MCPWM_EVT_EN_REG, MCPWM_TASK_EN_REG - * - Misc Configurations, e.g.: MCPWM_UPDATE_CFG_REG -*/ -#define MCPWM_RETENTION_REGS_CNT 73 -#define MCPWM_RETENTION_REGS_BASE(i) REG_MCPWM_BASE(i) -static const uint32_t mcpwm_regs_map[4] = {0xf7fff777, 0x3f7ffdff, 0x1f8ff8c, 0x0}; -#define MCPWM_SLEEP_RETENTION_ENTRIES(mcpwm_port) { \ - /* backup stage: save configuration registers \ - restore stage: restore the configuration registers */ \ - [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT( \ - REGDMA_MCPWM_LINK(0x00), \ - MCPWM_RETENTION_REGS_BASE(mcpwm_port), \ - MCPWM_RETENTION_REGS_BASE(mcpwm_port), \ - MCPWM_RETENTION_REGS_CNT, 0, 0, \ - mcpwm_regs_map[0], mcpwm_regs_map[1], \ - mcpwm_regs_map[2], mcpwm_regs_map[3]), \ - .owner = ENTRY(0)}, \ - /* restore stage: trigger a forced update of all active registers*/ \ - [1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x01), \ - MCPWM_UPDATE_CFG_REG(mcpwm_port), MCPWM_GLOBAL_FORCE_UP, MCPWM_GLOBAL_FORCE_UP_M, 1, 0), \ - .owner = ENTRY(0) }, \ - [2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x02), \ - MCPWM_UPDATE_CFG_REG(mcpwm_port), 0, MCPWM_GLOBAL_FORCE_UP_M, 1, 0), \ - .owner = ENTRY(0) }, \ -}; - -static const regdma_entries_config_t mcpwm0_regs_retention[] = MCPWM_SLEEP_RETENTION_ENTRIES(0); -static const regdma_entries_config_t mcpwm1_regs_retention[] = MCPWM_SLEEP_RETENTION_ENTRIES(1); -static const regdma_entries_config_t mcpwm2_regs_retention[] = MCPWM_SLEEP_RETENTION_ENTRIES(2); -static const regdma_entries_config_t mcpwm3_regs_retention[] = MCPWM_SLEEP_RETENTION_ENTRIES(3); - -const mcpwm_reg_retention_info_t mcpwm_reg_retention_info[4] = { - [0] = { - .regdma_entry_array = mcpwm0_regs_retention, - .array_size = ARRAY_SIZE(mcpwm0_regs_retention), - .retention_module = SLEEP_RETENTION_MODULE_MCPWM0 - }, - [1] = { - .regdma_entry_array = mcpwm1_regs_retention, - .array_size = ARRAY_SIZE(mcpwm1_regs_retention), - .retention_module = SLEEP_RETENTION_MODULE_MCPWM1 - }, - [2] = { - .regdma_entry_array = mcpwm2_regs_retention, - .array_size = ARRAY_SIZE(mcpwm2_regs_retention), - .retention_module = SLEEP_RETENTION_MODULE_MCPWM2 - }, - [3] = { - .regdma_entry_array = mcpwm3_regs_retention, - .array_size = ARRAY_SIZE(mcpwm3_regs_retention), - .retention_module = SLEEP_RETENTION_MODULE_MCPWM3 - }, -}; -#endif //SOC_MCPWM_SUPPORT_SLEEP_RETENTION diff --git a/components/esp_hal_mcpwm/include/hal/mcpwm_periph.h b/components/esp_hal_mcpwm/include/hal/mcpwm_periph.h index 60b2ce88475..bcee2546d72 100644 --- a/components/esp_hal_mcpwm/include/hal/mcpwm_periph.h +++ b/components/esp_hal_mcpwm/include/hal/mcpwm_periph.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2019-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2019-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -8,17 +8,11 @@ #include #include "soc/soc_caps.h" -#include "soc/periph_defs.h" -#include "soc/regdma.h" #if SOC_HAS(MCPWM) #include "hal/mcpwm_ll.h" #endif -#if SOC_MCPWM_SUPPORT_SLEEP_RETENTION -#include "soc/retention_periph_defs.h" -#endif - #ifdef __cplusplus extern "C" { #endif @@ -45,16 +39,6 @@ typedef struct { extern const soc_mcpwm_signal_desc_t soc_mcpwm_signals[MCPWM_LL_GET(GROUP_NUM)]; -#if SOC_MCPWM_SUPPORT_SLEEP_RETENTION -typedef struct { - const regdma_entries_config_t *regdma_entry_array; - uint32_t array_size; - const periph_retention_module_t retention_module; -} mcpwm_reg_retention_info_t; - -extern const mcpwm_reg_retention_info_t mcpwm_reg_retention_info[MCPWM_LL_GET(GROUP_NUM)]; -#endif // SOC_MCPWM_SUPPORT_SLEEP_RETENTION - #endif // SOC_HAS(MCPWM) #ifdef __cplusplus