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fix(esp_eth): fixed Ethernet PHY HW reset timing in common PHY code

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Ondrej Kosta
2026-08-11 13:57:08 +02:00
parent 923a5cfd8b
commit da47a936ac
1 changed files with 15 additions and 5 deletions
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20
components/esp_eth/src/phy/esp_eth_phy_802_3.c
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@@ -380,17 +380,27 @@ esp_err_t esp_eth_phy_802_3_del(phy_802_3_t *phy_802_3)
return ESP_OK; return ESP_OK;
} }
/* Delays for at least delay_us. Anything shorter than a FreeRTOS tick has to be busy waited since
the scheduler cannot express it. Longer delays are slept off by a single vTaskDelay which returns
after n-1 to n tick periods, because the call is placed somewhere inside an already running tick,
hence one extra tick is requested to not undershoot the delay. */
static void phy_802_3_delay_us(uint32_t delay_us)
{
uint32_t tick_period_us = portTICK_PERIOD_MS * 1000;
if (delay_us < tick_period_us) {
esp_rom_delay_us(delay_us);
} else {
vTaskDelay((delay_us + tick_period_us - 1) / tick_period_us + 1);
}
}
esp_err_t esp_eth_phy_802_3_reset_hw(phy_802_3_t *phy_802_3, uint32_t reset_assert_us) esp_err_t esp_eth_phy_802_3_reset_hw(phy_802_3_t *phy_802_3, uint32_t reset_assert_us)
{ {
if (phy_802_3->reset_gpio_num >= 0) { if (phy_802_3->reset_gpio_num >= 0) {
esp_rom_gpio_pad_select_gpio(phy_802_3->reset_gpio_num); esp_rom_gpio_pad_select_gpio(phy_802_3->reset_gpio_num);
gpio_set_direction(phy_802_3->reset_gpio_num, GPIO_MODE_OUTPUT); gpio_set_direction(phy_802_3->reset_gpio_num, GPIO_MODE_OUTPUT);
gpio_set_level(phy_802_3->reset_gpio_num, 0); gpio_set_level(phy_802_3->reset_gpio_num, 0);
if (reset_assert_us < 10000) { phy_802_3_delay_us(reset_assert_us);
esp_rom_delay_us(reset_assert_us);
} else {
vTaskDelay(pdMS_TO_TICKS(reset_assert_us/1000));
}
gpio_set_level(phy_802_3->reset_gpio_num, 1); gpio_set_level(phy_802_3->reset_gpio_num, 1);
} }
return ESP_OK; return ESP_OK;