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Merge branch 'feat/spi_master_ddr_mode' into 'master'

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feat(driver_spi): master driver support DDR(DTR) clock mode

Closes IDFGH-12948

See merge request espressif/esp-idf!49810
This commit is contained in:
morris
2026-08-20 17:40:32 +08:00
parent 9d7270493b a9ce9e4abf
commit d8df109e32
20 changed files with 178 additions and 8 deletions
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docs/en/api-reference/peripherals/spi_master.rst
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@@ -264,6 +264,13 @@ Supported line modes for {IDF_TARGET_NAME} are listed as follows, to make use of
SPI_TRANS_MULTILINE_CMD
- SPICOMMON_BUSFLAG_OCTAL
.. only:: SOC_SPI_SUPPORT_DDR_CLOCK
DDR Clock
^^^^^^^^^
Set :c:macro:`SPI_TRANS_DDRCLK` in :cpp:member:`spi_transaction_t::flags` to use double data rate mode for the current transaction. In this mode, the command, address, and data phases are sent/sampled on both the rising and falling edges of the clock. If this flag is not set, the transaction uses the traditional single data rate mode. DDRCLK mode is supported in 2/4/8 line modes as well.
Command and Address Phases
^^^^^^^^^^^^^^^^^^^^^^^^^^