Merge branch 'feat/spi_master_ddr_mode' into 'master'

feat(driver_spi): master driver support DDR(DTR) clock mode

Closes IDFGH-12948

See merge request espressif/esp-idf!49810

docs/en/api-reference/peripherals/spi_master.rst

@@ -264,6 +264,13 @@ Supported line modes for {IDF_TARGET_NAME} are listed as follows, to make use of
            SPI_TRANS_MULTILINE_CMD
          - SPICOMMON_BUSFLAG_OCTAL
 
+.. only:: SOC_SPI_SUPPORT_DDR_CLOCK
+
+    DDR Clock
+    ^^^^^^^^^
+
+    Set :c:macro:`SPI_TRANS_DDRCLK` in :cpp:member:`spi_transaction_t::flags` to use double data rate mode for the current transaction. In this mode, the command, address, and data phases are sent/sampled on both the rising and falling edges of the clock. If this flag is not set, the transaction uses the traditional single data rate mode. DDRCLK mode is supported in 2/4/8 line modes as well.
+
 Command and Address Phases
 ^^^^^^^^^^^^^^^^^^^^^^^^^^
 

docs/zh_CN/api-reference/peripherals/spi_master.rst

@@ -264,6 +264,13 @@ SPI 总线传输事务由五个阶段构成，详见下表（任意阶段均可
            SPI_TRANS_MULTILINE_CMD
          - SPICOMMON_BUSFLAG_OCTAL
 
+.. only:: SOC_SPI_SUPPORT_DDR_CLOCK
+
+    DDR 时钟
+    ^^^^^^^^
+
+    在 :cpp:member:`spi_transaction_t::flags` 中设置 :c:macro:`SPI_TRANS_DDRCLK`，可使当前传输事务使用时钟双边沿数据模式，该模式下， cmd/addr/data 段都将在时钟的上升沿和下降沿都进行传输，没有设置该标志时，传输将回到传统单边沿数据模式。DDRCLK 模式在 2/4/8 线模式下同样支持。
+
 命令阶段和地址阶段
 ^^^^^^^^^^^^^^^^^^^^^^^^^^