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Merge branch 'feat/spi_std_timing_and_bit_trans' into 'master'

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feat(driver_spi): support adjust master rx to standard timing

Closes IDF-11396

See merge request espressif/esp-idf!36058
This commit is contained in:
morris
2025-01-13 10:07:28 +08:00
parent 057bae82e1 460380bb25
commit d78f270b04
20 changed files with 312 additions and 13 deletions
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components/soc/esp32h2/register/soc/spi_struct.h
+9 -1
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@@ -622,7 +622,15 @@ typedef union {
* In the master mode it is pre-divider of spi_clk. Can be configured in CONF state.
*/
uint32_t clkdiv_pre:4;
uint32_t reserved_22:9;
uint32_t reserved_22:8;
/** clk_edge_sel : R/W; bitpos: [30]; default: 0;
* Configures use standard clock sampling edge or delay the sampling edge by half a
* cycle in master transfer.
* 0: clock sampling edge is delayed by half a cycle.
* 1: clock sampling edge is standard.
* Can be configured in CONF state. Only support on chip version >= 1.2
*/
uint32_t clk_edge_sel:1;
/** clk_equ_sysclk : R/W; bitpos: [31]; default: 1;
* In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from system
* clock. Can be configured in CONF state.