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feat(soc): update PMU & PAU register description

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This commit is contained in:
wuzhenghui
2026-07-06 21:33:12 +08:00
parent 315e812d5b
commit d78cc02b90
4 changed files with 980 additions and 528 deletions
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components/soc/esp32c61/register/soc/pau_reg.h
+67 -50
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@@ -1,5 +1,5 @@
/** /**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -12,53 +12,68 @@ extern "C" {
#endif #endif
/** PAU_REGDMA_CONF_REG register /** PAU_REGDMA_CONF_REG register
* Peri backup control register * Peripherals backup configuration/control register
*/ */
#define PAU_REGDMA_CONF_REG (DR_REG_PAU_BASE + 0x0) #define PAU_REGDMA_CONF_REG (DR_REG_PAU_BASE + 0x0)
/** PAU_FLOW_ERR : RO; bitpos: [2:0]; default: 0; /** PAU_FLOW_ERR : RO; bitpos: [2:0]; default: 0;
* backup error type * Represents the backup error type.
* 0: Received software triggered interrupt clear signal
* 1: Peripheral AHB bus timeout
* 2: Memory AHB bus timeout
* 3: Address link list wait timer timeout
* 4: Address mapping error
*/ */
#define PAU_FLOW_ERR 0x00000007U #define PAU_FLOW_ERR 0x00000007U
#define PAU_FLOW_ERR_M (PAU_FLOW_ERR_V << PAU_FLOW_ERR_S) #define PAU_FLOW_ERR_M (PAU_FLOW_ERR_V << PAU_FLOW_ERR_S)
#define PAU_FLOW_ERR_V 0x00000007U #define PAU_FLOW_ERR_V 0x00000007U
#define PAU_FLOW_ERR_S 0 #define PAU_FLOW_ERR_S 0
/** PAU_START : WT; bitpos: [3]; default: 0; /** PAU_START : WT; bitpos: [3]; default: 0;
* backup start signal * Write 1 to initiate the backup start signal.
*/ */
#define PAU_START (BIT(3)) #define PAU_START (BIT(3))
#define PAU_START_M (PAU_START_V << PAU_START_S) #define PAU_START_M (PAU_START_V << PAU_START_S)
#define PAU_START_V 0x00000001U #define PAU_START_V 0x00000001U
#define PAU_START_S 3 #define PAU_START_S 3
/** PAU_TO_MEM : R/W; bitpos: [4]; default: 0; /** PAU_TO_MEM : R/W; bitpos: [4]; default: 0;
* backup direction(reg to mem / mem to reg) * Configures the backup direction.
* 0: register to memory
* 1: memory to register
*/ */
#define PAU_TO_MEM (BIT(4)) #define PAU_TO_MEM (BIT(4))
#define PAU_TO_MEM_M (PAU_TO_MEM_V << PAU_TO_MEM_S) #define PAU_TO_MEM_M (PAU_TO_MEM_V << PAU_TO_MEM_S)
#define PAU_TO_MEM_V 0x00000001U #define PAU_TO_MEM_V 0x00000001U
#define PAU_TO_MEM_S 4 #define PAU_TO_MEM_S 4
/** PAU_LINK_SEL : R/W; bitpos: [6:5]; default: 0; /** PAU_LINK_SEL : R/W; bitpos: [6:5]; default: 0;
* Link select * Configures to select the link.
* 0: PAU_REGDMA_LINK_0_ADDR_REG
* 1: PAU_REGDMA_LINK_1_ADDR_REG
* 2: PAU_REGDMA_LINK_2_ADDR_REG
* 3: PAU_REGDMA_LINK_3_ADDR_REG
*/ */
#define PAU_LINK_SEL 0x00000003U #define PAU_LINK_SEL 0x00000003U
#define PAU_LINK_SEL_M (PAU_LINK_SEL_V << PAU_LINK_SEL_S) #define PAU_LINK_SEL_M (PAU_LINK_SEL_V << PAU_LINK_SEL_S)
#define PAU_LINK_SEL_V 0x00000003U #define PAU_LINK_SEL_V 0x00000003U
#define PAU_LINK_SEL_S 5 #define PAU_LINK_SEL_S 5
/** PAU_START_MAC : WT; bitpos: [7]; default: 0; /** PAU_START_MAC : WT; bitpos: [7]; default: 0;
* mac sw backup start signal * Write 1 to initiate the MAC software backup start signal.
*/ */
#define PAU_START_MAC (BIT(7)) #define PAU_START_MAC (BIT(7))
#define PAU_START_MAC_M (PAU_START_MAC_V << PAU_START_MAC_S) #define PAU_START_MAC_M (PAU_START_MAC_V << PAU_START_MAC_S)
#define PAU_START_MAC_V 0x00000001U #define PAU_START_MAC_V 0x00000001U
#define PAU_START_MAC_S 7 #define PAU_START_MAC_S 7
/** PAU_TO_MEM_MAC : R/W; bitpos: [8]; default: 0; /** PAU_TO_MEM_MAC : R/W; bitpos: [8]; default: 0;
* mac sw backup direction(reg to mem / mem to reg) * Configures the MAC software backup direction.
* 0: register to memory
* 1: memory to register
*/ */
#define PAU_TO_MEM_MAC (BIT(8)) #define PAU_TO_MEM_MAC (BIT(8))
#define PAU_TO_MEM_MAC_M (PAU_TO_MEM_MAC_V << PAU_TO_MEM_MAC_S) #define PAU_TO_MEM_MAC_M (PAU_TO_MEM_MAC_V << PAU_TO_MEM_MAC_S)
#define PAU_TO_MEM_MAC_V 0x00000001U #define PAU_TO_MEM_MAC_V 0x00000001U
#define PAU_TO_MEM_MAC_S 8 #define PAU_TO_MEM_MAC_S 8
/** PAU_SEL_MAC : R/W; bitpos: [9]; default: 0; /** PAU_SEL_MAC : R/W; bitpos: [9]; default: 0;
* mac hw/sw select * Configures the MAC hardware/software selection.
* 0: select the hardware path
* 1: select the software path
*/ */
#define PAU_SEL_MAC (BIT(9)) #define PAU_SEL_MAC (BIT(9))
#define PAU_SEL_MAC_M (PAU_SEL_MAC_V << PAU_SEL_MAC_S) #define PAU_SEL_MAC_M (PAU_SEL_MAC_V << PAU_SEL_MAC_S)
@@ -70,7 +85,9 @@ extern "C" {
*/ */
#define PAU_REGDMA_CLK_CONF_REG (DR_REG_PAU_BASE + 0x4) #define PAU_REGDMA_CLK_CONF_REG (DR_REG_PAU_BASE + 0x4)
/** PAU_CLK_EN : R/W; bitpos: [0]; default: 0; /** PAU_CLK_EN : R/W; bitpos: [0]; default: 0;
* clock enable * Configures whether or not to enable clock for the PAU module.
* 0: Disable
* 1: Enable
*/ */
#define PAU_CLK_EN (BIT(0)) #define PAU_CLK_EN (BIT(0))
#define PAU_CLK_EN_M (PAU_CLK_EN_V << PAU_CLK_EN_S) #define PAU_CLK_EN_M (PAU_CLK_EN_V << PAU_CLK_EN_S)
@@ -78,32 +95,32 @@ extern "C" {
#define PAU_CLK_EN_S 0 #define PAU_CLK_EN_S 0
/** PAU_REGDMA_ETM_CTRL_REG register /** PAU_REGDMA_ETM_CTRL_REG register
* ETM start ctrl reg * ETM start configuration/control register
*/ */
#define PAU_REGDMA_ETM_CTRL_REG (DR_REG_PAU_BASE + 0x8) #define PAU_REGDMA_ETM_CTRL_REG (DR_REG_PAU_BASE + 0x8)
/** PAU_ETM_START_0 : WT; bitpos: [0]; default: 0; /** PAU_ETM_START_0 : WT; bitpos: [0]; default: 0;
* etm_start_0 reg * Write 1 to start ETM operation 0.
*/ */
#define PAU_ETM_START_0 (BIT(0)) #define PAU_ETM_START_0 (BIT(0))
#define PAU_ETM_START_0_M (PAU_ETM_START_0_V << PAU_ETM_START_0_S) #define PAU_ETM_START_0_M (PAU_ETM_START_0_V << PAU_ETM_START_0_S)
#define PAU_ETM_START_0_V 0x00000001U #define PAU_ETM_START_0_V 0x00000001U
#define PAU_ETM_START_0_S 0 #define PAU_ETM_START_0_S 0
/** PAU_ETM_START_1 : WT; bitpos: [1]; default: 0; /** PAU_ETM_START_1 : WT; bitpos: [1]; default: 0;
* etm_start_1 reg * Write 1 to start ETM operation 1.
*/ */
#define PAU_ETM_START_1 (BIT(1)) #define PAU_ETM_START_1 (BIT(1))
#define PAU_ETM_START_1_M (PAU_ETM_START_1_V << PAU_ETM_START_1_S) #define PAU_ETM_START_1_M (PAU_ETM_START_1_V << PAU_ETM_START_1_S)
#define PAU_ETM_START_1_V 0x00000001U #define PAU_ETM_START_1_V 0x00000001U
#define PAU_ETM_START_1_S 1 #define PAU_ETM_START_1_S 1
/** PAU_ETM_START_2 : WT; bitpos: [2]; default: 0; /** PAU_ETM_START_2 : WT; bitpos: [2]; default: 0;
* etm_start_2 reg * Write 1 to start ETM operation 2.
*/ */
#define PAU_ETM_START_2 (BIT(2)) #define PAU_ETM_START_2 (BIT(2))
#define PAU_ETM_START_2_M (PAU_ETM_START_2_V << PAU_ETM_START_2_S) #define PAU_ETM_START_2_M (PAU_ETM_START_2_V << PAU_ETM_START_2_S)
#define PAU_ETM_START_2_V 0x00000001U #define PAU_ETM_START_2_V 0x00000001U
#define PAU_ETM_START_2_S 2 #define PAU_ETM_START_2_S 2
/** PAU_ETM_START_3 : WT; bitpos: [3]; default: 0; /** PAU_ETM_START_3 : WT; bitpos: [3]; default: 0;
* etm_start_3 reg * Write 1 to start ETM operation 3.
*/ */
#define PAU_ETM_START_3 (BIT(3)) #define PAU_ETM_START_3 (BIT(3))
#define PAU_ETM_START_3_M (PAU_ETM_START_3_V << PAU_ETM_START_3_S) #define PAU_ETM_START_3_M (PAU_ETM_START_3_V << PAU_ETM_START_3_S)
@@ -111,11 +128,11 @@ extern "C" {
#define PAU_ETM_START_3_S 3 #define PAU_ETM_START_3_S 3
/** PAU_REGDMA_LINK_0_ADDR_REG register /** PAU_REGDMA_LINK_0_ADDR_REG register
* link_0_addr * Link address configuration register 0
*/ */
#define PAU_REGDMA_LINK_0_ADDR_REG (DR_REG_PAU_BASE + 0xc) #define PAU_REGDMA_LINK_0_ADDR_REG (DR_REG_PAU_BASE + 0xc)
/** PAU_LINK_ADDR_0 : R/W; bitpos: [31:0]; default: 0; /** PAU_LINK_ADDR_0 : R/W; bitpos: [31:0]; default: 0;
* link_0_addr reg * Represents the address for link 0.
*/ */
#define PAU_LINK_ADDR_0 0xFFFFFFFFU #define PAU_LINK_ADDR_0 0xFFFFFFFFU
#define PAU_LINK_ADDR_0_M (PAU_LINK_ADDR_0_V << PAU_LINK_ADDR_0_S) #define PAU_LINK_ADDR_0_M (PAU_LINK_ADDR_0_V << PAU_LINK_ADDR_0_S)
@@ -123,11 +140,11 @@ extern "C" {
#define PAU_LINK_ADDR_0_S 0 #define PAU_LINK_ADDR_0_S 0
/** PAU_REGDMA_LINK_1_ADDR_REG register /** PAU_REGDMA_LINK_1_ADDR_REG register
* Link_1_addr * Link address configuration register 1
*/ */
#define PAU_REGDMA_LINK_1_ADDR_REG (DR_REG_PAU_BASE + 0x10) #define PAU_REGDMA_LINK_1_ADDR_REG (DR_REG_PAU_BASE + 0x10)
/** PAU_LINK_ADDR_1 : R/W; bitpos: [31:0]; default: 0; /** PAU_LINK_ADDR_1 : R/W; bitpos: [31:0]; default: 0;
* Link_1_addr reg * Represents the address for link 1.
*/ */
#define PAU_LINK_ADDR_1 0xFFFFFFFFU #define PAU_LINK_ADDR_1 0xFFFFFFFFU
#define PAU_LINK_ADDR_1_M (PAU_LINK_ADDR_1_V << PAU_LINK_ADDR_1_S) #define PAU_LINK_ADDR_1_M (PAU_LINK_ADDR_1_V << PAU_LINK_ADDR_1_S)
@@ -135,11 +152,11 @@ extern "C" {
#define PAU_LINK_ADDR_1_S 0 #define PAU_LINK_ADDR_1_S 0
/** PAU_REGDMA_LINK_2_ADDR_REG register /** PAU_REGDMA_LINK_2_ADDR_REG register
* Link_2_addr * Link address configuration register 2
*/ */
#define PAU_REGDMA_LINK_2_ADDR_REG (DR_REG_PAU_BASE + 0x14) #define PAU_REGDMA_LINK_2_ADDR_REG (DR_REG_PAU_BASE + 0x14)
/** PAU_LINK_ADDR_2 : R/W; bitpos: [31:0]; default: 0; /** PAU_LINK_ADDR_2 : R/W; bitpos: [31:0]; default: 0;
* Link_2_addr reg * Represents the address for link 2.
*/ */
#define PAU_LINK_ADDR_2 0xFFFFFFFFU #define PAU_LINK_ADDR_2 0xFFFFFFFFU
#define PAU_LINK_ADDR_2_M (PAU_LINK_ADDR_2_V << PAU_LINK_ADDR_2_S) #define PAU_LINK_ADDR_2_M (PAU_LINK_ADDR_2_V << PAU_LINK_ADDR_2_S)
@@ -147,11 +164,11 @@ extern "C" {
#define PAU_LINK_ADDR_2_S 0 #define PAU_LINK_ADDR_2_S 0
/** PAU_REGDMA_LINK_3_ADDR_REG register /** PAU_REGDMA_LINK_3_ADDR_REG register
* Link_3_addr * Link address configuration register 3
*/ */
#define PAU_REGDMA_LINK_3_ADDR_REG (DR_REG_PAU_BASE + 0x18) #define PAU_REGDMA_LINK_3_ADDR_REG (DR_REG_PAU_BASE + 0x18)
/** PAU_LINK_ADDR_3 : R/W; bitpos: [31:0]; default: 0; /** PAU_LINK_ADDR_3 : R/W; bitpos: [31:0]; default: 0;
* Link_3_addr reg * Represents the address for link 3.
*/ */
#define PAU_LINK_ADDR_3 0xFFFFFFFFU #define PAU_LINK_ADDR_3 0xFFFFFFFFU
#define PAU_LINK_ADDR_3_M (PAU_LINK_ADDR_3_V << PAU_LINK_ADDR_3_S) #define PAU_LINK_ADDR_3_M (PAU_LINK_ADDR_3_V << PAU_LINK_ADDR_3_S)
@@ -159,11 +176,11 @@ extern "C" {
#define PAU_LINK_ADDR_3_S 0 #define PAU_LINK_ADDR_3_S 0
/** PAU_REGDMA_LINK_MAC_ADDR_REG register /** PAU_REGDMA_LINK_MAC_ADDR_REG register
* Link_mac_addr * Link MAC address register
*/ */
#define PAU_REGDMA_LINK_MAC_ADDR_REG (DR_REG_PAU_BASE + 0x1c) #define PAU_REGDMA_LINK_MAC_ADDR_REG (DR_REG_PAU_BASE + 0x1c)
/** PAU_LINK_ADDR_MAC : R/W; bitpos: [31:0]; default: 0; /** PAU_LINK_ADDR_MAC : R/W; bitpos: [31:0]; default: 0;
* Link_mac_addr reg * Represents the MAC address for the link.
*/ */
#define PAU_LINK_ADDR_MAC 0xFFFFFFFFU #define PAU_LINK_ADDR_MAC 0xFFFFFFFFU
#define PAU_LINK_ADDR_MAC_M (PAU_LINK_ADDR_MAC_V << PAU_LINK_ADDR_MAC_S) #define PAU_LINK_ADDR_MAC_M (PAU_LINK_ADDR_MAC_V << PAU_LINK_ADDR_MAC_S)
@@ -171,11 +188,11 @@ extern "C" {
#define PAU_LINK_ADDR_MAC_S 0 #define PAU_LINK_ADDR_MAC_S 0
/** PAU_REGDMA_CURRENT_LINK_ADDR_REG register /** PAU_REGDMA_CURRENT_LINK_ADDR_REG register
* current link addr * Current link address register
*/ */
#define PAU_REGDMA_CURRENT_LINK_ADDR_REG (DR_REG_PAU_BASE + 0x20) #define PAU_REGDMA_CURRENT_LINK_ADDR_REG (DR_REG_PAU_BASE + 0x20)
/** PAU_CURRENT_LINK_ADDR : RO; bitpos: [31:0]; default: 0; /** PAU_CURRENT_LINK_ADDR : RO; bitpos: [31:0]; default: 0;
* current link addr reg * Represents the current link address.
*/ */
#define PAU_CURRENT_LINK_ADDR 0xFFFFFFFFU #define PAU_CURRENT_LINK_ADDR 0xFFFFFFFFU
#define PAU_CURRENT_LINK_ADDR_M (PAU_CURRENT_LINK_ADDR_V << PAU_CURRENT_LINK_ADDR_S) #define PAU_CURRENT_LINK_ADDR_M (PAU_CURRENT_LINK_ADDR_V << PAU_CURRENT_LINK_ADDR_S)
@@ -183,11 +200,11 @@ extern "C" {
#define PAU_CURRENT_LINK_ADDR_S 0 #define PAU_CURRENT_LINK_ADDR_S 0
/** PAU_REGDMA_BACKUP_ADDR_REG register /** PAU_REGDMA_BACKUP_ADDR_REG register
* Backup addr * Backup address register
*/ */
#define PAU_REGDMA_BACKUP_ADDR_REG (DR_REG_PAU_BASE + 0x24) #define PAU_REGDMA_BACKUP_ADDR_REG (DR_REG_PAU_BASE + 0x24)
/** PAU_BACKUP_ADDR : RO; bitpos: [31:0]; default: 0; /** PAU_BACKUP_ADDR : RO; bitpos: [31:0]; default: 0;
* backup addr reg * Represents the backup address.
*/ */
#define PAU_BACKUP_ADDR 0xFFFFFFFFU #define PAU_BACKUP_ADDR 0xFFFFFFFFU
#define PAU_BACKUP_ADDR_M (PAU_BACKUP_ADDR_V << PAU_BACKUP_ADDR_S) #define PAU_BACKUP_ADDR_M (PAU_BACKUP_ADDR_V << PAU_BACKUP_ADDR_S)
@@ -195,11 +212,11 @@ extern "C" {
#define PAU_BACKUP_ADDR_S 0 #define PAU_BACKUP_ADDR_S 0
/** PAU_REGDMA_MEM_ADDR_REG register /** PAU_REGDMA_MEM_ADDR_REG register
* mem addr * Memory address configuration register
*/ */
#define PAU_REGDMA_MEM_ADDR_REG (DR_REG_PAU_BASE + 0x28) #define PAU_REGDMA_MEM_ADDR_REG (DR_REG_PAU_BASE + 0x28)
/** PAU_MEM_ADDR : RO; bitpos: [31:0]; default: 0; /** PAU_MEM_ADDR : RO; bitpos: [31:0]; default: 0;
* mem addr reg * Represents the memory address.
*/ */
#define PAU_MEM_ADDR 0xFFFFFFFFU #define PAU_MEM_ADDR 0xFFFFFFFFU
#define PAU_MEM_ADDR_M (PAU_MEM_ADDR_V << PAU_MEM_ADDR_S) #define PAU_MEM_ADDR_M (PAU_MEM_ADDR_V << PAU_MEM_ADDR_S)
@@ -207,32 +224,32 @@ extern "C" {
#define PAU_MEM_ADDR_S 0 #define PAU_MEM_ADDR_S 0
/** PAU_REGDMA_BKP_CONF_REG register /** PAU_REGDMA_BKP_CONF_REG register
* backup config * Link configuration register
*/ */
#define PAU_REGDMA_BKP_CONF_REG (DR_REG_PAU_BASE + 0x2c) #define PAU_REGDMA_BKP_CONF_REG (DR_REG_PAU_BASE + 0x2c)
/** PAU_READ_INTERVAL : R/W; bitpos: [6:0]; default: 32; /** PAU_READ_INTERVAL : R/W; bitpos: [6:0]; default: 32;
* Link read_interval * Configures the read interval for the link.
*/ */
#define PAU_READ_INTERVAL 0x0000007FU #define PAU_READ_INTERVAL 0x0000007FU
#define PAU_READ_INTERVAL_M (PAU_READ_INTERVAL_V << PAU_READ_INTERVAL_S) #define PAU_READ_INTERVAL_M (PAU_READ_INTERVAL_V << PAU_READ_INTERVAL_S)
#define PAU_READ_INTERVAL_V 0x0000007FU #define PAU_READ_INTERVAL_V 0x0000007FU
#define PAU_READ_INTERVAL_S 0 #define PAU_READ_INTERVAL_S 0
/** PAU_LINK_TOUT_THRES : R/W; bitpos: [16:7]; default: 50; /** PAU_LINK_TOUT_THRES : R/W; bitpos: [16:7]; default: 50;
* link wait timeout threshold * Configures the link wait timeout threshold.
*/ */
#define PAU_LINK_TOUT_THRES 0x000003FFU #define PAU_LINK_TOUT_THRES 0x000003FFU
#define PAU_LINK_TOUT_THRES_M (PAU_LINK_TOUT_THRES_V << PAU_LINK_TOUT_THRES_S) #define PAU_LINK_TOUT_THRES_M (PAU_LINK_TOUT_THRES_V << PAU_LINK_TOUT_THRES_S)
#define PAU_LINK_TOUT_THRES_V 0x000003FFU #define PAU_LINK_TOUT_THRES_V 0x000003FFU
#define PAU_LINK_TOUT_THRES_S 7 #define PAU_LINK_TOUT_THRES_S 7
/** PAU_BURST_LIMIT : R/W; bitpos: [21:17]; default: 8; /** PAU_BURST_LIMIT : R/W; bitpos: [21:17]; default: 8;
* burst limit * Configures the burst limit.
*/ */
#define PAU_BURST_LIMIT 0x0000001FU #define PAU_BURST_LIMIT 0x0000001FU
#define PAU_BURST_LIMIT_M (PAU_BURST_LIMIT_V << PAU_BURST_LIMIT_S) #define PAU_BURST_LIMIT_M (PAU_BURST_LIMIT_V << PAU_BURST_LIMIT_S)
#define PAU_BURST_LIMIT_V 0x0000001FU #define PAU_BURST_LIMIT_V 0x0000001FU
#define PAU_BURST_LIMIT_S 17 #define PAU_BURST_LIMIT_S 17
/** PAU_BACKUP_TOUT_THRES : R/W; bitpos: [31:22]; default: 500; /** PAU_BACKUP_TOUT_THRES : R/W; bitpos: [31:22]; default: 500;
* Backup timeout threshold * Configures the backup timeout threshold.
*/ */
#define PAU_BACKUP_TOUT_THRES 0x000003FFU #define PAU_BACKUP_TOUT_THRES 0x000003FFU
#define PAU_BACKUP_TOUT_THRES_M (PAU_BACKUP_TOUT_THRES_V << PAU_BACKUP_TOUT_THRES_S) #define PAU_BACKUP_TOUT_THRES_M (PAU_BACKUP_TOUT_THRES_V << PAU_BACKUP_TOUT_THRES_S)
@@ -240,18 +257,18 @@ extern "C" {
#define PAU_BACKUP_TOUT_THRES_S 22 #define PAU_BACKUP_TOUT_THRES_S 22
/** PAU_INT_ENA_REG register /** PAU_INT_ENA_REG register
* Read only register for error and done * Interrupt register
*/ */
#define PAU_INT_ENA_REG (DR_REG_PAU_BASE + 0x30) #define PAU_INT_ENA_REG (DR_REG_PAU_BASE + 0x30)
/** PAU_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; /** PAU_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
* backup done flag * Write 1 to enable backup done interrupt.
*/ */
#define PAU_DONE_INT_ENA (BIT(0)) #define PAU_DONE_INT_ENA (BIT(0))
#define PAU_DONE_INT_ENA_M (PAU_DONE_INT_ENA_V << PAU_DONE_INT_ENA_S) #define PAU_DONE_INT_ENA_M (PAU_DONE_INT_ENA_V << PAU_DONE_INT_ENA_S)
#define PAU_DONE_INT_ENA_V 0x00000001U #define PAU_DONE_INT_ENA_V 0x00000001U
#define PAU_DONE_INT_ENA_S 0 #define PAU_DONE_INT_ENA_S 0
/** PAU_ERROR_INT_ENA : R/W; bitpos: [1]; default: 0; /** PAU_ERROR_INT_ENA : R/W; bitpos: [1]; default: 0;
* error flag * Write 1 to enable error interrupt.
*/ */
#define PAU_ERROR_INT_ENA (BIT(1)) #define PAU_ERROR_INT_ENA (BIT(1))
#define PAU_ERROR_INT_ENA_M (PAU_ERROR_INT_ENA_V << PAU_ERROR_INT_ENA_S) #define PAU_ERROR_INT_ENA_M (PAU_ERROR_INT_ENA_V << PAU_ERROR_INT_ENA_S)
@@ -259,18 +276,18 @@ extern "C" {
#define PAU_ERROR_INT_ENA_S 1 #define PAU_ERROR_INT_ENA_S 1
/** PAU_INT_RAW_REG register /** PAU_INT_RAW_REG register
* Read only register for error and done * Interrupt register
*/ */
#define PAU_INT_RAW_REG (DR_REG_PAU_BASE + 0x34) #define PAU_INT_RAW_REG (DR_REG_PAU_BASE + 0x34)
/** PAU_DONE_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; /** PAU_DONE_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
* backup done flag * The raw interrupt status for backup completion.
*/ */
#define PAU_DONE_INT_RAW (BIT(0)) #define PAU_DONE_INT_RAW (BIT(0))
#define PAU_DONE_INT_RAW_M (PAU_DONE_INT_RAW_V << PAU_DONE_INT_RAW_S) #define PAU_DONE_INT_RAW_M (PAU_DONE_INT_RAW_V << PAU_DONE_INT_RAW_S)
#define PAU_DONE_INT_RAW_V 0x00000001U #define PAU_DONE_INT_RAW_V 0x00000001U
#define PAU_DONE_INT_RAW_S 0 #define PAU_DONE_INT_RAW_S 0
/** PAU_ERROR_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; /** PAU_ERROR_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
* error flag * The raw interrupt status for errors.
*/ */
#define PAU_ERROR_INT_RAW (BIT(1)) #define PAU_ERROR_INT_RAW (BIT(1))
#define PAU_ERROR_INT_RAW_M (PAU_ERROR_INT_RAW_V << PAU_ERROR_INT_RAW_S) #define PAU_ERROR_INT_RAW_M (PAU_ERROR_INT_RAW_V << PAU_ERROR_INT_RAW_S)
@@ -278,18 +295,18 @@ extern "C" {
#define PAU_ERROR_INT_RAW_S 1 #define PAU_ERROR_INT_RAW_S 1
/** PAU_INT_CLR_REG register /** PAU_INT_CLR_REG register
* Read only register for error and done * Interrupt register
*/ */
#define PAU_INT_CLR_REG (DR_REG_PAU_BASE + 0x38) #define PAU_INT_CLR_REG (DR_REG_PAU_BASE + 0x38)
/** PAU_DONE_INT_CLR : WT; bitpos: [0]; default: 0; /** PAU_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
* backup done flag * Write 1 to clear the backup done interrupt.
*/ */
#define PAU_DONE_INT_CLR (BIT(0)) #define PAU_DONE_INT_CLR (BIT(0))
#define PAU_DONE_INT_CLR_M (PAU_DONE_INT_CLR_V << PAU_DONE_INT_CLR_S) #define PAU_DONE_INT_CLR_M (PAU_DONE_INT_CLR_V << PAU_DONE_INT_CLR_S)
#define PAU_DONE_INT_CLR_V 0x00000001U #define PAU_DONE_INT_CLR_V 0x00000001U
#define PAU_DONE_INT_CLR_S 0 #define PAU_DONE_INT_CLR_S 0
/** PAU_ERROR_INT_CLR : WT; bitpos: [1]; default: 0; /** PAU_ERROR_INT_CLR : WT; bitpos: [1]; default: 0;
* error flag * Write 1 to clear the error interrupt.
*/ */
#define PAU_ERROR_INT_CLR (BIT(1)) #define PAU_ERROR_INT_CLR (BIT(1))
#define PAU_ERROR_INT_CLR_M (PAU_ERROR_INT_CLR_V << PAU_ERROR_INT_CLR_S) #define PAU_ERROR_INT_CLR_M (PAU_ERROR_INT_CLR_V << PAU_ERROR_INT_CLR_S)
@@ -297,18 +314,18 @@ extern "C" {
#define PAU_ERROR_INT_CLR_S 1 #define PAU_ERROR_INT_CLR_S 1
/** PAU_INT_ST_REG register /** PAU_INT_ST_REG register
* Read only register for error and done * Interrupt register
*/ */
#define PAU_INT_ST_REG (DR_REG_PAU_BASE + 0x3c) #define PAU_INT_ST_REG (DR_REG_PAU_BASE + 0x3c)
/** PAU_DONE_INT_ST : RO; bitpos: [0]; default: 0; /** PAU_DONE_INT_ST : RO; bitpos: [0]; default: 0;
* backup done flag * Represents the backup completion status.
*/ */
#define PAU_DONE_INT_ST (BIT(0)) #define PAU_DONE_INT_ST (BIT(0))
#define PAU_DONE_INT_ST_M (PAU_DONE_INT_ST_V << PAU_DONE_INT_ST_S) #define PAU_DONE_INT_ST_M (PAU_DONE_INT_ST_V << PAU_DONE_INT_ST_S)
#define PAU_DONE_INT_ST_V 0x00000001U #define PAU_DONE_INT_ST_V 0x00000001U
#define PAU_DONE_INT_ST_S 0 #define PAU_DONE_INT_ST_S 0
/** PAU_ERROR_INT_ST : RO; bitpos: [1]; default: 0; /** PAU_ERROR_INT_ST : RO; bitpos: [1]; default: 0;
* error flag * Represents the error status.
*/ */
#define PAU_ERROR_INT_ST (BIT(1)) #define PAU_ERROR_INT_ST (BIT(1))
#define PAU_ERROR_INT_ST_M (PAU_ERROR_INT_ST_V << PAU_ERROR_INT_ST_S) #define PAU_ERROR_INT_ST_M (PAU_ERROR_INT_ST_V << PAU_ERROR_INT_ST_S)
@@ -316,11 +333,11 @@ extern "C" {
#define PAU_ERROR_INT_ST_S 1 #define PAU_ERROR_INT_ST_S 1
/** PAU_DATE_REG register /** PAU_DATE_REG register
* Date register. * Version control register
*/ */
#define PAU_DATE_REG (DR_REG_PAU_BASE + 0x3fc) #define PAU_DATE_REG (DR_REG_PAU_BASE + 0x3fc)
/** PAU_DATE : R/W; bitpos: [27:0]; default: 36708608; /** PAU_DATE : R/W; bitpos: [27:0]; default: 36708608;
* REGDMA date information/ REGDMA version information. * Version control register.
*/ */
#define PAU_DATE 0x0FFFFFFFU #define PAU_DATE 0x0FFFFFFFU
#define PAU_DATE_M (PAU_DATE_V << PAU_DATE_S) #define PAU_DATE_M (PAU_DATE_V << PAU_DATE_S)
components/soc/esp32c61/register/soc/pau_struct.h
+67 -50
View File
@@ -1,5 +1,5 @@
/** /**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -12,36 +12,51 @@ extern "C" {
/** Group: Configuration Register */ /** Group: Configuration Register */
/** Type of regdma_conf register /** Type of regdma_conf register
* Peri backup control register * Peripherals backup configuration/control register
*/ */
typedef union { typedef union {
struct { struct {
/** flow_err : RO; bitpos: [2:0]; default: 0; /** flow_err : RO; bitpos: [2:0]; default: 0;
* backup error type * Represents the backup error type.
* 0: Received software triggered interrupt clear signal
* 1: Peripheral AHB bus timeout
* 2: Memory AHB bus timeout
* 3: Address link list wait timer timeout
* 4: Address mapping error
*/ */
uint32_t flow_err:3; uint32_t flow_err:3;
/** start : WT; bitpos: [3]; default: 0; /** start : WT; bitpos: [3]; default: 0;
* backup start signal * Write 1 to initiate the backup start signal.
*/ */
uint32_t start:1; uint32_t start:1;
/** to_mem : R/W; bitpos: [4]; default: 0; /** to_mem : R/W; bitpos: [4]; default: 0;
* backup direction(reg to mem / mem to reg) * Configures the backup direction.
* 0: register to memory
* 1: memory to register
*/ */
uint32_t to_mem:1; uint32_t to_mem:1;
/** link_sel : R/W; bitpos: [6:5]; default: 0; /** link_sel : R/W; bitpos: [6:5]; default: 0;
* Link select * Configures to select the link.
* 0: PAU_REGDMA_LINK_0_ADDR_REG
* 1: PAU_REGDMA_LINK_1_ADDR_REG
* 2: PAU_REGDMA_LINK_2_ADDR_REG
* 3: PAU_REGDMA_LINK_3_ADDR_REG
*/ */
uint32_t link_sel:2; uint32_t link_sel:2;
/** start_mac : WT; bitpos: [7]; default: 0; /** start_mac : WT; bitpos: [7]; default: 0;
* mac sw backup start signal * Write 1 to initiate the MAC software backup start signal.
*/ */
uint32_t start_mac:1; uint32_t start_mac:1;
/** to_mem_mac : R/W; bitpos: [8]; default: 0; /** to_mem_mac : R/W; bitpos: [8]; default: 0;
* mac sw backup direction(reg to mem / mem to reg) * Configures the MAC software backup direction.
* 0: register to memory
* 1: memory to register
*/ */
uint32_t to_mem_mac:1; uint32_t to_mem_mac:1;
/** sel_mac : R/W; bitpos: [9]; default: 0; /** sel_mac : R/W; bitpos: [9]; default: 0;
* mac hw/sw select * Configures the MAC hardware/software selection.
* 0: select the hardware path
* 1: select the software path
*/ */
uint32_t sel_mac:1; uint32_t sel_mac:1;
uint32_t reserved_10:22; uint32_t reserved_10:22;
@@ -55,7 +70,9 @@ typedef union {
typedef union { typedef union {
struct { struct {
/** clk_en : R/W; bitpos: [0]; default: 0; /** clk_en : R/W; bitpos: [0]; default: 0;
* clock enable * Configures whether or not to enable clock for the PAU module.
* 0: Disable
* 1: Enable
*/ */
uint32_t clk_en:1; uint32_t clk_en:1;
uint32_t reserved_1:31; uint32_t reserved_1:31;
@@ -64,24 +81,24 @@ typedef union {
} pau_regdma_clk_conf_reg_t; } pau_regdma_clk_conf_reg_t;
/** Type of regdma_etm_ctrl register /** Type of regdma_etm_ctrl register
* ETM start ctrl reg * ETM start configuration/control register
*/ */
typedef union { typedef union {
struct { struct {
/** etm_start_0 : WT; bitpos: [0]; default: 0; /** etm_start_0 : WT; bitpos: [0]; default: 0;
* etm_start_0 reg * Write 1 to start ETM operation 0.
*/ */
uint32_t etm_start_0:1; uint32_t etm_start_0:1;
/** etm_start_1 : WT; bitpos: [1]; default: 0; /** etm_start_1 : WT; bitpos: [1]; default: 0;
* etm_start_1 reg * Write 1 to start ETM operation 1.
*/ */
uint32_t etm_start_1:1; uint32_t etm_start_1:1;
/** etm_start_2 : WT; bitpos: [2]; default: 0; /** etm_start_2 : WT; bitpos: [2]; default: 0;
* etm_start_2 reg * Write 1 to start ETM operation 2.
*/ */
uint32_t etm_start_2:1; uint32_t etm_start_2:1;
/** etm_start_3 : WT; bitpos: [3]; default: 0; /** etm_start_3 : WT; bitpos: [3]; default: 0;
* etm_start_3 reg * Write 1 to start ETM operation 3.
*/ */
uint32_t etm_start_3:1; uint32_t etm_start_3:1;
uint32_t reserved_4:28; uint32_t reserved_4:28;
@@ -90,12 +107,12 @@ typedef union {
} pau_regdma_etm_ctrl_reg_t; } pau_regdma_etm_ctrl_reg_t;
/** Type of regdma_link_0_addr register /** Type of regdma_link_0_addr register
* link_0_addr * Link address configuration register 0
*/ */
typedef union { typedef union {
struct { struct {
/** link_addr_0 : R/W; bitpos: [31:0]; default: 0; /** link_addr_0 : R/W; bitpos: [31:0]; default: 0;
* link_0_addr reg * Represents the address for link 0.
*/ */
uint32_t link_addr_0:32; uint32_t link_addr_0:32;
}; };
@@ -103,12 +120,12 @@ typedef union {
} pau_regdma_link_0_addr_reg_t; } pau_regdma_link_0_addr_reg_t;
/** Type of regdma_link_1_addr register /** Type of regdma_link_1_addr register
* Link_1_addr * Link address configuration register 1
*/ */
typedef union { typedef union {
struct { struct {
/** link_addr_1 : R/W; bitpos: [31:0]; default: 0; /** link_addr_1 : R/W; bitpos: [31:0]; default: 0;
* Link_1_addr reg * Represents the address for link 1.
*/ */
uint32_t link_addr_1:32; uint32_t link_addr_1:32;
}; };
@@ -116,12 +133,12 @@ typedef union {
} pau_regdma_link_1_addr_reg_t; } pau_regdma_link_1_addr_reg_t;
/** Type of regdma_link_2_addr register /** Type of regdma_link_2_addr register
* Link_2_addr * Link address configuration register 2
*/ */
typedef union { typedef union {
struct { struct {
/** link_addr_2 : R/W; bitpos: [31:0]; default: 0; /** link_addr_2 : R/W; bitpos: [31:0]; default: 0;
* Link_2_addr reg * Represents the address for link 2.
*/ */
uint32_t link_addr_2:32; uint32_t link_addr_2:32;
}; };
@@ -129,12 +146,12 @@ typedef union {
} pau_regdma_link_2_addr_reg_t; } pau_regdma_link_2_addr_reg_t;
/** Type of regdma_link_3_addr register /** Type of regdma_link_3_addr register
* Link_3_addr * Link address configuration register 3
*/ */
typedef union { typedef union {
struct { struct {
/** link_addr_3 : R/W; bitpos: [31:0]; default: 0; /** link_addr_3 : R/W; bitpos: [31:0]; default: 0;
* Link_3_addr reg * Represents the address for link 3.
*/ */
uint32_t link_addr_3:32; uint32_t link_addr_3:32;
}; };
@@ -142,12 +159,12 @@ typedef union {
} pau_regdma_link_3_addr_reg_t; } pau_regdma_link_3_addr_reg_t;
/** Type of regdma_link_mac_addr register /** Type of regdma_link_mac_addr register
* Link_mac_addr * Link MAC address register
*/ */
typedef union { typedef union {
struct { struct {
/** link_addr_mac : R/W; bitpos: [31:0]; default: 0; /** link_addr_mac : R/W; bitpos: [31:0]; default: 0;
* Link_mac_addr reg * Represents the MAC address for the link.
*/ */
uint32_t link_addr_mac:32; uint32_t link_addr_mac:32;
}; };
@@ -155,12 +172,12 @@ typedef union {
} pau_regdma_link_mac_addr_reg_t; } pau_regdma_link_mac_addr_reg_t;
/** Type of regdma_current_link_addr register /** Type of regdma_current_link_addr register
* current link addr * Current link address register
*/ */
typedef union { typedef union {
struct { struct {
/** current_link_addr : RO; bitpos: [31:0]; default: 0; /** current_link_addr : RO; bitpos: [31:0]; default: 0;
* current link addr reg * Represents the current link address.
*/ */
uint32_t current_link_addr:32; uint32_t current_link_addr:32;
}; };
@@ -168,12 +185,12 @@ typedef union {
} pau_regdma_current_link_addr_reg_t; } pau_regdma_current_link_addr_reg_t;
/** Type of regdma_backup_addr register /** Type of regdma_backup_addr register
* Backup addr * Backup address register
*/ */
typedef union { typedef union {
struct { struct {
/** backup_addr : RO; bitpos: [31:0]; default: 0; /** backup_addr : RO; bitpos: [31:0]; default: 0;
* backup addr reg * Represents the backup address.
*/ */
uint32_t backup_addr:32; uint32_t backup_addr:32;
}; };
@@ -181,12 +198,12 @@ typedef union {
} pau_regdma_backup_addr_reg_t; } pau_regdma_backup_addr_reg_t;
/** Type of regdma_mem_addr register /** Type of regdma_mem_addr register
* mem addr * Memory address configuration register
*/ */
typedef union { typedef union {
struct { struct {
/** mem_addr : RO; bitpos: [31:0]; default: 0; /** mem_addr : RO; bitpos: [31:0]; default: 0;
* mem addr reg * Represents the memory address.
*/ */
uint32_t mem_addr:32; uint32_t mem_addr:32;
}; };
@@ -194,24 +211,24 @@ typedef union {
} pau_regdma_mem_addr_reg_t; } pau_regdma_mem_addr_reg_t;
/** Type of regdma_bkp_conf register /** Type of regdma_bkp_conf register
* backup config * Link configuration register
*/ */
typedef union { typedef union {
struct { struct {
/** read_interval : R/W; bitpos: [6:0]; default: 32; /** read_interval : R/W; bitpos: [6:0]; default: 32;
* Link read_interval * Configures the read interval for the link.
*/ */
uint32_t read_interval:7; uint32_t read_interval:7;
/** link_tout_thres : R/W; bitpos: [16:7]; default: 50; /** link_tout_thres : R/W; bitpos: [16:7]; default: 50;
* link wait timeout threshold * Configures the link wait timeout threshold.
*/ */
uint32_t link_tout_thres:10; uint32_t link_tout_thres:10;
/** burst_limit : R/W; bitpos: [21:17]; default: 8; /** burst_limit : R/W; bitpos: [21:17]; default: 8;
* burst limit * Configures the burst limit.
*/ */
uint32_t burst_limit:5; uint32_t burst_limit:5;
/** backup_tout_thres : R/W; bitpos: [31:22]; default: 500; /** backup_tout_thres : R/W; bitpos: [31:22]; default: 500;
* Backup timeout threshold * Configures the backup timeout threshold.
*/ */
uint32_t backup_tout_thres:10; uint32_t backup_tout_thres:10;
}; };
@@ -219,16 +236,16 @@ typedef union {
} pau_regdma_bkp_conf_reg_t; } pau_regdma_bkp_conf_reg_t;
/** Type of int_ena register /** Type of int_ena register
* Read only register for error and done * Interrupt register
*/ */
typedef union { typedef union {
struct { struct {
/** done_int_ena : R/W; bitpos: [0]; default: 0; /** done_int_ena : R/W; bitpos: [0]; default: 0;
* backup done flag * Write 1 to enable backup done interrupt.
*/ */
uint32_t done_int_ena:1; uint32_t done_int_ena:1;
/** error_int_ena : R/W; bitpos: [1]; default: 0; /** error_int_ena : R/W; bitpos: [1]; default: 0;
* error flag * Write 1 to enable error interrupt.
*/ */
uint32_t error_int_ena:1; uint32_t error_int_ena:1;
uint32_t reserved_2:30; uint32_t reserved_2:30;
@@ -237,16 +254,16 @@ typedef union {
} pau_int_ena_reg_t; } pau_int_ena_reg_t;
/** Type of int_raw register /** Type of int_raw register
* Read only register for error and done * Interrupt register
*/ */
typedef union { typedef union {
struct { struct {
/** done_int_raw : R/WTC/SS; bitpos: [0]; default: 0; /** done_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
* backup done flag * The raw interrupt status for backup completion.
*/ */
uint32_t done_int_raw:1; uint32_t done_int_raw:1;
/** error_int_raw : R/WTC/SS; bitpos: [1]; default: 0; /** error_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
* error flag * The raw interrupt status for errors.
*/ */
uint32_t error_int_raw:1; uint32_t error_int_raw:1;
uint32_t reserved_2:30; uint32_t reserved_2:30;
@@ -255,16 +272,16 @@ typedef union {
} pau_int_raw_reg_t; } pau_int_raw_reg_t;
/** Type of int_clr register /** Type of int_clr register
* Read only register for error and done * Interrupt register
*/ */
typedef union { typedef union {
struct { struct {
/** done_int_clr : WT; bitpos: [0]; default: 0; /** done_int_clr : WT; bitpos: [0]; default: 0;
* backup done flag * Write 1 to clear the backup done interrupt.
*/ */
uint32_t done_int_clr:1; uint32_t done_int_clr:1;
/** error_int_clr : WT; bitpos: [1]; default: 0; /** error_int_clr : WT; bitpos: [1]; default: 0;
* error flag * Write 1 to clear the error interrupt.
*/ */
uint32_t error_int_clr:1; uint32_t error_int_clr:1;
uint32_t reserved_2:30; uint32_t reserved_2:30;
@@ -273,16 +290,16 @@ typedef union {
} pau_int_clr_reg_t; } pau_int_clr_reg_t;
/** Type of int_st register /** Type of int_st register
* Read only register for error and done * Interrupt register
*/ */
typedef union { typedef union {
struct { struct {
/** done_int_st : RO; bitpos: [0]; default: 0; /** done_int_st : RO; bitpos: [0]; default: 0;
* backup done flag * Represents the backup completion status.
*/ */
uint32_t done_int_st:1; uint32_t done_int_st:1;
/** error_int_st : RO; bitpos: [1]; default: 0; /** error_int_st : RO; bitpos: [1]; default: 0;
* error flag * Represents the error status.
*/ */
uint32_t error_int_st:1; uint32_t error_int_st:1;
uint32_t reserved_2:30; uint32_t reserved_2:30;
@@ -293,12 +310,12 @@ typedef union {
/** Group: Version Register */ /** Group: Version Register */
/** Type of date register /** Type of date register
* Date register. * Version control register
*/ */
typedef union { typedef union {
struct { struct {
/** date : R/W; bitpos: [27:0]; default: 36708608; /** date : R/W; bitpos: [27:0]; default: 36708608;
* REGDMA date information/ REGDMA version information. * Version control register.
*/ */
uint32_t date:28; uint32_t date:28;
uint32_t reserved_28:4; uint32_t reserved_28:4;
components/soc/esp32c61/register/soc/pmu_reg.h
+846 -427
View File
File diff suppressed because it is too large Load Diff
components/soc/esp32c61/register/soc/pmu_struct.h
-1
View File
@@ -208,7 +208,6 @@ typedef struct pmu_hp_hw_regmap_t{
pmu_hp_xtal_reg_t xtal; pmu_hp_xtal_reg_t xtal;
} pmu_hp_hw_regmap_t; } pmu_hp_hw_regmap_t;
/** */
typedef union { typedef union {
struct { struct {
uint32_t reserved0: 21; uint32_t reserved0: 21;