diff --git a/components/esp_hal_dma/esp32c61/include/hal/ahb_dma_ll.h b/components/esp_hal_dma/esp32c61/include/hal/ahb_dma_ll.h index 1372aa552d4..b5ae691b50e 100644 --- a/components/esp_hal_dma/esp32c61/include/hal/ahb_dma_ll.h +++ b/components/esp_hal_dma/esp32c61/include/hal/ahb_dma_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -233,9 +233,6 @@ static inline void ahb_dma_ll_rx_set_burst_size(ahb_dma_dev_t *dev, uint32_t cha case 32: burst_mode = 2; // incr8 break; - case 64: - burst_mode = 3; // incr16 - break; default: HAL_ASSERT(false); break; @@ -511,9 +508,6 @@ static inline void ahb_dma_ll_tx_set_burst_size(ahb_dma_dev_t *dev, uint32_t cha case 32: burst_mode = 2; // incr8 break; - case 64: - burst_mode = 3; // incr16 - break; default: HAL_ASSERT(false); break; diff --git a/components/soc/esp32c61/register/soc/ahb_dma_reg.h b/components/soc/esp32c61/register/soc/ahb_dma_reg.h index c1a6e9375dc..1e370a652ee 100644 --- a/components/soc/esp32c61/register/soc/ahb_dma_reg.h +++ b/components/soc/esp32c61/register/soc/ahb_dma_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -12,60 +12,60 @@ extern "C" { #endif /** AHB_DMA_IN_INT_RAW_CH0_REG register - * Raw interrupt status of RX channel 0 + * RX channel 0 raw interrupt status register */ #define AHB_DMA_IN_INT_RAW_CH0_REG (DR_REG_AHB_DMA_BASE + 0x0) /** AHB_DMA_IN_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt status of AHB_DMA_IN_DONE_CH0_INT + * The raw interrupt status of AHB_DMA_IN_DONE_CH0_INT. */ #define AHB_DMA_IN_DONE_CH0_INT_RAW (BIT(0)) #define AHB_DMA_IN_DONE_CH0_INT_RAW_M (AHB_DMA_IN_DONE_CH0_INT_RAW_V << AHB_DMA_IN_DONE_CH0_INT_RAW_S) #define AHB_DMA_IN_DONE_CH0_INT_RAW_V 0x00000001U #define AHB_DMA_IN_DONE_CH0_INT_RAW_S 0 /** AHB_DMA_IN_SUC_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt status of AHB_DMA_IN_SUC_EOF_CH0_INT + * The raw interrupt status of AHB_DMA_IN_SUC_EOF_CH0_INT. */ #define AHB_DMA_IN_SUC_EOF_CH0_INT_RAW (BIT(1)) #define AHB_DMA_IN_SUC_EOF_CH0_INT_RAW_M (AHB_DMA_IN_SUC_EOF_CH0_INT_RAW_V << AHB_DMA_IN_SUC_EOF_CH0_INT_RAW_S) #define AHB_DMA_IN_SUC_EOF_CH0_INT_RAW_V 0x00000001U #define AHB_DMA_IN_SUC_EOF_CH0_INT_RAW_S 1 /** AHB_DMA_IN_ERR_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt status of AHB_DMA_IN_ERR_EOF_CH0_INT + * Reserved. */ #define AHB_DMA_IN_ERR_EOF_CH0_INT_RAW (BIT(2)) #define AHB_DMA_IN_ERR_EOF_CH0_INT_RAW_M (AHB_DMA_IN_ERR_EOF_CH0_INT_RAW_V << AHB_DMA_IN_ERR_EOF_CH0_INT_RAW_S) #define AHB_DMA_IN_ERR_EOF_CH0_INT_RAW_V 0x00000001U #define AHB_DMA_IN_ERR_EOF_CH0_INT_RAW_S 2 /** AHB_DMA_IN_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt status of AHB_DMA_IN_DSCR_ERR_CH0_INT + * The raw interrupt status of AHB_DMA_IN_DSCR_ERR_CH0_INT. */ #define AHB_DMA_IN_DSCR_ERR_CH0_INT_RAW (BIT(3)) #define AHB_DMA_IN_DSCR_ERR_CH0_INT_RAW_M (AHB_DMA_IN_DSCR_ERR_CH0_INT_RAW_V << AHB_DMA_IN_DSCR_ERR_CH0_INT_RAW_S) #define AHB_DMA_IN_DSCR_ERR_CH0_INT_RAW_V 0x00000001U #define AHB_DMA_IN_DSCR_ERR_CH0_INT_RAW_S 3 /** AHB_DMA_IN_DSCR_EMPTY_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH0_INT + * The raw interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH0_INT. */ #define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_RAW (BIT(4)) #define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_M (AHB_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_V << AHB_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_S) #define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_V 0x00000001U #define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_S 4 /** AHB_DMA_INFIFO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt status of AHB_DMA_INFIFO_OVF_CH0_INT + * The raw interrupt status of AHB_DMA_INFIFO_OVF_CH0_INT. */ #define AHB_DMA_INFIFO_OVF_CH0_INT_RAW (BIT(5)) #define AHB_DMA_INFIFO_OVF_CH0_INT_RAW_M (AHB_DMA_INFIFO_OVF_CH0_INT_RAW_V << AHB_DMA_INFIFO_OVF_CH0_INT_RAW_S) #define AHB_DMA_INFIFO_OVF_CH0_INT_RAW_V 0x00000001U #define AHB_DMA_INFIFO_OVF_CH0_INT_RAW_S 5 /** AHB_DMA_INFIFO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt status of AHB_DMA_INFIFO_UDF_CH0_INT + * The raw interrupt status of AHB_DMA_INFIFO_UDF_CH0_INT. */ #define AHB_DMA_INFIFO_UDF_CH0_INT_RAW (BIT(6)) #define AHB_DMA_INFIFO_UDF_CH0_INT_RAW_M (AHB_DMA_INFIFO_UDF_CH0_INT_RAW_V << AHB_DMA_INFIFO_UDF_CH0_INT_RAW_S) #define AHB_DMA_INFIFO_UDF_CH0_INT_RAW_V 0x00000001U #define AHB_DMA_INFIFO_UDF_CH0_INT_RAW_S 6 /** AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt status of AHB_DMA_IN_RESP_ERR_CH0_INT + * The raw interrupt status of AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT. */ #define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_RAW (BIT(7)) #define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_RAW_M (AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_RAW_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_RAW_S) @@ -73,60 +73,60 @@ extern "C" { #define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_RAW_S 7 /** AHB_DMA_IN_INT_ST_CH0_REG register - * Masked interrupt status of RX channel 0 + * RX channel 0 masked interrupt status register */ #define AHB_DMA_IN_INT_ST_CH0_REG (DR_REG_AHB_DMA_BASE + 0x4) /** AHB_DMA_IN_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0; - * The masked interrupt status of AHB_DMA_IN_DONE_CH0_INT + * The masked interrupt status of AHB_DMA_IN_DONE_CH0_INT. */ #define AHB_DMA_IN_DONE_CH0_INT_ST (BIT(0)) #define AHB_DMA_IN_DONE_CH0_INT_ST_M (AHB_DMA_IN_DONE_CH0_INT_ST_V << AHB_DMA_IN_DONE_CH0_INT_ST_S) #define AHB_DMA_IN_DONE_CH0_INT_ST_V 0x00000001U #define AHB_DMA_IN_DONE_CH0_INT_ST_S 0 /** AHB_DMA_IN_SUC_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0; - * The masked interrupt status of AHB_DMA_IN_SUC_EOF_CH0_INT + * The masked interrupt status of AHB_DMA_IN_SUC_EOF_CH0_INT. */ #define AHB_DMA_IN_SUC_EOF_CH0_INT_ST (BIT(1)) #define AHB_DMA_IN_SUC_EOF_CH0_INT_ST_M (AHB_DMA_IN_SUC_EOF_CH0_INT_ST_V << AHB_DMA_IN_SUC_EOF_CH0_INT_ST_S) #define AHB_DMA_IN_SUC_EOF_CH0_INT_ST_V 0x00000001U #define AHB_DMA_IN_SUC_EOF_CH0_INT_ST_S 1 /** AHB_DMA_IN_ERR_EOF_CH0_INT_ST : RO; bitpos: [2]; default: 0; - * The masked interrupt status of AHB_DMA_IN_ERR_EOF_CH0_INT + * Reserved. */ #define AHB_DMA_IN_ERR_EOF_CH0_INT_ST (BIT(2)) #define AHB_DMA_IN_ERR_EOF_CH0_INT_ST_M (AHB_DMA_IN_ERR_EOF_CH0_INT_ST_V << AHB_DMA_IN_ERR_EOF_CH0_INT_ST_S) #define AHB_DMA_IN_ERR_EOF_CH0_INT_ST_V 0x00000001U #define AHB_DMA_IN_ERR_EOF_CH0_INT_ST_S 2 /** AHB_DMA_IN_DSCR_ERR_CH0_INT_ST : RO; bitpos: [3]; default: 0; - * The masked interrupt status of AHB_DMA_IN_DSCR_ERR_CH0_INT + * The masked interrupt status of AHB_DMA_IN_DSCR_ERR_CH0_INT. */ #define AHB_DMA_IN_DSCR_ERR_CH0_INT_ST (BIT(3)) #define AHB_DMA_IN_DSCR_ERR_CH0_INT_ST_M (AHB_DMA_IN_DSCR_ERR_CH0_INT_ST_V << AHB_DMA_IN_DSCR_ERR_CH0_INT_ST_S) #define AHB_DMA_IN_DSCR_ERR_CH0_INT_ST_V 0x00000001U #define AHB_DMA_IN_DSCR_ERR_CH0_INT_ST_S 3 /** AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ST : RO; bitpos: [4]; default: 0; - * The masked interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH0_INT + * The masked interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH0_INT. */ #define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ST (BIT(4)) #define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ST_M (AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ST_V << AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ST_S) #define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ST_V 0x00000001U #define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ST_S 4 /** AHB_DMA_INFIFO_OVF_CH0_INT_ST : RO; bitpos: [5]; default: 0; - * The masked interrupt status of AHB_DMA_INFIFO_OVF_CH0_INT + * The masked interrupt status of AHB_DMA_INFIFO_OVF_CH0_INT. */ #define AHB_DMA_INFIFO_OVF_CH0_INT_ST (BIT(5)) #define AHB_DMA_INFIFO_OVF_CH0_INT_ST_M (AHB_DMA_INFIFO_OVF_CH0_INT_ST_V << AHB_DMA_INFIFO_OVF_CH0_INT_ST_S) #define AHB_DMA_INFIFO_OVF_CH0_INT_ST_V 0x00000001U #define AHB_DMA_INFIFO_OVF_CH0_INT_ST_S 5 /** AHB_DMA_INFIFO_UDF_CH0_INT_ST : RO; bitpos: [6]; default: 0; - * The masked interrupt status of AHB_DMA_INFIFO_UDF_CH0_INT + * The masked interrupt status of AHB_DMA_INFIFO_UDF_CH0_INT. */ #define AHB_DMA_INFIFO_UDF_CH0_INT_ST (BIT(6)) #define AHB_DMA_INFIFO_UDF_CH0_INT_ST_M (AHB_DMA_INFIFO_UDF_CH0_INT_ST_V << AHB_DMA_INFIFO_UDF_CH0_INT_ST_S) #define AHB_DMA_INFIFO_UDF_CH0_INT_ST_V 0x00000001U #define AHB_DMA_INFIFO_UDF_CH0_INT_ST_S 6 /** AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ST : RO; bitpos: [7]; default: 0; - * The masked interrupt status of AHB_DMA_IN_RESP_ERR_CH0_INT + * The masked interrupt status of AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT. */ #define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ST (BIT(7)) #define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ST_M (AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ST_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ST_S) @@ -134,60 +134,60 @@ extern "C" { #define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ST_S 7 /** AHB_DMA_IN_INT_ENA_CH0_REG register - * Interrupt enable bits of RX channel 0 + * RX channel 0 interrupt enable register */ #define AHB_DMA_IN_INT_ENA_CH0_REG (DR_REG_AHB_DMA_BASE + 0x8) /** AHB_DMA_IN_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0; - * Write 1 to enable AHB_DMA_IN_DONE_CH0_INT + * Write 1 to enable AHB_DMA_IN_DONE_CH0_INT. */ #define AHB_DMA_IN_DONE_CH0_INT_ENA (BIT(0)) #define AHB_DMA_IN_DONE_CH0_INT_ENA_M (AHB_DMA_IN_DONE_CH0_INT_ENA_V << AHB_DMA_IN_DONE_CH0_INT_ENA_S) #define AHB_DMA_IN_DONE_CH0_INT_ENA_V 0x00000001U #define AHB_DMA_IN_DONE_CH0_INT_ENA_S 0 /** AHB_DMA_IN_SUC_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0; - * Write 1 to enable AHB_DMA_IN_SUC_EOF_CH0_INT + * Write 1 to enable AHB_DMA_IN_SUC_EOF_CH0_INT. */ #define AHB_DMA_IN_SUC_EOF_CH0_INT_ENA (BIT(1)) #define AHB_DMA_IN_SUC_EOF_CH0_INT_ENA_M (AHB_DMA_IN_SUC_EOF_CH0_INT_ENA_V << AHB_DMA_IN_SUC_EOF_CH0_INT_ENA_S) #define AHB_DMA_IN_SUC_EOF_CH0_INT_ENA_V 0x00000001U #define AHB_DMA_IN_SUC_EOF_CH0_INT_ENA_S 1 /** AHB_DMA_IN_ERR_EOF_CH0_INT_ENA : R/W; bitpos: [2]; default: 0; - * Write 1 to enable AHB_DMA_IN_ERR_EOF_CH0_INT + * Reserved. */ #define AHB_DMA_IN_ERR_EOF_CH0_INT_ENA (BIT(2)) #define AHB_DMA_IN_ERR_EOF_CH0_INT_ENA_M (AHB_DMA_IN_ERR_EOF_CH0_INT_ENA_V << AHB_DMA_IN_ERR_EOF_CH0_INT_ENA_S) #define AHB_DMA_IN_ERR_EOF_CH0_INT_ENA_V 0x00000001U #define AHB_DMA_IN_ERR_EOF_CH0_INT_ENA_S 2 /** AHB_DMA_IN_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [3]; default: 0; - * Write 1 to enable AHB_DMA_IN_DSCR_ERR_CH0_INT + * Write 1 to enable AHB_DMA_IN_DSCR_ERR_CH0_INT. */ #define AHB_DMA_IN_DSCR_ERR_CH0_INT_ENA (BIT(3)) #define AHB_DMA_IN_DSCR_ERR_CH0_INT_ENA_M (AHB_DMA_IN_DSCR_ERR_CH0_INT_ENA_V << AHB_DMA_IN_DSCR_ERR_CH0_INT_ENA_S) #define AHB_DMA_IN_DSCR_ERR_CH0_INT_ENA_V 0x00000001U #define AHB_DMA_IN_DSCR_ERR_CH0_INT_ENA_S 3 /** AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ENA : R/W; bitpos: [4]; default: 0; - * Write 1 to enable AHB_DMA_IN_DSCR_EMPTY_CH0_INT + * Write 1 to enable AHB_DMA_IN_DSCR_EMPTY_CH0_INT. */ #define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ENA (BIT(4)) #define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_M (AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_V << AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_S) #define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_V 0x00000001U #define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_S 4 /** AHB_DMA_INFIFO_OVF_CH0_INT_ENA : R/W; bitpos: [5]; default: 0; - * Write 1 to enable AHB_DMA_INFIFO_OVF_CH0_INT + * Write 1 to enable AHB_DMA_INFIFO_OVF_CH0_INT. */ #define AHB_DMA_INFIFO_OVF_CH0_INT_ENA (BIT(5)) #define AHB_DMA_INFIFO_OVF_CH0_INT_ENA_M (AHB_DMA_INFIFO_OVF_CH0_INT_ENA_V << AHB_DMA_INFIFO_OVF_CH0_INT_ENA_S) #define AHB_DMA_INFIFO_OVF_CH0_INT_ENA_V 0x00000001U #define AHB_DMA_INFIFO_OVF_CH0_INT_ENA_S 5 /** AHB_DMA_INFIFO_UDF_CH0_INT_ENA : R/W; bitpos: [6]; default: 0; - * Write 1 to enable AHB_DMA_INFIFO_UDF_CH0_INT + * Write 1 to enable AHB_DMA_INFIFO_UDF_CH0_INT. */ #define AHB_DMA_INFIFO_UDF_CH0_INT_ENA (BIT(6)) #define AHB_DMA_INFIFO_UDF_CH0_INT_ENA_M (AHB_DMA_INFIFO_UDF_CH0_INT_ENA_V << AHB_DMA_INFIFO_UDF_CH0_INT_ENA_S) #define AHB_DMA_INFIFO_UDF_CH0_INT_ENA_V 0x00000001U #define AHB_DMA_INFIFO_UDF_CH0_INT_ENA_S 6 /** AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ENA : R/W; bitpos: [7]; default: 0; - * Write 1 to enable AHB_DMA_IN_RESP_ERR_CH0_INT + * Write 1 to enable AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT. */ #define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ENA (BIT(7)) #define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ENA_M (AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ENA_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ENA_S) @@ -195,60 +195,60 @@ extern "C" { #define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ENA_S 7 /** AHB_DMA_IN_INT_CLR_CH0_REG register - * Interrupt clear bits of RX channel 0 + * RX channel 0 interrupt clear register */ #define AHB_DMA_IN_INT_CLR_CH0_REG (DR_REG_AHB_DMA_BASE + 0xc) /** AHB_DMA_IN_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0; - * Write 1 to clear AHB_DMA_IN_DONE_CH0_INT + * Write 1 to clear AHB_DMA_IN_DONE_CH0_INT. */ #define AHB_DMA_IN_DONE_CH0_INT_CLR (BIT(0)) #define AHB_DMA_IN_DONE_CH0_INT_CLR_M (AHB_DMA_IN_DONE_CH0_INT_CLR_V << AHB_DMA_IN_DONE_CH0_INT_CLR_S) #define AHB_DMA_IN_DONE_CH0_INT_CLR_V 0x00000001U #define AHB_DMA_IN_DONE_CH0_INT_CLR_S 0 /** AHB_DMA_IN_SUC_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0; - * Write 1 to clear AHB_DMA_IN_SUC_EOF_CH0_INT + * Write 1 to clear AHB_DMA_IN_SUC_EOF_CH0_INT. */ #define AHB_DMA_IN_SUC_EOF_CH0_INT_CLR (BIT(1)) #define AHB_DMA_IN_SUC_EOF_CH0_INT_CLR_M (AHB_DMA_IN_SUC_EOF_CH0_INT_CLR_V << AHB_DMA_IN_SUC_EOF_CH0_INT_CLR_S) #define AHB_DMA_IN_SUC_EOF_CH0_INT_CLR_V 0x00000001U #define AHB_DMA_IN_SUC_EOF_CH0_INT_CLR_S 1 /** AHB_DMA_IN_ERR_EOF_CH0_INT_CLR : WT; bitpos: [2]; default: 0; - * Write 1 to clear AHB_DMA_IN_ERR_EOF_CH0_INT + * Reserved. */ #define AHB_DMA_IN_ERR_EOF_CH0_INT_CLR (BIT(2)) #define AHB_DMA_IN_ERR_EOF_CH0_INT_CLR_M (AHB_DMA_IN_ERR_EOF_CH0_INT_CLR_V << AHB_DMA_IN_ERR_EOF_CH0_INT_CLR_S) #define AHB_DMA_IN_ERR_EOF_CH0_INT_CLR_V 0x00000001U #define AHB_DMA_IN_ERR_EOF_CH0_INT_CLR_S 2 /** AHB_DMA_IN_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [3]; default: 0; - * Write 1 to clear AHB_DMA_IN_DSCR_ERR_CH0_INT + * Write 1 to clear AHB_DMA_IN_DSCR_ERR_CH0_INT. */ #define AHB_DMA_IN_DSCR_ERR_CH0_INT_CLR (BIT(3)) #define AHB_DMA_IN_DSCR_ERR_CH0_INT_CLR_M (AHB_DMA_IN_DSCR_ERR_CH0_INT_CLR_V << AHB_DMA_IN_DSCR_ERR_CH0_INT_CLR_S) #define AHB_DMA_IN_DSCR_ERR_CH0_INT_CLR_V 0x00000001U #define AHB_DMA_IN_DSCR_ERR_CH0_INT_CLR_S 3 /** AHB_DMA_IN_DSCR_EMPTY_CH0_INT_CLR : WT; bitpos: [4]; default: 0; - * Write 1 to clear AHB_DMA_IN_DSCR_EMPTY_CH0_INT + * Write 1 to clear AHB_DMA_IN_DSCR_EMPTY_CH0_INT. */ #define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_CLR (BIT(4)) #define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_M (AHB_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_V << AHB_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_S) #define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_V 0x00000001U #define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_S 4 /** AHB_DMA_INFIFO_OVF_CH0_INT_CLR : WT; bitpos: [5]; default: 0; - * Write 1 to clear AHB_DMA_INFIFO_OVF_CH0_INT + * Write 1 to clear AHB_DMA_INFIFO_OVF_CH0_INT. */ #define AHB_DMA_INFIFO_OVF_CH0_INT_CLR (BIT(5)) #define AHB_DMA_INFIFO_OVF_CH0_INT_CLR_M (AHB_DMA_INFIFO_OVF_CH0_INT_CLR_V << AHB_DMA_INFIFO_OVF_CH0_INT_CLR_S) #define AHB_DMA_INFIFO_OVF_CH0_INT_CLR_V 0x00000001U #define AHB_DMA_INFIFO_OVF_CH0_INT_CLR_S 5 /** AHB_DMA_INFIFO_UDF_CH0_INT_CLR : WT; bitpos: [6]; default: 0; - * Write 1 to clear AHB_DMA_INFIFO_UDF_CH0_INT + * Write 1 to clear AHB_DMA_INFIFO_UDF_CH0_INT. */ #define AHB_DMA_INFIFO_UDF_CH0_INT_CLR (BIT(6)) #define AHB_DMA_INFIFO_UDF_CH0_INT_CLR_M (AHB_DMA_INFIFO_UDF_CH0_INT_CLR_V << AHB_DMA_INFIFO_UDF_CH0_INT_CLR_S) #define AHB_DMA_INFIFO_UDF_CH0_INT_CLR_V 0x00000001U #define AHB_DMA_INFIFO_UDF_CH0_INT_CLR_S 6 /** AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_CLR : WT; bitpos: [7]; default: 0; - * Write 1 to clear AHB_DMA_IN_RESP_ERR_CH0_INT + * Write 1 to clear AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT. */ #define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_CLR (BIT(7)) #define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_CLR_M (AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_CLR_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_CLR_S) @@ -256,60 +256,60 @@ extern "C" { #define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_CLR_S 7 /** AHB_DMA_IN_INT_RAW_CH1_REG register - * Raw interrupt status of RX channel 1 + * RX channel 1 raw interrupt status register */ #define AHB_DMA_IN_INT_RAW_CH1_REG (DR_REG_AHB_DMA_BASE + 0x10) /** AHB_DMA_IN_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt status of AHB_DMA_IN_DONE_CH1_INT + * The raw interrupt status of AHB_DMA_IN_DONE_CH1_INT. */ #define AHB_DMA_IN_DONE_CH1_INT_RAW (BIT(0)) #define AHB_DMA_IN_DONE_CH1_INT_RAW_M (AHB_DMA_IN_DONE_CH1_INT_RAW_V << AHB_DMA_IN_DONE_CH1_INT_RAW_S) #define AHB_DMA_IN_DONE_CH1_INT_RAW_V 0x00000001U #define AHB_DMA_IN_DONE_CH1_INT_RAW_S 0 /** AHB_DMA_IN_SUC_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt status of AHB_DMA_IN_SUC_EOF_CH1_INT + * The raw interrupt status of AHB_DMA_IN_SUC_EOF_CH1_INT. */ #define AHB_DMA_IN_SUC_EOF_CH1_INT_RAW (BIT(1)) #define AHB_DMA_IN_SUC_EOF_CH1_INT_RAW_M (AHB_DMA_IN_SUC_EOF_CH1_INT_RAW_V << AHB_DMA_IN_SUC_EOF_CH1_INT_RAW_S) #define AHB_DMA_IN_SUC_EOF_CH1_INT_RAW_V 0x00000001U #define AHB_DMA_IN_SUC_EOF_CH1_INT_RAW_S 1 /** AHB_DMA_IN_ERR_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt status of AHB_DMA_IN_ERR_EOF_CH1_INT + * Reserved. */ #define AHB_DMA_IN_ERR_EOF_CH1_INT_RAW (BIT(2)) #define AHB_DMA_IN_ERR_EOF_CH1_INT_RAW_M (AHB_DMA_IN_ERR_EOF_CH1_INT_RAW_V << AHB_DMA_IN_ERR_EOF_CH1_INT_RAW_S) #define AHB_DMA_IN_ERR_EOF_CH1_INT_RAW_V 0x00000001U #define AHB_DMA_IN_ERR_EOF_CH1_INT_RAW_S 2 /** AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt status of AHB_DMA_IN_DSCR_ERR_CH1_INT + * The raw interrupt status of AHB_DMA_IN_DSCR_ERR_CH1_INT. */ #define AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW (BIT(3)) #define AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW_M (AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW_V << AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW_S) #define AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW_V 0x00000001U #define AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW_S 3 /** AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH1_INT + * The raw interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH1_INT. */ #define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW (BIT(4)) #define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_M (AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_V << AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_S) #define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_V 0x00000001U #define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_S 4 /** AHB_DMA_INFIFO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt status of AHB_DMA_INFIFO_OVF_CH1_INT + * The raw interrupt status of AHB_DMA_INFIFO_OVF_CH1_INT. */ #define AHB_DMA_INFIFO_OVF_CH1_INT_RAW (BIT(5)) #define AHB_DMA_INFIFO_OVF_CH1_INT_RAW_M (AHB_DMA_INFIFO_OVF_CH1_INT_RAW_V << AHB_DMA_INFIFO_OVF_CH1_INT_RAW_S) #define AHB_DMA_INFIFO_OVF_CH1_INT_RAW_V 0x00000001U #define AHB_DMA_INFIFO_OVF_CH1_INT_RAW_S 5 /** AHB_DMA_INFIFO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt status of AHB_DMA_INFIFO_UDF_CH1_INT + * The raw interrupt status of AHB_DMA_INFIFO_UDF_CH1_INT. */ #define AHB_DMA_INFIFO_UDF_CH1_INT_RAW (BIT(6)) #define AHB_DMA_INFIFO_UDF_CH1_INT_RAW_M (AHB_DMA_INFIFO_UDF_CH1_INT_RAW_V << AHB_DMA_INFIFO_UDF_CH1_INT_RAW_S) #define AHB_DMA_INFIFO_UDF_CH1_INT_RAW_V 0x00000001U #define AHB_DMA_INFIFO_UDF_CH1_INT_RAW_S 6 /** AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt status of AHB_DMA_IN_RESP_ERR_CH1_INT + * The raw interrupt status of AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT. */ #define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_RAW (BIT(7)) #define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_RAW_M (AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_RAW_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_RAW_S) @@ -317,60 +317,60 @@ extern "C" { #define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_RAW_S 7 /** AHB_DMA_IN_INT_ST_CH1_REG register - * Masked interrupt status of RX channel 1 + * RX channel 1 masked interrupt status register */ #define AHB_DMA_IN_INT_ST_CH1_REG (DR_REG_AHB_DMA_BASE + 0x14) /** AHB_DMA_IN_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0; - * The masked interrupt status of AHB_DMA_IN_DONE_CH1_INT + * The masked interrupt status of AHB_DMA_IN_DONE_CH1_INT. */ #define AHB_DMA_IN_DONE_CH1_INT_ST (BIT(0)) #define AHB_DMA_IN_DONE_CH1_INT_ST_M (AHB_DMA_IN_DONE_CH1_INT_ST_V << AHB_DMA_IN_DONE_CH1_INT_ST_S) #define AHB_DMA_IN_DONE_CH1_INT_ST_V 0x00000001U #define AHB_DMA_IN_DONE_CH1_INT_ST_S 0 /** AHB_DMA_IN_SUC_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0; - * The masked interrupt status of AHB_DMA_IN_SUC_EOF_CH1_INT + * The masked interrupt status of AHB_DMA_IN_SUC_EOF_CH1_INT. */ #define AHB_DMA_IN_SUC_EOF_CH1_INT_ST (BIT(1)) #define AHB_DMA_IN_SUC_EOF_CH1_INT_ST_M (AHB_DMA_IN_SUC_EOF_CH1_INT_ST_V << AHB_DMA_IN_SUC_EOF_CH1_INT_ST_S) #define AHB_DMA_IN_SUC_EOF_CH1_INT_ST_V 0x00000001U #define AHB_DMA_IN_SUC_EOF_CH1_INT_ST_S 1 /** AHB_DMA_IN_ERR_EOF_CH1_INT_ST : RO; bitpos: [2]; default: 0; - * The masked interrupt status of AHB_DMA_IN_ERR_EOF_CH1_INT + * Reserved. */ #define AHB_DMA_IN_ERR_EOF_CH1_INT_ST (BIT(2)) #define AHB_DMA_IN_ERR_EOF_CH1_INT_ST_M (AHB_DMA_IN_ERR_EOF_CH1_INT_ST_V << AHB_DMA_IN_ERR_EOF_CH1_INT_ST_S) #define AHB_DMA_IN_ERR_EOF_CH1_INT_ST_V 0x00000001U #define AHB_DMA_IN_ERR_EOF_CH1_INT_ST_S 2 /** AHB_DMA_IN_DSCR_ERR_CH1_INT_ST : RO; bitpos: [3]; default: 0; - * The masked interrupt status of AHB_DMA_IN_DSCR_ERR_CH1_INT + * The masked interrupt status of AHB_DMA_IN_DSCR_ERR_CH1_INT. */ #define AHB_DMA_IN_DSCR_ERR_CH1_INT_ST (BIT(3)) #define AHB_DMA_IN_DSCR_ERR_CH1_INT_ST_M (AHB_DMA_IN_DSCR_ERR_CH1_INT_ST_V << AHB_DMA_IN_DSCR_ERR_CH1_INT_ST_S) #define AHB_DMA_IN_DSCR_ERR_CH1_INT_ST_V 0x00000001U #define AHB_DMA_IN_DSCR_ERR_CH1_INT_ST_S 3 /** AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ST : RO; bitpos: [4]; default: 0; - * The masked interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH1_INT + * The masked interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH1_INT. */ #define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ST (BIT(4)) #define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ST_M (AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ST_V << AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ST_S) #define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ST_V 0x00000001U #define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ST_S 4 /** AHB_DMA_INFIFO_OVF_CH1_INT_ST : RO; bitpos: [5]; default: 0; - * The masked interrupt status of AHB_DMA_INFIFO_OVF_CH1_INT + * The masked interrupt status of AHB_DMA_INFIFO_OVF_CH1_INT. */ #define AHB_DMA_INFIFO_OVF_CH1_INT_ST (BIT(5)) #define AHB_DMA_INFIFO_OVF_CH1_INT_ST_M (AHB_DMA_INFIFO_OVF_CH1_INT_ST_V << AHB_DMA_INFIFO_OVF_CH1_INT_ST_S) #define AHB_DMA_INFIFO_OVF_CH1_INT_ST_V 0x00000001U #define AHB_DMA_INFIFO_OVF_CH1_INT_ST_S 5 /** AHB_DMA_INFIFO_UDF_CH1_INT_ST : RO; bitpos: [6]; default: 0; - * The masked interrupt status of AHB_DMA_INFIFO_UDF_CH1_INT + * The masked interrupt status of AHB_DMA_INFIFO_UDF_CH1_INT. */ #define AHB_DMA_INFIFO_UDF_CH1_INT_ST (BIT(6)) #define AHB_DMA_INFIFO_UDF_CH1_INT_ST_M (AHB_DMA_INFIFO_UDF_CH1_INT_ST_V << AHB_DMA_INFIFO_UDF_CH1_INT_ST_S) #define AHB_DMA_INFIFO_UDF_CH1_INT_ST_V 0x00000001U #define AHB_DMA_INFIFO_UDF_CH1_INT_ST_S 6 /** AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ST : RO; bitpos: [7]; default: 0; - * The masked interrupt status of AHB_DMA_IN_RESP_ERR_CH1_INT + * The masked interrupt status of AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT. */ #define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ST (BIT(7)) #define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ST_M (AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ST_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ST_S) @@ -378,60 +378,60 @@ extern "C" { #define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ST_S 7 /** AHB_DMA_IN_INT_ENA_CH1_REG register - * Interrupt enable bits of RX channel 1 + * RX channel 1 interrupt enable register */ #define AHB_DMA_IN_INT_ENA_CH1_REG (DR_REG_AHB_DMA_BASE + 0x18) /** AHB_DMA_IN_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0; - * Write 1 to enable AHB_DMA_IN_DONE_CH1_INT + * Write 1 to enable AHB_DMA_IN_DONE_CH1_INT. */ #define AHB_DMA_IN_DONE_CH1_INT_ENA (BIT(0)) #define AHB_DMA_IN_DONE_CH1_INT_ENA_M (AHB_DMA_IN_DONE_CH1_INT_ENA_V << AHB_DMA_IN_DONE_CH1_INT_ENA_S) #define AHB_DMA_IN_DONE_CH1_INT_ENA_V 0x00000001U #define AHB_DMA_IN_DONE_CH1_INT_ENA_S 0 /** AHB_DMA_IN_SUC_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0; - * Write 1 to enable AHB_DMA_IN_SUC_EOF_CH1_INT + * Write 1 to enable AHB_DMA_IN_SUC_EOF_CH1_INT. */ #define AHB_DMA_IN_SUC_EOF_CH1_INT_ENA (BIT(1)) #define AHB_DMA_IN_SUC_EOF_CH1_INT_ENA_M (AHB_DMA_IN_SUC_EOF_CH1_INT_ENA_V << AHB_DMA_IN_SUC_EOF_CH1_INT_ENA_S) #define AHB_DMA_IN_SUC_EOF_CH1_INT_ENA_V 0x00000001U #define AHB_DMA_IN_SUC_EOF_CH1_INT_ENA_S 1 /** AHB_DMA_IN_ERR_EOF_CH1_INT_ENA : R/W; bitpos: [2]; default: 0; - * Write 1 to enable AHB_DMA_IN_ERR_EOF_CH1_INT + * Reserved. */ #define AHB_DMA_IN_ERR_EOF_CH1_INT_ENA (BIT(2)) #define AHB_DMA_IN_ERR_EOF_CH1_INT_ENA_M (AHB_DMA_IN_ERR_EOF_CH1_INT_ENA_V << AHB_DMA_IN_ERR_EOF_CH1_INT_ENA_S) #define AHB_DMA_IN_ERR_EOF_CH1_INT_ENA_V 0x00000001U #define AHB_DMA_IN_ERR_EOF_CH1_INT_ENA_S 2 /** AHB_DMA_IN_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [3]; default: 0; - * Write 1 to enable AHB_DMA_IN_DSCR_ERR_CH1_INT + * Write 1 to enable AHB_DMA_IN_DSCR_ERR_CH1_INT. */ #define AHB_DMA_IN_DSCR_ERR_CH1_INT_ENA (BIT(3)) #define AHB_DMA_IN_DSCR_ERR_CH1_INT_ENA_M (AHB_DMA_IN_DSCR_ERR_CH1_INT_ENA_V << AHB_DMA_IN_DSCR_ERR_CH1_INT_ENA_S) #define AHB_DMA_IN_DSCR_ERR_CH1_INT_ENA_V 0x00000001U #define AHB_DMA_IN_DSCR_ERR_CH1_INT_ENA_S 3 /** AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ENA : R/W; bitpos: [4]; default: 0; - * Write 1 to enable AHB_DMA_IN_DSCR_EMPTY_CH1_INT + * Write 1 to enable AHB_DMA_IN_DSCR_EMPTY_CH1_INT. */ #define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ENA (BIT(4)) #define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_M (AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_V << AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_S) #define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_V 0x00000001U #define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_S 4 /** AHB_DMA_INFIFO_OVF_CH1_INT_ENA : R/W; bitpos: [5]; default: 0; - * Write 1 to enable AHB_DMA_INFIFO_OVF_CH1_INT + * Write 1 to enable AHB_DMA_INFIFO_OVF_CH1_INT. */ #define AHB_DMA_INFIFO_OVF_CH1_INT_ENA (BIT(5)) #define AHB_DMA_INFIFO_OVF_CH1_INT_ENA_M (AHB_DMA_INFIFO_OVF_CH1_INT_ENA_V << AHB_DMA_INFIFO_OVF_CH1_INT_ENA_S) #define AHB_DMA_INFIFO_OVF_CH1_INT_ENA_V 0x00000001U #define AHB_DMA_INFIFO_OVF_CH1_INT_ENA_S 5 /** AHB_DMA_INFIFO_UDF_CH1_INT_ENA : R/W; bitpos: [6]; default: 0; - * Write 1 to enable AHB_DMA_INFIFO_UDF_CH1_INT + * Write 1 to enable AHB_DMA_INFIFO_UDF_CH1_INT. */ #define AHB_DMA_INFIFO_UDF_CH1_INT_ENA (BIT(6)) #define AHB_DMA_INFIFO_UDF_CH1_INT_ENA_M (AHB_DMA_INFIFO_UDF_CH1_INT_ENA_V << AHB_DMA_INFIFO_UDF_CH1_INT_ENA_S) #define AHB_DMA_INFIFO_UDF_CH1_INT_ENA_V 0x00000001U #define AHB_DMA_INFIFO_UDF_CH1_INT_ENA_S 6 /** AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ENA : R/W; bitpos: [7]; default: 0; - * Write 1 to enable AHB_DMA_IN_RESP_ERR_CH1_INT + * Write 1 to enable AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT. */ #define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ENA (BIT(7)) #define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ENA_M (AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ENA_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ENA_S) @@ -439,60 +439,60 @@ extern "C" { #define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ENA_S 7 /** AHB_DMA_IN_INT_CLR_CH1_REG register - * Interrupt clear bits of RX channel 1 + * RX channel 1 interrupt clear register */ #define AHB_DMA_IN_INT_CLR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1c) /** AHB_DMA_IN_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0; - * Write 1 to clear AHB_DMA_IN_DONE_CH1_INT + * Write 1 to clear AHB_DMA_IN_DONE_CH1_INT. */ #define AHB_DMA_IN_DONE_CH1_INT_CLR (BIT(0)) #define AHB_DMA_IN_DONE_CH1_INT_CLR_M (AHB_DMA_IN_DONE_CH1_INT_CLR_V << AHB_DMA_IN_DONE_CH1_INT_CLR_S) #define AHB_DMA_IN_DONE_CH1_INT_CLR_V 0x00000001U #define AHB_DMA_IN_DONE_CH1_INT_CLR_S 0 /** AHB_DMA_IN_SUC_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0; - * Write 1 to clear AHB_DMA_IN_SUC_EOF_CH1_INT + * Write 1 to clear AHB_DMA_IN_SUC_EOF_CH1_INT. */ #define AHB_DMA_IN_SUC_EOF_CH1_INT_CLR (BIT(1)) #define AHB_DMA_IN_SUC_EOF_CH1_INT_CLR_M (AHB_DMA_IN_SUC_EOF_CH1_INT_CLR_V << AHB_DMA_IN_SUC_EOF_CH1_INT_CLR_S) #define AHB_DMA_IN_SUC_EOF_CH1_INT_CLR_V 0x00000001U #define AHB_DMA_IN_SUC_EOF_CH1_INT_CLR_S 1 /** AHB_DMA_IN_ERR_EOF_CH1_INT_CLR : WT; bitpos: [2]; default: 0; - * Write 1 to clear AHB_DMA_IN_ERR_EOF_CH1_INT + * Reserved. */ #define AHB_DMA_IN_ERR_EOF_CH1_INT_CLR (BIT(2)) #define AHB_DMA_IN_ERR_EOF_CH1_INT_CLR_M (AHB_DMA_IN_ERR_EOF_CH1_INT_CLR_V << AHB_DMA_IN_ERR_EOF_CH1_INT_CLR_S) #define AHB_DMA_IN_ERR_EOF_CH1_INT_CLR_V 0x00000001U #define AHB_DMA_IN_ERR_EOF_CH1_INT_CLR_S 2 /** AHB_DMA_IN_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [3]; default: 0; - * Write 1 to clear AHB_DMA_IN_DSCR_ERR_CH1_INT + * Write 1 to clear AHB_DMA_IN_DSCR_ERR_CH1_INT. */ #define AHB_DMA_IN_DSCR_ERR_CH1_INT_CLR (BIT(3)) #define AHB_DMA_IN_DSCR_ERR_CH1_INT_CLR_M (AHB_DMA_IN_DSCR_ERR_CH1_INT_CLR_V << AHB_DMA_IN_DSCR_ERR_CH1_INT_CLR_S) #define AHB_DMA_IN_DSCR_ERR_CH1_INT_CLR_V 0x00000001U #define AHB_DMA_IN_DSCR_ERR_CH1_INT_CLR_S 3 /** AHB_DMA_IN_DSCR_EMPTY_CH1_INT_CLR : WT; bitpos: [4]; default: 0; - * Write 1 to clear AHB_DMA_IN_DSCR_EMPTY_CH1_INT + * Write 1 to clear AHB_DMA_IN_DSCR_EMPTY_CH1_INT. */ #define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_CLR (BIT(4)) #define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_M (AHB_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_V << AHB_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_S) #define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_V 0x00000001U #define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_S 4 /** AHB_DMA_INFIFO_OVF_CH1_INT_CLR : WT; bitpos: [5]; default: 0; - * Write 1 to clear AHB_DMA_INFIFO_OVF_CH1_INT + * Write 1 to clear AHB_DMA_INFIFO_OVF_CH1_INT. */ #define AHB_DMA_INFIFO_OVF_CH1_INT_CLR (BIT(5)) #define AHB_DMA_INFIFO_OVF_CH1_INT_CLR_M (AHB_DMA_INFIFO_OVF_CH1_INT_CLR_V << AHB_DMA_INFIFO_OVF_CH1_INT_CLR_S) #define AHB_DMA_INFIFO_OVF_CH1_INT_CLR_V 0x00000001U #define AHB_DMA_INFIFO_OVF_CH1_INT_CLR_S 5 /** AHB_DMA_INFIFO_UDF_CH1_INT_CLR : WT; bitpos: [6]; default: 0; - * Write 1 to clear AHB_DMA_INFIFO_UDF_CH1_INT + * Write 1 to clear AHB_DMA_INFIFO_UDF_CH1_INT. */ #define AHB_DMA_INFIFO_UDF_CH1_INT_CLR (BIT(6)) #define AHB_DMA_INFIFO_UDF_CH1_INT_CLR_M (AHB_DMA_INFIFO_UDF_CH1_INT_CLR_V << AHB_DMA_INFIFO_UDF_CH1_INT_CLR_S) #define AHB_DMA_INFIFO_UDF_CH1_INT_CLR_V 0x00000001U #define AHB_DMA_INFIFO_UDF_CH1_INT_CLR_S 6 /** AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_CLR : WT; bitpos: [7]; default: 0; - * Write 1 to clear AHB_DMA_IN_RESP_ERR_CH1_INT + * Write 1 to clear AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT. */ #define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_CLR (BIT(7)) #define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_CLR_M (AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_CLR_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_CLR_S) @@ -500,53 +500,53 @@ extern "C" { #define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_CLR_S 7 /** AHB_DMA_OUT_INT_RAW_CH0_REG register - * //Raw interrupt status of TX channel 0 + * TX channel 0 raw interrupt status register */ #define AHB_DMA_OUT_INT_RAW_CH0_REG (DR_REG_AHB_DMA_BASE + 0x30) /** AHB_DMA_OUT_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_DONE_CH0_INT + * The raw interrupt status of AHB_DMA_OUT_DONE_CH0_INT. */ #define AHB_DMA_OUT_DONE_CH0_INT_RAW (BIT(0)) #define AHB_DMA_OUT_DONE_CH0_INT_RAW_M (AHB_DMA_OUT_DONE_CH0_INT_RAW_V << AHB_DMA_OUT_DONE_CH0_INT_RAW_S) #define AHB_DMA_OUT_DONE_CH0_INT_RAW_V 0x00000001U #define AHB_DMA_OUT_DONE_CH0_INT_RAW_S 0 /** AHB_DMA_OUT_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_EOF_CH0_INT + * The raw interrupt status of AHB_DMA_OUT_EOF_CH0_INT. */ #define AHB_DMA_OUT_EOF_CH0_INT_RAW (BIT(1)) #define AHB_DMA_OUT_EOF_CH0_INT_RAW_M (AHB_DMA_OUT_EOF_CH0_INT_RAW_V << AHB_DMA_OUT_EOF_CH0_INT_RAW_S) #define AHB_DMA_OUT_EOF_CH0_INT_RAW_V 0x00000001U #define AHB_DMA_OUT_EOF_CH0_INT_RAW_S 1 /** AHB_DMA_OUT_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_DSCR_ERR_CH0_INT + * The raw interrupt status of AHB_DMA_OUT_DSCR_ERR_CH0_INT. */ #define AHB_DMA_OUT_DSCR_ERR_CH0_INT_RAW (BIT(2)) #define AHB_DMA_OUT_DSCR_ERR_CH0_INT_RAW_M (AHB_DMA_OUT_DSCR_ERR_CH0_INT_RAW_V << AHB_DMA_OUT_DSCR_ERR_CH0_INT_RAW_S) #define AHB_DMA_OUT_DSCR_ERR_CH0_INT_RAW_V 0x00000001U #define AHB_DMA_OUT_DSCR_ERR_CH0_INT_RAW_S 2 /** AHB_DMA_OUT_TOTAL_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH0_INT + * The raw interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH0_INT. */ #define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_RAW (BIT(3)) #define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_M (AHB_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_V << AHB_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_S) #define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_V 0x00000001U #define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_S 3 /** AHB_DMA_OUTFIFO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt status of AHB_DMA_OUTFIFO_OVF_CH0_INT + * The raw interrupt status of AHB_DMA_OUTFIFO_OVF_CH0_INT. */ #define AHB_DMA_OUTFIFO_OVF_CH0_INT_RAW (BIT(4)) #define AHB_DMA_OUTFIFO_OVF_CH0_INT_RAW_M (AHB_DMA_OUTFIFO_OVF_CH0_INT_RAW_V << AHB_DMA_OUTFIFO_OVF_CH0_INT_RAW_S) #define AHB_DMA_OUTFIFO_OVF_CH0_INT_RAW_V 0x00000001U #define AHB_DMA_OUTFIFO_OVF_CH0_INT_RAW_S 4 /** AHB_DMA_OUTFIFO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt status of AHB_DMA_OUTFIFO_UDF_CH0_INT + * The raw interrupt status of AHB_DMA_OUTFIFO_UDF_CH0_INT. */ #define AHB_DMA_OUTFIFO_UDF_CH0_INT_RAW (BIT(5)) #define AHB_DMA_OUTFIFO_UDF_CH0_INT_RAW_M (AHB_DMA_OUTFIFO_UDF_CH0_INT_RAW_V << AHB_DMA_OUTFIFO_UDF_CH0_INT_RAW_S) #define AHB_DMA_OUTFIFO_UDF_CH0_INT_RAW_V 0x00000001U #define AHB_DMA_OUTFIFO_UDF_CH0_INT_RAW_S 5 /** AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_RESP_ERR_CH0_INT + * The raw interrupt status of AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT. */ #define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_RAW (BIT(6)) #define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_RAW_M (AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_RAW_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_RAW_S) @@ -554,53 +554,53 @@ extern "C" { #define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_RAW_S 6 /** AHB_DMA_OUT_INT_ST_CH0_REG register - * Masked interrupt status of TX channel 0 + * TX channel 0 masked interrupt status register */ #define AHB_DMA_OUT_INT_ST_CH0_REG (DR_REG_AHB_DMA_BASE + 0x34) /** AHB_DMA_OUT_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_DONE_CH0_INT + * The masked interrupt status of AHB_DMA_OUT_DONE_CH0_INT. */ #define AHB_DMA_OUT_DONE_CH0_INT_ST (BIT(0)) #define AHB_DMA_OUT_DONE_CH0_INT_ST_M (AHB_DMA_OUT_DONE_CH0_INT_ST_V << AHB_DMA_OUT_DONE_CH0_INT_ST_S) #define AHB_DMA_OUT_DONE_CH0_INT_ST_V 0x00000001U #define AHB_DMA_OUT_DONE_CH0_INT_ST_S 0 /** AHB_DMA_OUT_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_EOF_CH0_INT + * The masked interrupt status of AHB_DMA_OUT_EOF_CH0_INT. */ #define AHB_DMA_OUT_EOF_CH0_INT_ST (BIT(1)) #define AHB_DMA_OUT_EOF_CH0_INT_ST_M (AHB_DMA_OUT_EOF_CH0_INT_ST_V << AHB_DMA_OUT_EOF_CH0_INT_ST_S) #define AHB_DMA_OUT_EOF_CH0_INT_ST_V 0x00000001U #define AHB_DMA_OUT_EOF_CH0_INT_ST_S 1 /** AHB_DMA_OUT_DSCR_ERR_CH0_INT_ST : RO; bitpos: [2]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_DSCR_ERR_CH0_INT + * The masked interrupt status of AHB_DMA_OUT_DSCR_ERR_CH0_INT. */ #define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ST (BIT(2)) #define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ST_M (AHB_DMA_OUT_DSCR_ERR_CH0_INT_ST_V << AHB_DMA_OUT_DSCR_ERR_CH0_INT_ST_S) #define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ST_V 0x00000001U #define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ST_S 2 /** AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ST : RO; bitpos: [3]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH0_INT + * The masked interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH0_INT. */ #define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ST (BIT(3)) #define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ST_M (AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ST_V << AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ST_S) #define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ST_V 0x00000001U #define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ST_S 3 /** AHB_DMA_OUTFIFO_OVF_CH0_INT_ST : RO; bitpos: [4]; default: 0; - * The masked interrupt status of AHB_DMA_OUTFIFO_OVF_CH0_INT + * The masked interrupt status of AHB_DMA_OUTFIFO_OVF_CH0_INT. */ #define AHB_DMA_OUTFIFO_OVF_CH0_INT_ST (BIT(4)) #define AHB_DMA_OUTFIFO_OVF_CH0_INT_ST_M (AHB_DMA_OUTFIFO_OVF_CH0_INT_ST_V << AHB_DMA_OUTFIFO_OVF_CH0_INT_ST_S) #define AHB_DMA_OUTFIFO_OVF_CH0_INT_ST_V 0x00000001U #define AHB_DMA_OUTFIFO_OVF_CH0_INT_ST_S 4 /** AHB_DMA_OUTFIFO_UDF_CH0_INT_ST : RO; bitpos: [5]; default: 0; - * The masked interrupt status of AHB_DMA_OUTFIFO_UDF_CH0_INT + * The masked interrupt status of AHB_DMA_OUTFIFO_UDF_CH0_INT. */ #define AHB_DMA_OUTFIFO_UDF_CH0_INT_ST (BIT(5)) #define AHB_DMA_OUTFIFO_UDF_CH0_INT_ST_M (AHB_DMA_OUTFIFO_UDF_CH0_INT_ST_V << AHB_DMA_OUTFIFO_UDF_CH0_INT_ST_S) #define AHB_DMA_OUTFIFO_UDF_CH0_INT_ST_V 0x00000001U #define AHB_DMA_OUTFIFO_UDF_CH0_INT_ST_S 5 /** AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ST : RO; bitpos: [6]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_RESP_ERR_CH0_INT + * The masked interrupt status of AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT. */ #define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ST (BIT(6)) #define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ST_M (AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ST_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ST_S) @@ -608,53 +608,53 @@ extern "C" { #define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ST_S 6 /** AHB_DMA_OUT_INT_ENA_CH0_REG register - * Interrupt enable bits of TX channel 0 + * TX channel 0 interrupt enable register */ #define AHB_DMA_OUT_INT_ENA_CH0_REG (DR_REG_AHB_DMA_BASE + 0x38) /** AHB_DMA_OUT_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0; - * Write 1 to enable AHB_DMA_OUT_DONE_CH0_INT + * Write 1 to enable AHB_DMA_OUT_DONE_CH0_INT. */ #define AHB_DMA_OUT_DONE_CH0_INT_ENA (BIT(0)) #define AHB_DMA_OUT_DONE_CH0_INT_ENA_M (AHB_DMA_OUT_DONE_CH0_INT_ENA_V << AHB_DMA_OUT_DONE_CH0_INT_ENA_S) #define AHB_DMA_OUT_DONE_CH0_INT_ENA_V 0x00000001U #define AHB_DMA_OUT_DONE_CH0_INT_ENA_S 0 /** AHB_DMA_OUT_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0; - * Write 1 to enable AHB_DMA_OUT_EOF_CH0_INT + * Write 1 to enable AHB_DMA_OUT_EOF_CH0_INT. */ #define AHB_DMA_OUT_EOF_CH0_INT_ENA (BIT(1)) #define AHB_DMA_OUT_EOF_CH0_INT_ENA_M (AHB_DMA_OUT_EOF_CH0_INT_ENA_V << AHB_DMA_OUT_EOF_CH0_INT_ENA_S) #define AHB_DMA_OUT_EOF_CH0_INT_ENA_V 0x00000001U #define AHB_DMA_OUT_EOF_CH0_INT_ENA_S 1 /** AHB_DMA_OUT_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [2]; default: 0; - * Write 1 to enable AHB_DMA_OUT_DSCR_ERR_CH0_INT + * Write 1 to enable AHB_DMA_OUT_DSCR_ERR_CH0_INT. */ #define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ENA (BIT(2)) #define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ENA_M (AHB_DMA_OUT_DSCR_ERR_CH0_INT_ENA_V << AHB_DMA_OUT_DSCR_ERR_CH0_INT_ENA_S) #define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ENA_V 0x00000001U #define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ENA_S 2 /** AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ENA : R/W; bitpos: [3]; default: 0; - * Write 1 to enable AHB_DMA_OUT_TOTAL_EOF_CH0_INT + * Write 1 to enable AHB_DMA_OUT_TOTAL_EOF_CH0_INT. */ #define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ENA (BIT(3)) #define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_M (AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_V << AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_S) #define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_V 0x00000001U #define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_S 3 /** AHB_DMA_OUTFIFO_OVF_CH0_INT_ENA : R/W; bitpos: [4]; default: 0; - * Write 1 to enable AHB_DMA_OUTFIFO_OVF_CH0_INT + * Write 1 to enable AHB_DMA_OUTFIFO_OVF_CH0_INT. */ #define AHB_DMA_OUTFIFO_OVF_CH0_INT_ENA (BIT(4)) #define AHB_DMA_OUTFIFO_OVF_CH0_INT_ENA_M (AHB_DMA_OUTFIFO_OVF_CH0_INT_ENA_V << AHB_DMA_OUTFIFO_OVF_CH0_INT_ENA_S) #define AHB_DMA_OUTFIFO_OVF_CH0_INT_ENA_V 0x00000001U #define AHB_DMA_OUTFIFO_OVF_CH0_INT_ENA_S 4 /** AHB_DMA_OUTFIFO_UDF_CH0_INT_ENA : R/W; bitpos: [5]; default: 0; - * Write 1 to enable AHB_DMA_OUTFIFO_UDF_CH0_INT + * Write 1 to enable AHB_DMA_OUTFIFO_UDF_CH0_INT. */ #define AHB_DMA_OUTFIFO_UDF_CH0_INT_ENA (BIT(5)) #define AHB_DMA_OUTFIFO_UDF_CH0_INT_ENA_M (AHB_DMA_OUTFIFO_UDF_CH0_INT_ENA_V << AHB_DMA_OUTFIFO_UDF_CH0_INT_ENA_S) #define AHB_DMA_OUTFIFO_UDF_CH0_INT_ENA_V 0x00000001U #define AHB_DMA_OUTFIFO_UDF_CH0_INT_ENA_S 5 /** AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ENA : R/W; bitpos: [6]; default: 0; - * Write 1 to enable AHB_DMA_OUT_RESP_ERR_CH0_INT + * Write 1 to enable AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT. */ #define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ENA (BIT(6)) #define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ENA_M (AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ENA_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ENA_S) @@ -662,53 +662,53 @@ extern "C" { #define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ENA_S 6 /** AHB_DMA_OUT_INT_CLR_CH0_REG register - * Interrupt clear bits of TX channel 0 + * TX channel 0 interrupt clear register */ #define AHB_DMA_OUT_INT_CLR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x3c) /** AHB_DMA_OUT_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0; - * Write 1 to clear AHB_DMA_OUT_DONE_CH0_INT + * Write 1 to clear AHB_DMA_OUT_DONE_CH0_INT. */ #define AHB_DMA_OUT_DONE_CH0_INT_CLR (BIT(0)) #define AHB_DMA_OUT_DONE_CH0_INT_CLR_M (AHB_DMA_OUT_DONE_CH0_INT_CLR_V << AHB_DMA_OUT_DONE_CH0_INT_CLR_S) #define AHB_DMA_OUT_DONE_CH0_INT_CLR_V 0x00000001U #define AHB_DMA_OUT_DONE_CH0_INT_CLR_S 0 /** AHB_DMA_OUT_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0; - * Write 1 to clear AHB_DMA_OUT_EOF_CH0_INT + * Write 1 to clear AHB_DMA_OUT_EOF_CH0_INT. */ #define AHB_DMA_OUT_EOF_CH0_INT_CLR (BIT(1)) #define AHB_DMA_OUT_EOF_CH0_INT_CLR_M (AHB_DMA_OUT_EOF_CH0_INT_CLR_V << AHB_DMA_OUT_EOF_CH0_INT_CLR_S) #define AHB_DMA_OUT_EOF_CH0_INT_CLR_V 0x00000001U #define AHB_DMA_OUT_EOF_CH0_INT_CLR_S 1 /** AHB_DMA_OUT_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [2]; default: 0; - * Write 1 to clear AHB_DMA_OUT_DSCR_ERR_CH0_INT + * Write 1 to clear AHB_DMA_OUT_DSCR_ERR_CH0_INT. */ #define AHB_DMA_OUT_DSCR_ERR_CH0_INT_CLR (BIT(2)) #define AHB_DMA_OUT_DSCR_ERR_CH0_INT_CLR_M (AHB_DMA_OUT_DSCR_ERR_CH0_INT_CLR_V << AHB_DMA_OUT_DSCR_ERR_CH0_INT_CLR_S) #define AHB_DMA_OUT_DSCR_ERR_CH0_INT_CLR_V 0x00000001U #define AHB_DMA_OUT_DSCR_ERR_CH0_INT_CLR_S 2 /** AHB_DMA_OUT_TOTAL_EOF_CH0_INT_CLR : WT; bitpos: [3]; default: 0; - * Write 1 to clear AHB_DMA_OUT_TOTAL_EOF_CH0_INT + * Write 1 to clear AHB_DMA_OUT_TOTAL_EOF_CH0_INT. */ #define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_CLR (BIT(3)) #define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_M (AHB_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_V << AHB_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_S) #define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_V 0x00000001U #define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_S 3 /** AHB_DMA_OUTFIFO_OVF_CH0_INT_CLR : WT; bitpos: [4]; default: 0; - * Write 1 to clear AHB_DMA_OUTFIFO_OVF_CH0_INT + * Write 1 to clear AHB_DMA_OUTFIFO_OVF_CH0_INT. */ #define AHB_DMA_OUTFIFO_OVF_CH0_INT_CLR (BIT(4)) #define AHB_DMA_OUTFIFO_OVF_CH0_INT_CLR_M (AHB_DMA_OUTFIFO_OVF_CH0_INT_CLR_V << AHB_DMA_OUTFIFO_OVF_CH0_INT_CLR_S) #define AHB_DMA_OUTFIFO_OVF_CH0_INT_CLR_V 0x00000001U #define AHB_DMA_OUTFIFO_OVF_CH0_INT_CLR_S 4 /** AHB_DMA_OUTFIFO_UDF_CH0_INT_CLR : WT; bitpos: [5]; default: 0; - * Write 1 to clear AHB_DMA_OUTFIFO_UDF_CH0_INT + * Write 1 to clear AHB_DMA_OUTFIFO_UDF_CH0_INT. */ #define AHB_DMA_OUTFIFO_UDF_CH0_INT_CLR (BIT(5)) #define AHB_DMA_OUTFIFO_UDF_CH0_INT_CLR_M (AHB_DMA_OUTFIFO_UDF_CH0_INT_CLR_V << AHB_DMA_OUTFIFO_UDF_CH0_INT_CLR_S) #define AHB_DMA_OUTFIFO_UDF_CH0_INT_CLR_V 0x00000001U #define AHB_DMA_OUTFIFO_UDF_CH0_INT_CLR_S 5 /** AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_CLR : WT; bitpos: [6]; default: 0; - * Write 1 to clear AHB_DMA_OUT_RESP_ERR_CH0_INT + * Write 1 to clear AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT. */ #define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_CLR (BIT(6)) #define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_CLR_M (AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_CLR_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_CLR_S) @@ -716,53 +716,53 @@ extern "C" { #define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_CLR_S 6 /** AHB_DMA_OUT_INT_RAW_CH1_REG register - * //Raw interrupt status of TX channel 1 + * TX channel 1 raw interrupt status register */ #define AHB_DMA_OUT_INT_RAW_CH1_REG (DR_REG_AHB_DMA_BASE + 0x40) /** AHB_DMA_OUT_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_DONE_CH1_INT + * The raw interrupt status of AHB_DMA_OUT_DONE_CH1_INT. */ #define AHB_DMA_OUT_DONE_CH1_INT_RAW (BIT(0)) #define AHB_DMA_OUT_DONE_CH1_INT_RAW_M (AHB_DMA_OUT_DONE_CH1_INT_RAW_V << AHB_DMA_OUT_DONE_CH1_INT_RAW_S) #define AHB_DMA_OUT_DONE_CH1_INT_RAW_V 0x00000001U #define AHB_DMA_OUT_DONE_CH1_INT_RAW_S 0 /** AHB_DMA_OUT_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_EOF_CH1_INT + * The raw interrupt status of AHB_DMA_OUT_EOF_CH1_INT. */ #define AHB_DMA_OUT_EOF_CH1_INT_RAW (BIT(1)) #define AHB_DMA_OUT_EOF_CH1_INT_RAW_M (AHB_DMA_OUT_EOF_CH1_INT_RAW_V << AHB_DMA_OUT_EOF_CH1_INT_RAW_S) #define AHB_DMA_OUT_EOF_CH1_INT_RAW_V 0x00000001U #define AHB_DMA_OUT_EOF_CH1_INT_RAW_S 1 /** AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_DSCR_ERR_CH1_INT + * The raw interrupt status of AHB_DMA_OUT_DSCR_ERR_CH1_INT. */ #define AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW (BIT(2)) #define AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW_M (AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW_V << AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW_S) #define AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW_V 0x00000001U #define AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW_S 2 /** AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH1_INT + * The raw interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH1_INT. */ #define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW (BIT(3)) #define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_M (AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_V << AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_S) #define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_V 0x00000001U #define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_S 3 /** AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt status of AHB_DMA_OUTFIFO_OVF_CH1_INT + * The raw interrupt status of AHB_DMA_OUTFIFO_OVF_CH1_INT. */ #define AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW (BIT(4)) #define AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW_M (AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW_V << AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW_S) #define AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW_V 0x00000001U #define AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW_S 4 /** AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt status of AHB_DMA_OUTFIFO_UDF_CH1_INT + * The raw interrupt status of AHB_DMA_OUTFIFO_UDF_CH1_INT. */ #define AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW (BIT(5)) #define AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW_M (AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW_V << AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW_S) #define AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW_V 0x00000001U #define AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW_S 5 /** AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_RESP_ERR_CH1_INT + * The raw interrupt status of AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT. */ #define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_RAW (BIT(6)) #define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_RAW_M (AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_RAW_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_RAW_S) @@ -770,53 +770,53 @@ extern "C" { #define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_RAW_S 6 /** AHB_DMA_OUT_INT_ST_CH1_REG register - * Masked interrupt status of TX channel 1 + * TX channel 1 masked interrupt status register */ #define AHB_DMA_OUT_INT_ST_CH1_REG (DR_REG_AHB_DMA_BASE + 0x44) /** AHB_DMA_OUT_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_DONE_CH1_INT + * The masked interrupt status of AHB_DMA_OUT_DONE_CH1_INT. */ #define AHB_DMA_OUT_DONE_CH1_INT_ST (BIT(0)) #define AHB_DMA_OUT_DONE_CH1_INT_ST_M (AHB_DMA_OUT_DONE_CH1_INT_ST_V << AHB_DMA_OUT_DONE_CH1_INT_ST_S) #define AHB_DMA_OUT_DONE_CH1_INT_ST_V 0x00000001U #define AHB_DMA_OUT_DONE_CH1_INT_ST_S 0 /** AHB_DMA_OUT_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_EOF_CH1_INT + * The masked interrupt status of AHB_DMA_OUT_EOF_CH1_INT. */ #define AHB_DMA_OUT_EOF_CH1_INT_ST (BIT(1)) #define AHB_DMA_OUT_EOF_CH1_INT_ST_M (AHB_DMA_OUT_EOF_CH1_INT_ST_V << AHB_DMA_OUT_EOF_CH1_INT_ST_S) #define AHB_DMA_OUT_EOF_CH1_INT_ST_V 0x00000001U #define AHB_DMA_OUT_EOF_CH1_INT_ST_S 1 /** AHB_DMA_OUT_DSCR_ERR_CH1_INT_ST : RO; bitpos: [2]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_DSCR_ERR_CH1_INT + * The masked interrupt status of AHB_DMA_OUT_DSCR_ERR_CH1_INT. */ #define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ST (BIT(2)) #define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ST_M (AHB_DMA_OUT_DSCR_ERR_CH1_INT_ST_V << AHB_DMA_OUT_DSCR_ERR_CH1_INT_ST_S) #define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ST_V 0x00000001U #define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ST_S 2 /** AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ST : RO; bitpos: [3]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH1_INT + * The masked interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH1_INT. */ #define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ST (BIT(3)) #define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ST_M (AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ST_V << AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ST_S) #define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ST_V 0x00000001U #define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ST_S 3 /** AHB_DMA_OUTFIFO_OVF_CH1_INT_ST : RO; bitpos: [4]; default: 0; - * The masked interrupt status of AHB_DMA_OUTFIFO_OVF_CH1_INT + * The masked interrupt status of AHB_DMA_OUTFIFO_OVF_CH1_INT. */ #define AHB_DMA_OUTFIFO_OVF_CH1_INT_ST (BIT(4)) #define AHB_DMA_OUTFIFO_OVF_CH1_INT_ST_M (AHB_DMA_OUTFIFO_OVF_CH1_INT_ST_V << AHB_DMA_OUTFIFO_OVF_CH1_INT_ST_S) #define AHB_DMA_OUTFIFO_OVF_CH1_INT_ST_V 0x00000001U #define AHB_DMA_OUTFIFO_OVF_CH1_INT_ST_S 4 /** AHB_DMA_OUTFIFO_UDF_CH1_INT_ST : RO; bitpos: [5]; default: 0; - * The masked interrupt status of AHB_DMA_OUTFIFO_UDF_CH1_INT + * The masked interrupt status of AHB_DMA_OUTFIFO_UDF_CH1_INT. */ #define AHB_DMA_OUTFIFO_UDF_CH1_INT_ST (BIT(5)) #define AHB_DMA_OUTFIFO_UDF_CH1_INT_ST_M (AHB_DMA_OUTFIFO_UDF_CH1_INT_ST_V << AHB_DMA_OUTFIFO_UDF_CH1_INT_ST_S) #define AHB_DMA_OUTFIFO_UDF_CH1_INT_ST_V 0x00000001U #define AHB_DMA_OUTFIFO_UDF_CH1_INT_ST_S 5 /** AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ST : RO; bitpos: [6]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_RESP_ERR_CH1_INT + * The masked interrupt status of AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT. */ #define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ST (BIT(6)) #define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ST_M (AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ST_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ST_S) @@ -824,53 +824,53 @@ extern "C" { #define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ST_S 6 /** AHB_DMA_OUT_INT_ENA_CH1_REG register - * Interrupt enable bits of TX channel 1 + * TX channel 1 interrupt enable register */ #define AHB_DMA_OUT_INT_ENA_CH1_REG (DR_REG_AHB_DMA_BASE + 0x48) /** AHB_DMA_OUT_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0; - * Write 1 to enable AHB_DMA_OUT_DONE_CH1_INT + * Write 1 to enable AHB_DMA_OUT_DONE_CH1_INT. */ #define AHB_DMA_OUT_DONE_CH1_INT_ENA (BIT(0)) #define AHB_DMA_OUT_DONE_CH1_INT_ENA_M (AHB_DMA_OUT_DONE_CH1_INT_ENA_V << AHB_DMA_OUT_DONE_CH1_INT_ENA_S) #define AHB_DMA_OUT_DONE_CH1_INT_ENA_V 0x00000001U #define AHB_DMA_OUT_DONE_CH1_INT_ENA_S 0 /** AHB_DMA_OUT_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0; - * Write 1 to enable AHB_DMA_OUT_EOF_CH1_INT + * Write 1 to enable AHB_DMA_OUT_EOF_CH1_INT. */ #define AHB_DMA_OUT_EOF_CH1_INT_ENA (BIT(1)) #define AHB_DMA_OUT_EOF_CH1_INT_ENA_M (AHB_DMA_OUT_EOF_CH1_INT_ENA_V << AHB_DMA_OUT_EOF_CH1_INT_ENA_S) #define AHB_DMA_OUT_EOF_CH1_INT_ENA_V 0x00000001U #define AHB_DMA_OUT_EOF_CH1_INT_ENA_S 1 /** AHB_DMA_OUT_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [2]; default: 0; - * Write 1 to enable AHB_DMA_OUT_DSCR_ERR_CH1_INT + * Write 1 to enable AHB_DMA_OUT_DSCR_ERR_CH1_INT. */ #define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ENA (BIT(2)) #define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ENA_M (AHB_DMA_OUT_DSCR_ERR_CH1_INT_ENA_V << AHB_DMA_OUT_DSCR_ERR_CH1_INT_ENA_S) #define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ENA_V 0x00000001U #define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ENA_S 2 /** AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ENA : R/W; bitpos: [3]; default: 0; - * Write 1 to enable AHB_DMA_OUT_TOTAL_EOF_CH1_INT + * Write 1 to enable AHB_DMA_OUT_TOTAL_EOF_CH1_INT. */ #define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ENA (BIT(3)) #define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_M (AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_V << AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_S) #define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_V 0x00000001U #define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_S 3 /** AHB_DMA_OUTFIFO_OVF_CH1_INT_ENA : R/W; bitpos: [4]; default: 0; - * Write 1 to enable AHB_DMA_OUTFIFO_OVF_CH1_INT + * Write 1 to enable AHB_DMA_OUTFIFO_OVF_CH1_INT. */ #define AHB_DMA_OUTFIFO_OVF_CH1_INT_ENA (BIT(4)) #define AHB_DMA_OUTFIFO_OVF_CH1_INT_ENA_M (AHB_DMA_OUTFIFO_OVF_CH1_INT_ENA_V << AHB_DMA_OUTFIFO_OVF_CH1_INT_ENA_S) #define AHB_DMA_OUTFIFO_OVF_CH1_INT_ENA_V 0x00000001U #define AHB_DMA_OUTFIFO_OVF_CH1_INT_ENA_S 4 /** AHB_DMA_OUTFIFO_UDF_CH1_INT_ENA : R/W; bitpos: [5]; default: 0; - * Write 1 to enable AHB_DMA_OUTFIFO_UDF_CH1_INT + * Write 1 to enable AHB_DMA_OUTFIFO_UDF_CH1_INT. */ #define AHB_DMA_OUTFIFO_UDF_CH1_INT_ENA (BIT(5)) #define AHB_DMA_OUTFIFO_UDF_CH1_INT_ENA_M (AHB_DMA_OUTFIFO_UDF_CH1_INT_ENA_V << AHB_DMA_OUTFIFO_UDF_CH1_INT_ENA_S) #define AHB_DMA_OUTFIFO_UDF_CH1_INT_ENA_V 0x00000001U #define AHB_DMA_OUTFIFO_UDF_CH1_INT_ENA_S 5 /** AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ENA : R/W; bitpos: [6]; default: 0; - * Write 1 to enable AHB_DMA_OUT_RESP_ERR_CH1_INT + * Write 1 to enable AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT. */ #define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ENA (BIT(6)) #define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ENA_M (AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ENA_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ENA_S) @@ -878,91 +878,72 @@ extern "C" { #define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ENA_S 6 /** AHB_DMA_OUT_INT_CLR_CH1_REG register - * Interrupt clear bits of TX channel 1 + * TX channel 1 interrupt clear register */ #define AHB_DMA_OUT_INT_CLR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x4c) /** AHB_DMA_OUT_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0; - * Write 1 to clear AHB_DMA_OUT_DONE_CH1_INT + * Write 1 to clear AHB_DMA_OUT_DONE_CH1_INT. */ #define AHB_DMA_OUT_DONE_CH1_INT_CLR (BIT(0)) #define AHB_DMA_OUT_DONE_CH1_INT_CLR_M (AHB_DMA_OUT_DONE_CH1_INT_CLR_V << AHB_DMA_OUT_DONE_CH1_INT_CLR_S) #define AHB_DMA_OUT_DONE_CH1_INT_CLR_V 0x00000001U #define AHB_DMA_OUT_DONE_CH1_INT_CLR_S 0 /** AHB_DMA_OUT_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0; - * Write 1 to clear AHB_DMA_OUT_EOF_CH1_INT + * Write 1 to clear AHB_DMA_OUT_EOF_CH1_INT. */ #define AHB_DMA_OUT_EOF_CH1_INT_CLR (BIT(1)) #define AHB_DMA_OUT_EOF_CH1_INT_CLR_M (AHB_DMA_OUT_EOF_CH1_INT_CLR_V << AHB_DMA_OUT_EOF_CH1_INT_CLR_S) #define AHB_DMA_OUT_EOF_CH1_INT_CLR_V 0x00000001U #define AHB_DMA_OUT_EOF_CH1_INT_CLR_S 1 /** AHB_DMA_OUT_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [2]; default: 0; - * Write 1 to clear AHB_DMA_OUT_DSCR_ERR_CH1_INT + * Write 1 to clear AHB_DMA_OUT_DSCR_ERR_CH1_INT. */ #define AHB_DMA_OUT_DSCR_ERR_CH1_INT_CLR (BIT(2)) #define AHB_DMA_OUT_DSCR_ERR_CH1_INT_CLR_M (AHB_DMA_OUT_DSCR_ERR_CH1_INT_CLR_V << AHB_DMA_OUT_DSCR_ERR_CH1_INT_CLR_S) #define AHB_DMA_OUT_DSCR_ERR_CH1_INT_CLR_V 0x00000001U #define AHB_DMA_OUT_DSCR_ERR_CH1_INT_CLR_S 2 /** AHB_DMA_OUT_TOTAL_EOF_CH1_INT_CLR : WT; bitpos: [3]; default: 0; - * Write 1 to clear AHB_DMA_OUT_TOTAL_EOF_CH1_INT + * Write 1 to clear AHB_DMA_OUT_TOTAL_EOF_CH1_INT. */ #define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_CLR (BIT(3)) #define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_M (AHB_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_V << AHB_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_S) #define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_V 0x00000001U #define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_S 3 /** AHB_DMA_OUTFIFO_OVF_CH1_INT_CLR : WT; bitpos: [4]; default: 0; - * Write 1 to clear AHB_DMA_OUTFIFO_OVF_CH1_INT + * Write 1 to clear AHB_DMA_OUTFIFO_OVF_CH1_INT. */ #define AHB_DMA_OUTFIFO_OVF_CH1_INT_CLR (BIT(4)) #define AHB_DMA_OUTFIFO_OVF_CH1_INT_CLR_M (AHB_DMA_OUTFIFO_OVF_CH1_INT_CLR_V << AHB_DMA_OUTFIFO_OVF_CH1_INT_CLR_S) #define AHB_DMA_OUTFIFO_OVF_CH1_INT_CLR_V 0x00000001U #define AHB_DMA_OUTFIFO_OVF_CH1_INT_CLR_S 4 /** AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR : WT; bitpos: [5]; default: 0; - * Write 1 to clear AHB_DMA_OUTFIFO_UDF_CH1_INT + * Write 1 to clear AHB_DMA_OUTFIFO_UDF_CH1_INT. */ #define AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR (BIT(5)) #define AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR_M (AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR_V << AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR_S) #define AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR_V 0x00000001U #define AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR_S 5 /** AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_CLR : WT; bitpos: [6]; default: 0; - * Write 1 to clear AHB_DMA_OUT_RESP_ERR_CH1_INT + * Write 1 to clear AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT. */ #define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_CLR (BIT(6)) #define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_CLR_M (AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_CLR_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_CLR_S) #define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_CLR_V 0x00000001U #define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_CLR_S 6 -/** AHB_DMA_AHB_TEST_REG register - * only for test - */ -#define AHB_DMA_AHB_TEST_REG (DR_REG_AHB_DMA_BASE + 0x60) -/** AHB_DMA_AHB_TESTMODE : R/W; bitpos: [2:0]; default: 0; - * reserved - */ -#define AHB_DMA_AHB_TESTMODE 0x00000007U -#define AHB_DMA_AHB_TESTMODE_M (AHB_DMA_AHB_TESTMODE_V << AHB_DMA_AHB_TESTMODE_S) -#define AHB_DMA_AHB_TESTMODE_V 0x00000007U -#define AHB_DMA_AHB_TESTMODE_S 0 -/** AHB_DMA_AHB_TESTADDR : R/W; bitpos: [5:4]; default: 0; - * reserved - */ -#define AHB_DMA_AHB_TESTADDR 0x00000003U -#define AHB_DMA_AHB_TESTADDR_M (AHB_DMA_AHB_TESTADDR_V << AHB_DMA_AHB_TESTADDR_S) -#define AHB_DMA_AHB_TESTADDR_V 0x00000003U -#define AHB_DMA_AHB_TESTADDR_S 4 - /** AHB_DMA_MISC_CONF_REG register - * reserved + * Miscellaneous register */ #define AHB_DMA_MISC_CONF_REG (DR_REG_AHB_DMA_BASE + 0x64) /** AHB_DMA_AHBM_RST_INTER : R/W; bitpos: [0]; default: 0; - * Write 1 and then 0 to reset the internal AHB FSM + * Write 1 and then 0 to reset the internal AHB FSM. */ #define AHB_DMA_AHBM_RST_INTER (BIT(0)) #define AHB_DMA_AHBM_RST_INTER_M (AHB_DMA_AHBM_RST_INTER_V << AHB_DMA_AHBM_RST_INTER_S) #define AHB_DMA_AHBM_RST_INTER_V 0x00000001U #define AHB_DMA_AHBM_RST_INTER_S 0 /** AHB_DMA_ARB_PRI_DIS : R/W; bitpos: [2]; default: 0; - * Configures whether to disable the fixed-priority channel arbitration. + * Configures whether to disable the priority arbitration. * 0: Enable * 1: Disable */ @@ -971,9 +952,9 @@ extern "C" { #define AHB_DMA_ARB_PRI_DIS_V 0x00000001U #define AHB_DMA_ARB_PRI_DIS_S 2 /** AHB_DMA_CLK_EN : R/W; bitpos: [3]; default: 0; - * Configures clock gating. - * 0: Support clock only when the application writes registers. - * 1: Always force the clock on for registers. + * Configures AHB DMA clock gating. + * 0: Support clock only when the application writes registers + * 1: Always force the clock on for registers */ #define AHB_DMA_CLK_EN (BIT(3)) #define AHB_DMA_CLK_EN_M (AHB_DMA_CLK_EN_V << AHB_DMA_CLK_EN_S) @@ -985,7 +966,7 @@ extern "C" { */ #define AHB_DMA_DATE_REG (DR_REG_AHB_DMA_BASE + 0x68) /** AHB_DMA_DATE : R/W; bitpos: [31:0]; default: 2410220; - * Version control register + * Version control register. */ #define AHB_DMA_DATE 0xFFFFFFFFU #define AHB_DMA_DATE_M (AHB_DMA_DATE_V << AHB_DMA_DATE_S) @@ -997,14 +978,14 @@ extern "C" { */ #define AHB_DMA_IN_CONF0_CH0_REG (DR_REG_AHB_DMA_BASE + 0x70) /** AHB_DMA_IN_RST_CH0 : R/W; bitpos: [0]; default: 0; - * Write 1 and then 0 to reset AHB_DMA channel 0 RX FSM and RX FIFO pointer. + * Write 1 and then 0 to reset RX channel 0 FSM and RX FIFO pointer. */ #define AHB_DMA_IN_RST_CH0 (BIT(0)) #define AHB_DMA_IN_RST_CH0_M (AHB_DMA_IN_RST_CH0_V << AHB_DMA_IN_RST_CH0_S) #define AHB_DMA_IN_RST_CH0_V 0x00000001U #define AHB_DMA_IN_RST_CH0_S 0 /** AHB_DMA_IN_LOOP_TEST_CH0 : R/W; bitpos: [1]; default: 0; - * reserved + * Configures the owner bit value for inlink write-back. */ #define AHB_DMA_IN_LOOP_TEST_CH0 (BIT(1)) #define AHB_DMA_IN_LOOP_TEST_CH0_M (AHB_DMA_IN_LOOP_TEST_CH0_V << AHB_DMA_IN_LOOP_TEST_CH0_S) @@ -1039,11 +1020,11 @@ extern "C" { #define AHB_DMA_IN_ETM_EN_CH0_V 0x00000001U #define AHB_DMA_IN_ETM_EN_CH0_S 5 /** AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0 : R/W; bitpos: [7:6]; default: 0; - * Configures max burst size for Rx channel0. - * 2'b00: single - * 2'b01: incr4 - * 2'b10: incr8 - * 2'b11: incr16 + * Configures maximum burst length for RX channel0. + * 0: SINGLE + * 1: INCR4 + * 2: INCR8 + * 3: Reserved */ #define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0 0x00000003U #define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0_M (AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0_V << AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0_S) @@ -1065,7 +1046,7 @@ extern "C" { #define AHB_DMA_IN_CHECK_OWNER_CH0_S 12 /** AHB_DMA_INFIFO_STATUS_CH0_REG register - * Receive FIFO status of RX channel 0 + * RX channel 0 FIFO status */ #define AHB_DMA_INFIFO_STATUS_CH0_REG (DR_REG_AHB_DMA_BASE + 0x78) /** AHB_DMA_INFIFO_FULL_CH0 : RO; bitpos: [0]; default: 1; @@ -1087,42 +1068,42 @@ extern "C" { #define AHB_DMA_INFIFO_EMPTY_CH0_V 0x00000001U #define AHB_DMA_INFIFO_EMPTY_CH0_S 1 /** AHB_DMA_INFIFO_CNT_CH0 : RO; bitpos: [14:8]; default: 0; - * Represents the number of data bytes in L1 RX FIFO for RX channel 0 + * Represents the number of data bytes in L1 RX FIFO for RX channel 0. */ #define AHB_DMA_INFIFO_CNT_CH0 0x0000007FU #define AHB_DMA_INFIFO_CNT_CH0_M (AHB_DMA_INFIFO_CNT_CH0_V << AHB_DMA_INFIFO_CNT_CH0_S) #define AHB_DMA_INFIFO_CNT_CH0_V 0x0000007FU #define AHB_DMA_INFIFO_CNT_CH0_S 8 /** AHB_DMA_IN_REMAIN_UNDER_1B_CH0 : RO; bitpos: [23]; default: 1; - * reserved + * Reserved. */ #define AHB_DMA_IN_REMAIN_UNDER_1B_CH0 (BIT(23)) #define AHB_DMA_IN_REMAIN_UNDER_1B_CH0_M (AHB_DMA_IN_REMAIN_UNDER_1B_CH0_V << AHB_DMA_IN_REMAIN_UNDER_1B_CH0_S) #define AHB_DMA_IN_REMAIN_UNDER_1B_CH0_V 0x00000001U #define AHB_DMA_IN_REMAIN_UNDER_1B_CH0_S 23 /** AHB_DMA_IN_REMAIN_UNDER_2B_CH0 : RO; bitpos: [24]; default: 1; - * reserved + * Reserved. */ #define AHB_DMA_IN_REMAIN_UNDER_2B_CH0 (BIT(24)) #define AHB_DMA_IN_REMAIN_UNDER_2B_CH0_M (AHB_DMA_IN_REMAIN_UNDER_2B_CH0_V << AHB_DMA_IN_REMAIN_UNDER_2B_CH0_S) #define AHB_DMA_IN_REMAIN_UNDER_2B_CH0_V 0x00000001U #define AHB_DMA_IN_REMAIN_UNDER_2B_CH0_S 24 /** AHB_DMA_IN_REMAIN_UNDER_3B_CH0 : RO; bitpos: [25]; default: 1; - * reserved + * Reserved. */ #define AHB_DMA_IN_REMAIN_UNDER_3B_CH0 (BIT(25)) #define AHB_DMA_IN_REMAIN_UNDER_3B_CH0_M (AHB_DMA_IN_REMAIN_UNDER_3B_CH0_V << AHB_DMA_IN_REMAIN_UNDER_3B_CH0_S) #define AHB_DMA_IN_REMAIN_UNDER_3B_CH0_V 0x00000001U #define AHB_DMA_IN_REMAIN_UNDER_3B_CH0_S 25 /** AHB_DMA_IN_REMAIN_UNDER_4B_CH0 : RO; bitpos: [26]; default: 1; - * reserved + * Reserved. */ #define AHB_DMA_IN_REMAIN_UNDER_4B_CH0 (BIT(26)) #define AHB_DMA_IN_REMAIN_UNDER_4B_CH0_M (AHB_DMA_IN_REMAIN_UNDER_4B_CH0_V << AHB_DMA_IN_REMAIN_UNDER_4B_CH0_S) #define AHB_DMA_IN_REMAIN_UNDER_4B_CH0_V 0x00000001U #define AHB_DMA_IN_REMAIN_UNDER_4B_CH0_S 26 /** AHB_DMA_IN_BUF_HUNGRY_CH0 : RO; bitpos: [27]; default: 0; - * reserved + * Reserved. */ #define AHB_DMA_IN_BUF_HUNGRY_CH0 (BIT(27)) #define AHB_DMA_IN_BUF_HUNGRY_CH0_M (AHB_DMA_IN_BUF_HUNGRY_CH0_V << AHB_DMA_IN_BUF_HUNGRY_CH0_S) @@ -1130,18 +1111,18 @@ extern "C" { #define AHB_DMA_IN_BUF_HUNGRY_CH0_S 27 /** AHB_DMA_IN_POP_CH0_REG register - * Receive FIFO status of RX channel 0 + * Pop control register of RX channel 0 */ #define AHB_DMA_IN_POP_CH0_REG (DR_REG_AHB_DMA_BASE + 0x7c) /** AHB_DMA_INFIFO_RDATA_CH0 : RO; bitpos: [11:0]; default: 2048; - * Represents the data popped from AHB_DMA FIFO. + * Represents the data popped from AHB DMA RX FIFO. */ #define AHB_DMA_INFIFO_RDATA_CH0 0x00000FFFU #define AHB_DMA_INFIFO_RDATA_CH0_M (AHB_DMA_INFIFO_RDATA_CH0_V << AHB_DMA_INFIFO_RDATA_CH0_S) #define AHB_DMA_INFIFO_RDATA_CH0_V 0x00000FFFU #define AHB_DMA_INFIFO_RDATA_CH0_S 0 /** AHB_DMA_INFIFO_POP_CH0 : WT; bitpos: [12]; default: 0; - * Configures whether to pop data from AHB_DMA FIFO. + * Configures whether to pop data from AHB DMA RX FIFO. * 0: Invalid. No effect * 1: Pop */ @@ -1151,22 +1132,21 @@ extern "C" { #define AHB_DMA_INFIFO_POP_CH0_S 12 /** AHB_DMA_IN_LINK_CH0_REG register - * Receive FIFO status of RX channel 0 + * Linked list descriptor configuration and control register of RX channel 0 */ #define AHB_DMA_IN_LINK_CH0_REG (DR_REG_AHB_DMA_BASE + 0x80) /** AHB_DMA_INLINK_AUTO_RET_CH0 : R/W; bitpos: [0]; default: 1; - * Configures whether to return to current receive descriptor's address when there are - * some errors in current receiving data. + * Configures whether to return to the current receive descriptor's address when there + * are some errors in current receiving data. * 0: Not return * 1: Return - * . */ #define AHB_DMA_INLINK_AUTO_RET_CH0 (BIT(0)) #define AHB_DMA_INLINK_AUTO_RET_CH0_M (AHB_DMA_INLINK_AUTO_RET_CH0_V << AHB_DMA_INLINK_AUTO_RET_CH0_S) #define AHB_DMA_INLINK_AUTO_RET_CH0_V 0x00000001U #define AHB_DMA_INLINK_AUTO_RET_CH0_S 0 /** AHB_DMA_INLINK_STOP_CH0 : WT; bitpos: [1]; default: 0; - * Configures whether to stop AHB_DMA's RX channel 0 from receiving data. + * Configures whether to stop RX channel 0 from receiving data. * 0: Invalid. No effect * 1: Stop */ @@ -1175,7 +1155,7 @@ extern "C" { #define AHB_DMA_INLINK_STOP_CH0_V 0x00000001U #define AHB_DMA_INLINK_STOP_CH0_S 1 /** AHB_DMA_INLINK_START_CH0 : WT; bitpos: [2]; default: 0; - * Configures whether to enable AHB_DMA's RX channel 0 for data transfer. + * Configures whether to enable RX channel 0 for data transfer. * 0: Disable * 1: Enable */ @@ -1184,7 +1164,7 @@ extern "C" { #define AHB_DMA_INLINK_START_CH0_V 0x00000001U #define AHB_DMA_INLINK_START_CH0_S 2 /** AHB_DMA_INLINK_RESTART_CH0 : WT; bitpos: [3]; default: 0; - * Configures whether to restart RX channel 0 for AHB_DMA transfer. + * Configures whether to restart RX channel 0 for AHB DMA transfer. * 0: Invalid. No effect * 1: Restart */ @@ -1203,26 +1183,28 @@ extern "C" { #define AHB_DMA_INLINK_PARK_CH0_S 4 /** AHB_DMA_IN_STATE_CH0_REG register - * Receive status of RX channel 0 + * RX channel 0 status */ #define AHB_DMA_IN_STATE_CH0_REG (DR_REG_AHB_DMA_BASE + 0x84) /** AHB_DMA_INLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0; - * reserved + * Represents the lower 18 bits of the next receive descriptor address that is + * pre-read (but not processed yet). If the current receive descriptor is the last + * descriptor, then this field represents the address of the current receive + * descriptor. */ #define AHB_DMA_INLINK_DSCR_ADDR_CH0 0x0003FFFFU #define AHB_DMA_INLINK_DSCR_ADDR_CH0_M (AHB_DMA_INLINK_DSCR_ADDR_CH0_V << AHB_DMA_INLINK_DSCR_ADDR_CH0_S) #define AHB_DMA_INLINK_DSCR_ADDR_CH0_V 0x0003FFFFU #define AHB_DMA_INLINK_DSCR_ADDR_CH0_S 0 /** AHB_DMA_IN_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0; - * reserved + * Reserved. */ #define AHB_DMA_IN_DSCR_STATE_CH0 0x00000003U #define AHB_DMA_IN_DSCR_STATE_CH0_M (AHB_DMA_IN_DSCR_STATE_CH0_V << AHB_DMA_IN_DSCR_STATE_CH0_S) #define AHB_DMA_IN_DSCR_STATE_CH0_V 0x00000003U #define AHB_DMA_IN_DSCR_STATE_CH0_S 18 /** AHB_DMA_IN_STATE_CH0 : RO; bitpos: [22:20]; default: 0; - * Represents the address of the lower 18 bits of the next receive descriptor to be - * processed. + * Reserved. */ #define AHB_DMA_IN_STATE_CH0 0x00000007U #define AHB_DMA_IN_STATE_CH0_M (AHB_DMA_IN_STATE_CH0_V << AHB_DMA_IN_STATE_CH0_S) @@ -1243,12 +1225,11 @@ extern "C" { #define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH0_S 0 /** AHB_DMA_IN_ERR_EOF_DES_ADDR_CH0_REG register - * Receive descriptor address when errors occur of RX channel 0 + * Reserved */ #define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x8c) /** AHB_DMA_IN_ERR_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the receive descriptor when there are some errors in the - * currently received data. + * Reserved. */ #define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH0 0xFFFFFFFFU #define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH0_M (AHB_DMA_IN_ERR_EOF_DES_ADDR_CH0_V << AHB_DMA_IN_ERR_EOF_DES_ADDR_CH0_S) @@ -1256,12 +1237,13 @@ extern "C" { #define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH0_S 0 /** AHB_DMA_IN_DSCR_CH0_REG register - * Current receive descriptor address of RX channel 0 + * Address of the next receive descriptor pointed by the current pre-read receive + * descriptor on RX channel 0 */ #define AHB_DMA_IN_DSCR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x90) /** AHB_DMA_INLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0; * Represents the address of the next receive descriptor x+1 pointed by the current - * receive descriptor that has already been fetched. + * receive descriptor that is pre-read. */ #define AHB_DMA_INLINK_DSCR_CH0 0xFFFFFFFFU #define AHB_DMA_INLINK_DSCR_CH0_M (AHB_DMA_INLINK_DSCR_CH0_V << AHB_DMA_INLINK_DSCR_CH0_S) @@ -1269,12 +1251,11 @@ extern "C" { #define AHB_DMA_INLINK_DSCR_CH0_S 0 /** AHB_DMA_IN_DSCR_BF0_CH0_REG register - * The last receive descriptor address of RX channel 0 + * Address of the current pre-read receive descriptor on RX channel 0 */ #define AHB_DMA_IN_DSCR_BF0_CH0_REG (DR_REG_AHB_DMA_BASE + 0x94) /** AHB_DMA_INLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the current receive descriptor x that has already been - * fetched. + * Represents the address of the current receive descriptor x that is pre-read. */ #define AHB_DMA_INLINK_DSCR_BF0_CH0 0xFFFFFFFFU #define AHB_DMA_INLINK_DSCR_BF0_CH0_M (AHB_DMA_INLINK_DSCR_BF0_CH0_V << AHB_DMA_INLINK_DSCR_BF0_CH0_S) @@ -1282,25 +1263,25 @@ extern "C" { #define AHB_DMA_INLINK_DSCR_BF0_CH0_S 0 /** AHB_DMA_IN_DSCR_BF1_CH0_REG register - * The second-to-last receive descriptor address of RX channel 0 + * Address of the previous pre-read receive descriptor on RX channel 0 */ #define AHB_DMA_IN_DSCR_BF1_CH0_REG (DR_REG_AHB_DMA_BASE + 0x98) /** AHB_DMA_INLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the previous receive descriptor x-1 that has already been - * fetched. + * Represents the address of the previous receive descriptor x-1 that is pre-read. */ #define AHB_DMA_INLINK_DSCR_BF1_CH0 0xFFFFFFFFU #define AHB_DMA_INLINK_DSCR_BF1_CH0_M (AHB_DMA_INLINK_DSCR_BF1_CH0_V << AHB_DMA_INLINK_DSCR_BF1_CH0_S) #define AHB_DMA_INLINK_DSCR_BF1_CH0_V 0xFFFFFFFFU #define AHB_DMA_INLINK_DSCR_BF1_CH0_S 0 -/** AHB_DMA_IN_PERI_CH0_REG register +/** AHB_DMA_IN_PRI_CH0_REG register * Priority register of RX channel 0 */ -#define AHB_DMA_IN_PERI_CH0_REG (DR_REG_AHB_DMA_BASE + 0x9c) +#define AHB_DMA_IN_PRI_CH0_REG (DR_REG_AHB_DMA_BASE + 0x9c) /** AHB_DMA_RX_PRI_CH0 : R/W; bitpos: [3:0]; default: 0; - * Configures the priority of RX channel 0.The larger of the value, the higher of the - * priority.. + * Configures the priority of RX channel 0. The larger the value, the higher the + * priority. + * Value range: 0 ~ 5 */ #define AHB_DMA_RX_PRI_CH0 0x0000000FU #define AHB_DMA_RX_PRI_CH0_M (AHB_DMA_RX_PRI_CH0_V << AHB_DMA_RX_PRI_CH0_S) @@ -1314,13 +1295,14 @@ extern "C" { /** AHB_DMA_PERI_IN_SEL_CH0 : R/W; bitpos: [5:0]; default: 63; * Configures the peripheral connected to RX channel 0. * 0: Dummy - * 1: SPI2 + * 1: GP-SPI * 2: Dummy - * 3: I2S0 + * 3: I2S * 4 ~ 6: Dummy * 7: SHA - * 8: ADC_DAC - * 9~15: Dummy + * 8: ADC + * 9 ~ 15: Dummy + * 16 ~ 63: Invalid */ #define AHB_DMA_PERI_IN_SEL_CH0 0x0000003FU #define AHB_DMA_PERI_IN_SEL_CH0_M (AHB_DMA_PERI_IN_SEL_CH0_V << AHB_DMA_PERI_IN_SEL_CH0_S) @@ -1328,11 +1310,11 @@ extern "C" { #define AHB_DMA_PERI_IN_SEL_CH0_S 0 /** AHB_DMA_IN_DONE_DES_ADDR_CH0_REG register - * RX_done Inlink descriptor address of RX channel 0 + * Address of the completed inlink descriptor on RX channel 0 */ #define AHB_DMA_IN_DONE_DES_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0xb0) /** AHB_DMA_IN_DONE_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the inlink descriptor when this descriptor is completed . + * Represents the address of the inlink descriptor when this descriptor is completed. */ #define AHB_DMA_IN_DONE_DES_ADDR_CH0 0xFFFFFFFFU #define AHB_DMA_IN_DONE_DES_ADDR_CH0_M (AHB_DMA_IN_DONE_DES_ADDR_CH0_V << AHB_DMA_IN_DONE_DES_ADDR_CH0_S) @@ -1344,7 +1326,7 @@ extern "C" { */ #define AHB_DMA_OUT_CONF0_CH0_REG (DR_REG_AHB_DMA_BASE + 0xd0) /** AHB_DMA_OUT_RST_CH0 : R/W; bitpos: [0]; default: 0; - * Configures the reset state of AHB_DMA channel 0 TX FSM and TX FIFO pointer. + * Configures the reset state of TX channel 0 FSM and TX FIFO pointer. * 0: Release reset * 1: Reset */ @@ -1353,7 +1335,7 @@ extern "C" { #define AHB_DMA_OUT_RST_CH0_V 0x00000001U #define AHB_DMA_OUT_RST_CH0_S 0 /** AHB_DMA_OUT_LOOP_TEST_CH0 : R/W; bitpos: [1]; default: 0; - * reserved + * Configures the owner bit value for outlink write-back. */ #define AHB_DMA_OUT_LOOP_TEST_CH0 (BIT(1)) #define AHB_DMA_OUT_LOOP_TEST_CH0_M (AHB_DMA_OUT_LOOP_TEST_CH0_V << AHB_DMA_OUT_LOOP_TEST_CH0_S) @@ -1372,9 +1354,9 @@ extern "C" { /** AHB_DMA_OUT_EOF_MODE_CH0 : R/W; bitpos: [3]; default: 1; * Configures when to generate EOF flag. * 0: EOF flag for TX channel 0 is generated when data to be transmitted has been - * pushed into FIFO in AHB_DMA. + * pushed into FIFO in AHB DMA. * 1: EOF flag for TX channel 0 is generated when data to be transmitted has been - * popped from FIFO in AHB_DMA. + * popped from FIFO in AHB DMA. */ #define AHB_DMA_OUT_EOF_MODE_CH0 (BIT(3)) #define AHB_DMA_OUT_EOF_MODE_CH0_M (AHB_DMA_OUT_EOF_MODE_CH0_V << AHB_DMA_OUT_EOF_MODE_CH0_S) @@ -1400,11 +1382,11 @@ extern "C" { #define AHB_DMA_OUT_ETM_EN_CH0_V 0x00000001U #define AHB_DMA_OUT_ETM_EN_CH0_S 6 /** AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0 : R/W; bitpos: [9:8]; default: 0; - * Configures max burst size for TX channel0. - * 2'b00: single - * 2'b01: incr4 - * 2'b10: incr8 - * 2'b11: incr16 + * Configures maximum burst length for TX channel0. + * 0: SINGLE + * 1: INCR4 + * 2: INCR8 + * 3: Reserved */ #define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0 0x00000003U #define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0_M (AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0_V << AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0_S) @@ -1426,7 +1408,7 @@ extern "C" { #define AHB_DMA_OUT_CHECK_OWNER_CH0_S 12 /** AHB_DMA_OUTFIFO_STATUS_CH0_REG register - * Receive FIFO status of RX channel 0 + * TX channel 0 FIFO status */ #define AHB_DMA_OUTFIFO_STATUS_CH0_REG (DR_REG_AHB_DMA_BASE + 0xd8) /** AHB_DMA_OUTFIFO_FULL_CH0 : RO; bitpos: [0]; default: 0; @@ -1448,35 +1430,35 @@ extern "C" { #define AHB_DMA_OUTFIFO_EMPTY_CH0_V 0x00000001U #define AHB_DMA_OUTFIFO_EMPTY_CH0_S 1 /** AHB_DMA_OUTFIFO_CNT_CH0 : RO; bitpos: [14:8]; default: 0; - * Represents the number of data bytes in L1 TX FIFO for TX channel 0 + * Represents the number of data bytes in L1 TX FIFO for TX channel 0. */ #define AHB_DMA_OUTFIFO_CNT_CH0 0x0000007FU #define AHB_DMA_OUTFIFO_CNT_CH0_M (AHB_DMA_OUTFIFO_CNT_CH0_V << AHB_DMA_OUTFIFO_CNT_CH0_S) #define AHB_DMA_OUTFIFO_CNT_CH0_V 0x0000007FU #define AHB_DMA_OUTFIFO_CNT_CH0_S 8 /** AHB_DMA_OUT_REMAIN_UNDER_1B_CH0 : RO; bitpos: [23]; default: 1; - * reserved + * Reserved. */ #define AHB_DMA_OUT_REMAIN_UNDER_1B_CH0 (BIT(23)) #define AHB_DMA_OUT_REMAIN_UNDER_1B_CH0_M (AHB_DMA_OUT_REMAIN_UNDER_1B_CH0_V << AHB_DMA_OUT_REMAIN_UNDER_1B_CH0_S) #define AHB_DMA_OUT_REMAIN_UNDER_1B_CH0_V 0x00000001U #define AHB_DMA_OUT_REMAIN_UNDER_1B_CH0_S 23 /** AHB_DMA_OUT_REMAIN_UNDER_2B_CH0 : RO; bitpos: [24]; default: 1; - * reserved + * Reserved. */ #define AHB_DMA_OUT_REMAIN_UNDER_2B_CH0 (BIT(24)) #define AHB_DMA_OUT_REMAIN_UNDER_2B_CH0_M (AHB_DMA_OUT_REMAIN_UNDER_2B_CH0_V << AHB_DMA_OUT_REMAIN_UNDER_2B_CH0_S) #define AHB_DMA_OUT_REMAIN_UNDER_2B_CH0_V 0x00000001U #define AHB_DMA_OUT_REMAIN_UNDER_2B_CH0_S 24 /** AHB_DMA_OUT_REMAIN_UNDER_3B_CH0 : RO; bitpos: [25]; default: 1; - * reserved + * Reserved. */ #define AHB_DMA_OUT_REMAIN_UNDER_3B_CH0 (BIT(25)) #define AHB_DMA_OUT_REMAIN_UNDER_3B_CH0_M (AHB_DMA_OUT_REMAIN_UNDER_3B_CH0_V << AHB_DMA_OUT_REMAIN_UNDER_3B_CH0_S) #define AHB_DMA_OUT_REMAIN_UNDER_3B_CH0_V 0x00000001U #define AHB_DMA_OUT_REMAIN_UNDER_3B_CH0_S 25 /** AHB_DMA_OUT_REMAIN_UNDER_4B_CH0 : RO; bitpos: [26]; default: 1; - * reserved + * Reserved. */ #define AHB_DMA_OUT_REMAIN_UNDER_4B_CH0 (BIT(26)) #define AHB_DMA_OUT_REMAIN_UNDER_4B_CH0_M (AHB_DMA_OUT_REMAIN_UNDER_4B_CH0_V << AHB_DMA_OUT_REMAIN_UNDER_4B_CH0_S) @@ -1488,16 +1470,16 @@ extern "C" { */ #define AHB_DMA_OUT_PUSH_CH0_REG (DR_REG_AHB_DMA_BASE + 0xdc) /** AHB_DMA_OUTFIFO_WDATA_CH0 : R/W; bitpos: [8:0]; default: 0; - * Configures whether to push data into AHB_DMA FIFO. - * 0: Invalid. No effect - * 1: Push + * Represents the data that need to be pushed into AHB DMA TX FIFO. */ #define AHB_DMA_OUTFIFO_WDATA_CH0 0x000001FFU #define AHB_DMA_OUTFIFO_WDATA_CH0_M (AHB_DMA_OUTFIFO_WDATA_CH0_V << AHB_DMA_OUTFIFO_WDATA_CH0_S) #define AHB_DMA_OUTFIFO_WDATA_CH0_V 0x000001FFU #define AHB_DMA_OUTFIFO_WDATA_CH0_S 0 /** AHB_DMA_OUTFIFO_PUSH_CH0 : WT; bitpos: [9]; default: 0; - * Configures the data that need to be pushed into AHB_DMA FIFO. + * Configures whether to push data into AHB DMA TX FIFO. + * 0: Invalid. No effect + * 1: Push */ #define AHB_DMA_OUTFIFO_PUSH_CH0 (BIT(9)) #define AHB_DMA_OUTFIFO_PUSH_CH0_M (AHB_DMA_OUTFIFO_PUSH_CH0_V << AHB_DMA_OUTFIFO_PUSH_CH0_S) @@ -1505,11 +1487,11 @@ extern "C" { #define AHB_DMA_OUTFIFO_PUSH_CH0_S 9 /** AHB_DMA_OUT_LINK_CH0_REG register - * Push control register of TX channel 0 + * Linked list descriptor configuration and control register of TX channel 0 */ #define AHB_DMA_OUT_LINK_CH0_REG (DR_REG_AHB_DMA_BASE + 0xe0) /** AHB_DMA_OUTLINK_STOP_CH0 : WT; bitpos: [0]; default: 0; - * Configures whether to stop AHB_DMA's TX channel 0 from transmitting data. + * Configures whether to stop TX channel 0 from transmitting data. * 0: Invalid. No effect * 1: Stop */ @@ -1518,7 +1500,7 @@ extern "C" { #define AHB_DMA_OUTLINK_STOP_CH0_V 0x00000001U #define AHB_DMA_OUTLINK_STOP_CH0_S 0 /** AHB_DMA_OUTLINK_START_CH0 : WT; bitpos: [1]; default: 0; - * Configures whether to enable AHB_DMA's TX channel 0 for data transfer. + * Configures whether to enable TX channel 0 for data transfer. * 0: Disable * 1: Enable */ @@ -1527,7 +1509,7 @@ extern "C" { #define AHB_DMA_OUTLINK_START_CH0_V 0x00000001U #define AHB_DMA_OUTLINK_START_CH0_S 1 /** AHB_DMA_OUTLINK_RESTART_CH0 : WT; bitpos: [2]; default: 0; - * Configures whether to restart TX channel 0 for AHB_DMA transfer. + * Configures whether to restart TX channel 0 for AHB DMA transfer. * 0: Invalid. No effect * 1: Restart */ @@ -1546,26 +1528,28 @@ extern "C" { #define AHB_DMA_OUTLINK_PARK_CH0_S 3 /** AHB_DMA_OUT_STATE_CH0_REG register - * Transmit status of TX channel 0 + * TX channel 0 status */ #define AHB_DMA_OUT_STATE_CH0_REG (DR_REG_AHB_DMA_BASE + 0xe4) /** AHB_DMA_OUTLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0; - * Represents the lower 18 bits of the address of the next transmit descriptor to be - * processed. + * Represents the lower 18 bits of the next transmit descriptor address that is + * pre-read (but not processed yet). If the current transmit descriptor is the last + * descriptor, then this field represents the address of the current transmit + * descriptor. */ #define AHB_DMA_OUTLINK_DSCR_ADDR_CH0 0x0003FFFFU #define AHB_DMA_OUTLINK_DSCR_ADDR_CH0_M (AHB_DMA_OUTLINK_DSCR_ADDR_CH0_V << AHB_DMA_OUTLINK_DSCR_ADDR_CH0_S) #define AHB_DMA_OUTLINK_DSCR_ADDR_CH0_V 0x0003FFFFU #define AHB_DMA_OUTLINK_DSCR_ADDR_CH0_S 0 /** AHB_DMA_OUT_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0; - * reserved + * Reserved. */ #define AHB_DMA_OUT_DSCR_STATE_CH0 0x00000003U #define AHB_DMA_OUT_DSCR_STATE_CH0_M (AHB_DMA_OUT_DSCR_STATE_CH0_V << AHB_DMA_OUT_DSCR_STATE_CH0_S) #define AHB_DMA_OUT_DSCR_STATE_CH0_V 0x00000003U #define AHB_DMA_OUT_DSCR_STATE_CH0_S 18 /** AHB_DMA_OUT_STATE_CH0 : RO; bitpos: [22:20]; default: 0; - * reserved + * Reserved. */ #define AHB_DMA_OUT_STATE_CH0 0x00000007U #define AHB_DMA_OUT_STATE_CH0_M (AHB_DMA_OUT_STATE_CH0_V << AHB_DMA_OUT_STATE_CH0_S) @@ -1599,12 +1583,13 @@ extern "C" { #define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH0_S 0 /** AHB_DMA_OUT_DSCR_CH0_REG register - * Current transmit descriptor address of TX channel 0 + * Address of the next transmit descriptor pointed by the current pre-read transmit + * descriptor on TX channel 0 */ #define AHB_DMA_OUT_DSCR_CH0_REG (DR_REG_AHB_DMA_BASE + 0xf0) /** AHB_DMA_OUTLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0; * Represents the address of the next transmit descriptor y+1 pointed by the current - * transmit descriptor that has already been fetched. + * transmit descriptor that is pre-read. */ #define AHB_DMA_OUTLINK_DSCR_CH0 0xFFFFFFFFU #define AHB_DMA_OUTLINK_DSCR_CH0_M (AHB_DMA_OUTLINK_DSCR_CH0_V << AHB_DMA_OUTLINK_DSCR_CH0_S) @@ -1612,12 +1597,11 @@ extern "C" { #define AHB_DMA_OUTLINK_DSCR_CH0_S 0 /** AHB_DMA_OUT_DSCR_BF0_CH0_REG register - * The last transmit descriptor address of TX channel 0 + * Address of the current pre-read transmit descriptor on TX channel 0 */ #define AHB_DMA_OUT_DSCR_BF0_CH0_REG (DR_REG_AHB_DMA_BASE + 0xf4) /** AHB_DMA_OUTLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the current transmit descriptor y that has already been - * fetched. + * Represents the address of the current transmit descriptor y that is pre-read. */ #define AHB_DMA_OUTLINK_DSCR_BF0_CH0 0xFFFFFFFFU #define AHB_DMA_OUTLINK_DSCR_BF0_CH0_M (AHB_DMA_OUTLINK_DSCR_BF0_CH0_V << AHB_DMA_OUTLINK_DSCR_BF0_CH0_S) @@ -1625,25 +1609,25 @@ extern "C" { #define AHB_DMA_OUTLINK_DSCR_BF0_CH0_S 0 /** AHB_DMA_OUT_DSCR_BF1_CH0_REG register - * The second-to-last transmit descriptor address of TX channel 0 + * Address of the previous pre-read transmit descriptor on TX channel 0 */ #define AHB_DMA_OUT_DSCR_BF1_CH0_REG (DR_REG_AHB_DMA_BASE + 0xf8) /** AHB_DMA_OUTLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the previous transmit descriptor y-1 that has already - * been fetched. + * Represents the address of the previous transmit descriptor y-1 that is pre-read. */ #define AHB_DMA_OUTLINK_DSCR_BF1_CH0 0xFFFFFFFFU #define AHB_DMA_OUTLINK_DSCR_BF1_CH0_M (AHB_DMA_OUTLINK_DSCR_BF1_CH0_V << AHB_DMA_OUTLINK_DSCR_BF1_CH0_S) #define AHB_DMA_OUTLINK_DSCR_BF1_CH0_V 0xFFFFFFFFU #define AHB_DMA_OUTLINK_DSCR_BF1_CH0_S 0 -/** AHB_DMA_OUT_PERI_CH0_REG register +/** AHB_DMA_OUT_PRI_CH0_REG register * Priority register of TX channel 0 */ -#define AHB_DMA_OUT_PERI_CH0_REG (DR_REG_AHB_DMA_BASE + 0xfc) +#define AHB_DMA_OUT_PRI_CH0_REG (DR_REG_AHB_DMA_BASE + 0xfc) /** AHB_DMA_TX_PRI_CH0 : R/W; bitpos: [3:0]; default: 0; - * Configures the priority of TX channel 0.The larger of the value, the higher of the - * priority.. + * Configures the priority of TX channel 0. The larger the value, the higher the + * priority. + * Value range: 0 ~ 5 */ #define AHB_DMA_TX_PRI_CH0 0x0000000FU #define AHB_DMA_TX_PRI_CH0_M (AHB_DMA_TX_PRI_CH0_V << AHB_DMA_TX_PRI_CH0_S) @@ -1657,13 +1641,14 @@ extern "C" { /** AHB_DMA_PERI_OUT_SEL_CH0 : R/W; bitpos: [5:0]; default: 63; * Configures the peripheral connected to TX channel 0. * 0: Dummy - * 1: SPI2 + * 1: GP-SPI * 2: Dummy - * 3: I2S0 + * 3: I2S * 4 ~ 6: Dummy * 7: SHA - * 8: ADC_DAC - * 9~15: Dummy + * 8: ADC + * 9 ~ 15: Dummy + * 16 ~ 63: Invalid */ #define AHB_DMA_PERI_OUT_SEL_CH0 0x0000003FU #define AHB_DMA_PERI_OUT_SEL_CH0_M (AHB_DMA_PERI_OUT_SEL_CH0_V << AHB_DMA_PERI_OUT_SEL_CH0_S) @@ -1671,7 +1656,7 @@ extern "C" { #define AHB_DMA_PERI_OUT_SEL_CH0_S 0 /** AHB_DMA_OUT_DONE_DES_ADDR_CH0_REG register - * TX done outlink descriptor address of TX channel 0 + * Address of the completed outlink descriptor on TX channel 0 */ #define AHB_DMA_OUT_DONE_DES_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x110) /** AHB_DMA_OUT_DONE_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; @@ -1687,14 +1672,14 @@ extern "C" { */ #define AHB_DMA_IN_CONF0_CH1_REG (DR_REG_AHB_DMA_BASE + 0x130) /** AHB_DMA_IN_RST_CH1 : R/W; bitpos: [0]; default: 0; - * Write 1 and then 0 to reset AHB_DMA channel 1 RX FSM and RX FIFO pointer. + * Write 1 and then 0 to reset RX channel 1 FSM and RX FIFO pointer. */ #define AHB_DMA_IN_RST_CH1 (BIT(0)) #define AHB_DMA_IN_RST_CH1_M (AHB_DMA_IN_RST_CH1_V << AHB_DMA_IN_RST_CH1_S) #define AHB_DMA_IN_RST_CH1_V 0x00000001U #define AHB_DMA_IN_RST_CH1_S 0 /** AHB_DMA_IN_LOOP_TEST_CH1 : R/W; bitpos: [1]; default: 0; - * reserved + * Configures the owner bit value for inlink write-back. */ #define AHB_DMA_IN_LOOP_TEST_CH1 (BIT(1)) #define AHB_DMA_IN_LOOP_TEST_CH1_M (AHB_DMA_IN_LOOP_TEST_CH1_V << AHB_DMA_IN_LOOP_TEST_CH1_S) @@ -1729,11 +1714,11 @@ extern "C" { #define AHB_DMA_IN_ETM_EN_CH1_V 0x00000001U #define AHB_DMA_IN_ETM_EN_CH1_S 5 /** AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1 : R/W; bitpos: [7:6]; default: 0; - * Configures max burst size for Rx channel1. - * 2'b00: single - * 2'b01: incr4 - * 2'b10: incr8 - * 2'b11: incr16 + * Configures maximum burst length for RX channel1. + * 0: SINGLE + * 1: INCR4 + * 2: INCR8 + * 3: Reserved */ #define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1 0x00000003U #define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1_M (AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1_V << AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1_S) @@ -1755,7 +1740,7 @@ extern "C" { #define AHB_DMA_IN_CHECK_OWNER_CH1_S 12 /** AHB_DMA_INFIFO_STATUS_CH1_REG register - * Receive FIFO status of RX channel 1 + * RX channel 1 FIFO status */ #define AHB_DMA_INFIFO_STATUS_CH1_REG (DR_REG_AHB_DMA_BASE + 0x138) /** AHB_DMA_INFIFO_FULL_CH1 : RO; bitpos: [0]; default: 1; @@ -1777,42 +1762,42 @@ extern "C" { #define AHB_DMA_INFIFO_EMPTY_CH1_V 0x00000001U #define AHB_DMA_INFIFO_EMPTY_CH1_S 1 /** AHB_DMA_INFIFO_CNT_CH1 : RO; bitpos: [14:8]; default: 0; - * Represents the number of data bytes in L1 RX FIFO for RX channel 1 + * Represents the number of data bytes in L1 RX FIFO for RX channel 1. */ #define AHB_DMA_INFIFO_CNT_CH1 0x0000007FU #define AHB_DMA_INFIFO_CNT_CH1_M (AHB_DMA_INFIFO_CNT_CH1_V << AHB_DMA_INFIFO_CNT_CH1_S) #define AHB_DMA_INFIFO_CNT_CH1_V 0x0000007FU #define AHB_DMA_INFIFO_CNT_CH1_S 8 /** AHB_DMA_IN_REMAIN_UNDER_1B_CH1 : RO; bitpos: [23]; default: 1; - * reserved + * Reserved. */ #define AHB_DMA_IN_REMAIN_UNDER_1B_CH1 (BIT(23)) #define AHB_DMA_IN_REMAIN_UNDER_1B_CH1_M (AHB_DMA_IN_REMAIN_UNDER_1B_CH1_V << AHB_DMA_IN_REMAIN_UNDER_1B_CH1_S) #define AHB_DMA_IN_REMAIN_UNDER_1B_CH1_V 0x00000001U #define AHB_DMA_IN_REMAIN_UNDER_1B_CH1_S 23 /** AHB_DMA_IN_REMAIN_UNDER_2B_CH1 : RO; bitpos: [24]; default: 1; - * reserved + * Reserved. */ #define AHB_DMA_IN_REMAIN_UNDER_2B_CH1 (BIT(24)) #define AHB_DMA_IN_REMAIN_UNDER_2B_CH1_M (AHB_DMA_IN_REMAIN_UNDER_2B_CH1_V << AHB_DMA_IN_REMAIN_UNDER_2B_CH1_S) #define AHB_DMA_IN_REMAIN_UNDER_2B_CH1_V 0x00000001U #define AHB_DMA_IN_REMAIN_UNDER_2B_CH1_S 24 /** AHB_DMA_IN_REMAIN_UNDER_3B_CH1 : RO; bitpos: [25]; default: 1; - * reserved + * Reserved. */ #define AHB_DMA_IN_REMAIN_UNDER_3B_CH1 (BIT(25)) #define AHB_DMA_IN_REMAIN_UNDER_3B_CH1_M (AHB_DMA_IN_REMAIN_UNDER_3B_CH1_V << AHB_DMA_IN_REMAIN_UNDER_3B_CH1_S) #define AHB_DMA_IN_REMAIN_UNDER_3B_CH1_V 0x00000001U #define AHB_DMA_IN_REMAIN_UNDER_3B_CH1_S 25 /** AHB_DMA_IN_REMAIN_UNDER_4B_CH1 : RO; bitpos: [26]; default: 1; - * reserved + * Reserved. */ #define AHB_DMA_IN_REMAIN_UNDER_4B_CH1 (BIT(26)) #define AHB_DMA_IN_REMAIN_UNDER_4B_CH1_M (AHB_DMA_IN_REMAIN_UNDER_4B_CH1_V << AHB_DMA_IN_REMAIN_UNDER_4B_CH1_S) #define AHB_DMA_IN_REMAIN_UNDER_4B_CH1_V 0x00000001U #define AHB_DMA_IN_REMAIN_UNDER_4B_CH1_S 26 /** AHB_DMA_IN_BUF_HUNGRY_CH1 : RO; bitpos: [27]; default: 0; - * reserved + * Reserved. */ #define AHB_DMA_IN_BUF_HUNGRY_CH1 (BIT(27)) #define AHB_DMA_IN_BUF_HUNGRY_CH1_M (AHB_DMA_IN_BUF_HUNGRY_CH1_V << AHB_DMA_IN_BUF_HUNGRY_CH1_S) @@ -1820,18 +1805,18 @@ extern "C" { #define AHB_DMA_IN_BUF_HUNGRY_CH1_S 27 /** AHB_DMA_IN_POP_CH1_REG register - * Receive FIFO status of RX channel 1 + * Pop control register of RX channel 1 */ #define AHB_DMA_IN_POP_CH1_REG (DR_REG_AHB_DMA_BASE + 0x13c) /** AHB_DMA_INFIFO_RDATA_CH1 : RO; bitpos: [11:0]; default: 2048; - * Represents the data popped from AHB_DMA FIFO. + * Represents the data popped from AHB DMA RX FIFO. */ #define AHB_DMA_INFIFO_RDATA_CH1 0x00000FFFU #define AHB_DMA_INFIFO_RDATA_CH1_M (AHB_DMA_INFIFO_RDATA_CH1_V << AHB_DMA_INFIFO_RDATA_CH1_S) #define AHB_DMA_INFIFO_RDATA_CH1_V 0x00000FFFU #define AHB_DMA_INFIFO_RDATA_CH1_S 0 /** AHB_DMA_INFIFO_POP_CH1 : WT; bitpos: [12]; default: 0; - * Configures whether to pop data from AHB_DMA FIFO. + * Configures whether to pop data from AHB DMA RX FIFO. * 0: Invalid. No effect * 1: Pop */ @@ -1841,22 +1826,21 @@ extern "C" { #define AHB_DMA_INFIFO_POP_CH1_S 12 /** AHB_DMA_IN_LINK_CH1_REG register - * Receive FIFO status of RX channel 1 + * Linked list descriptor configuration and control register of RX channel 1 */ #define AHB_DMA_IN_LINK_CH1_REG (DR_REG_AHB_DMA_BASE + 0x140) /** AHB_DMA_INLINK_AUTO_RET_CH1 : R/W; bitpos: [0]; default: 1; - * Configures whether to return to current receive descriptor's address when there are - * some errors in current receiving data. + * Configures whether to return to the current receive descriptor's address when there + * are some errors in current receiving data. * 0: Not return * 1: Return - * . */ #define AHB_DMA_INLINK_AUTO_RET_CH1 (BIT(0)) #define AHB_DMA_INLINK_AUTO_RET_CH1_M (AHB_DMA_INLINK_AUTO_RET_CH1_V << AHB_DMA_INLINK_AUTO_RET_CH1_S) #define AHB_DMA_INLINK_AUTO_RET_CH1_V 0x00000001U #define AHB_DMA_INLINK_AUTO_RET_CH1_S 0 /** AHB_DMA_INLINK_STOP_CH1 : WT; bitpos: [1]; default: 0; - * Configures whether to stop AHB_DMA's RX channel 1 from receiving data. + * Configures whether to stop RX channel 1 from receiving data. * 0: Invalid. No effect * 1: Stop */ @@ -1865,7 +1849,7 @@ extern "C" { #define AHB_DMA_INLINK_STOP_CH1_V 0x00000001U #define AHB_DMA_INLINK_STOP_CH1_S 1 /** AHB_DMA_INLINK_START_CH1 : WT; bitpos: [2]; default: 0; - * Configures whether to enable AHB_DMA's RX channel 1 for data transfer. + * Configures whether to enable RX channel 1 for data transfer. * 0: Disable * 1: Enable */ @@ -1874,7 +1858,7 @@ extern "C" { #define AHB_DMA_INLINK_START_CH1_V 0x00000001U #define AHB_DMA_INLINK_START_CH1_S 2 /** AHB_DMA_INLINK_RESTART_CH1 : WT; bitpos: [3]; default: 0; - * Configures whether to restart RX channel 1 for AHB_DMA transfer. + * Configures whether to restart RX channel 1 for AHB DMA transfer. * 0: Invalid. No effect * 1: Restart */ @@ -1893,26 +1877,28 @@ extern "C" { #define AHB_DMA_INLINK_PARK_CH1_S 4 /** AHB_DMA_IN_STATE_CH1_REG register - * Receive status of RX channel 1 + * RX channel 1 status */ #define AHB_DMA_IN_STATE_CH1_REG (DR_REG_AHB_DMA_BASE + 0x144) /** AHB_DMA_INLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0; - * reserved + * Represents the lower 18 bits of the next receive descriptor address that is + * pre-read (but not processed yet). If the current receive descriptor is the last + * descriptor, then this field represents the address of the current receive + * descriptor. */ #define AHB_DMA_INLINK_DSCR_ADDR_CH1 0x0003FFFFU #define AHB_DMA_INLINK_DSCR_ADDR_CH1_M (AHB_DMA_INLINK_DSCR_ADDR_CH1_V << AHB_DMA_INLINK_DSCR_ADDR_CH1_S) #define AHB_DMA_INLINK_DSCR_ADDR_CH1_V 0x0003FFFFU #define AHB_DMA_INLINK_DSCR_ADDR_CH1_S 0 /** AHB_DMA_IN_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0; - * reserved + * Reserved. */ #define AHB_DMA_IN_DSCR_STATE_CH1 0x00000003U #define AHB_DMA_IN_DSCR_STATE_CH1_M (AHB_DMA_IN_DSCR_STATE_CH1_V << AHB_DMA_IN_DSCR_STATE_CH1_S) #define AHB_DMA_IN_DSCR_STATE_CH1_V 0x00000003U #define AHB_DMA_IN_DSCR_STATE_CH1_S 18 /** AHB_DMA_IN_STATE_CH1 : RO; bitpos: [22:20]; default: 0; - * Represents the address of the lower 18 bits of the next receive descriptor to be - * processed. + * Reserved. */ #define AHB_DMA_IN_STATE_CH1 0x00000007U #define AHB_DMA_IN_STATE_CH1_M (AHB_DMA_IN_STATE_CH1_V << AHB_DMA_IN_STATE_CH1_S) @@ -1933,12 +1919,11 @@ extern "C" { #define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1_S 0 /** AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1_REG register - * Receive descriptor address when errors occur of RX channel 1 + * Reserved */ #define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x14c) /** AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the receive descriptor when there are some errors in the - * currently received data. + * Reserved. */ #define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1 0xFFFFFFFFU #define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1_M (AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1_V << AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1_S) @@ -1946,12 +1931,13 @@ extern "C" { #define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1_S 0 /** AHB_DMA_IN_DSCR_CH1_REG register - * Current receive descriptor address of RX channel 1 + * Address of the next receive descriptor pointed by the current pre-read receive + * descriptor on RX channel 1 */ #define AHB_DMA_IN_DSCR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x150) /** AHB_DMA_INLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0; * Represents the address of the next receive descriptor x+1 pointed by the current - * receive descriptor that has already been fetched. + * receive descriptor that is pre-read. */ #define AHB_DMA_INLINK_DSCR_CH1 0xFFFFFFFFU #define AHB_DMA_INLINK_DSCR_CH1_M (AHB_DMA_INLINK_DSCR_CH1_V << AHB_DMA_INLINK_DSCR_CH1_S) @@ -1959,12 +1945,11 @@ extern "C" { #define AHB_DMA_INLINK_DSCR_CH1_S 0 /** AHB_DMA_IN_DSCR_BF0_CH1_REG register - * The last receive descriptor address of RX channel 1 + * Address of the current pre-read receive descriptor on RX channel 1 */ #define AHB_DMA_IN_DSCR_BF0_CH1_REG (DR_REG_AHB_DMA_BASE + 0x154) /** AHB_DMA_INLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the current receive descriptor x that has already been - * fetched. + * Represents the address of the current receive descriptor x that is pre-read. */ #define AHB_DMA_INLINK_DSCR_BF0_CH1 0xFFFFFFFFU #define AHB_DMA_INLINK_DSCR_BF0_CH1_M (AHB_DMA_INLINK_DSCR_BF0_CH1_V << AHB_DMA_INLINK_DSCR_BF0_CH1_S) @@ -1972,25 +1957,25 @@ extern "C" { #define AHB_DMA_INLINK_DSCR_BF0_CH1_S 0 /** AHB_DMA_IN_DSCR_BF1_CH1_REG register - * The second-to-last receive descriptor address of RX channel 1 + * Address of the previous pre-read receive descriptor on RX channel 1 */ #define AHB_DMA_IN_DSCR_BF1_CH1_REG (DR_REG_AHB_DMA_BASE + 0x158) /** AHB_DMA_INLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the previous receive descriptor x-1 that has already been - * fetched. + * Represents the address of the previous receive descriptor x-1 that is pre-read. */ #define AHB_DMA_INLINK_DSCR_BF1_CH1 0xFFFFFFFFU #define AHB_DMA_INLINK_DSCR_BF1_CH1_M (AHB_DMA_INLINK_DSCR_BF1_CH1_V << AHB_DMA_INLINK_DSCR_BF1_CH1_S) #define AHB_DMA_INLINK_DSCR_BF1_CH1_V 0xFFFFFFFFU #define AHB_DMA_INLINK_DSCR_BF1_CH1_S 0 -/** AHB_DMA_IN_PERI_CH1_REG register +/** AHB_DMA_IN_PRI_CH1_REG register * Priority register of RX channel 1 */ -#define AHB_DMA_IN_PERI_CH1_REG (DR_REG_AHB_DMA_BASE + 0x15c) +#define AHB_DMA_IN_PRI_CH1_REG (DR_REG_AHB_DMA_BASE + 0x15c) /** AHB_DMA_RX_PRI_CH1 : R/W; bitpos: [3:0]; default: 0; - * Configures the priority of RX channel 1.The larger of the value, the higher of the - * priority.. + * Configures the priority of RX channel 1. The larger the value, the higher the + * priority. + * Value range: 0 ~ 5 */ #define AHB_DMA_RX_PRI_CH1 0x0000000FU #define AHB_DMA_RX_PRI_CH1_M (AHB_DMA_RX_PRI_CH1_V << AHB_DMA_RX_PRI_CH1_S) @@ -2004,13 +1989,14 @@ extern "C" { /** AHB_DMA_PERI_IN_SEL_CH1 : R/W; bitpos: [5:0]; default: 63; * Configures the peripheral connected to RX channel 1. * 0: Dummy - * 1: SPI2 + * 1: GP-SPI * 2: Dummy - * 3: I2S0 + * 3: I2S * 4 ~ 6: Dummy * 7: SHA - * 8: ADC_DAC - * 9~15: Dummy + * 8: ADC + * 9 ~ 15: Dummy + * 16 ~ 63: Invalid */ #define AHB_DMA_PERI_IN_SEL_CH1 0x0000003FU #define AHB_DMA_PERI_IN_SEL_CH1_M (AHB_DMA_PERI_IN_SEL_CH1_V << AHB_DMA_PERI_IN_SEL_CH1_S) @@ -2018,11 +2004,11 @@ extern "C" { #define AHB_DMA_PERI_IN_SEL_CH1_S 0 /** AHB_DMA_IN_DONE_DES_ADDR_CH1_REG register - * RX_done Inlink descriptor address of RX channel 1 + * Address of the completed inlink descriptor on RX channel 1 */ #define AHB_DMA_IN_DONE_DES_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x170) /** AHB_DMA_IN_DONE_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the inlink descriptor when this descriptor is completed . + * Represents the address of the inlink descriptor when this descriptor is completed. */ #define AHB_DMA_IN_DONE_DES_ADDR_CH1 0xFFFFFFFFU #define AHB_DMA_IN_DONE_DES_ADDR_CH1_M (AHB_DMA_IN_DONE_DES_ADDR_CH1_V << AHB_DMA_IN_DONE_DES_ADDR_CH1_S) @@ -2034,7 +2020,7 @@ extern "C" { */ #define AHB_DMA_OUT_CONF0_CH1_REG (DR_REG_AHB_DMA_BASE + 0x190) /** AHB_DMA_OUT_RST_CH1 : R/W; bitpos: [0]; default: 0; - * Configures the reset state of AHB_DMA channel 1 TX FSM and TX FIFO pointer. + * Configures the reset state of TX channel 1 FSM and TX FIFO pointer. * 0: Release reset * 1: Reset */ @@ -2043,7 +2029,7 @@ extern "C" { #define AHB_DMA_OUT_RST_CH1_V 0x00000001U #define AHB_DMA_OUT_RST_CH1_S 0 /** AHB_DMA_OUT_LOOP_TEST_CH1 : R/W; bitpos: [1]; default: 0; - * reserved + * Configures the owner bit value for outlink write-back. */ #define AHB_DMA_OUT_LOOP_TEST_CH1 (BIT(1)) #define AHB_DMA_OUT_LOOP_TEST_CH1_M (AHB_DMA_OUT_LOOP_TEST_CH1_V << AHB_DMA_OUT_LOOP_TEST_CH1_S) @@ -2062,9 +2048,9 @@ extern "C" { /** AHB_DMA_OUT_EOF_MODE_CH1 : R/W; bitpos: [3]; default: 1; * Configures when to generate EOF flag. * 0: EOF flag for TX channel 1 is generated when data to be transmitted has been - * pushed into FIFO in AHB_DMA. + * pushed into FIFO in AHB DMA. * 1: EOF flag for TX channel 1 is generated when data to be transmitted has been - * popped from FIFO in AHB_DMA. + * popped from FIFO in AHB DMA. */ #define AHB_DMA_OUT_EOF_MODE_CH1 (BIT(3)) #define AHB_DMA_OUT_EOF_MODE_CH1_M (AHB_DMA_OUT_EOF_MODE_CH1_V << AHB_DMA_OUT_EOF_MODE_CH1_S) @@ -2090,11 +2076,11 @@ extern "C" { #define AHB_DMA_OUT_ETM_EN_CH1_V 0x00000001U #define AHB_DMA_OUT_ETM_EN_CH1_S 6 /** AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1 : R/W; bitpos: [9:8]; default: 0; - * Configures max burst size for TX channel1. - * 2'b00: single - * 2'b01: incr4 - * 2'b10: incr8 - * 2'b11: incr16 + * Configures maximum burst length for TX channel1. + * 0: SINGLE + * 1: INCR4 + * 2: INCR8 + * 3: Reserved */ #define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1 0x00000003U #define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1_M (AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1_V << AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1_S) @@ -2116,7 +2102,7 @@ extern "C" { #define AHB_DMA_OUT_CHECK_OWNER_CH1_S 12 /** AHB_DMA_OUTFIFO_STATUS_CH1_REG register - * Receive FIFO status of RX channel 1 + * TX channel 1 FIFO status */ #define AHB_DMA_OUTFIFO_STATUS_CH1_REG (DR_REG_AHB_DMA_BASE + 0x198) /** AHB_DMA_OUTFIFO_FULL_CH1 : RO; bitpos: [0]; default: 0; @@ -2138,35 +2124,35 @@ extern "C" { #define AHB_DMA_OUTFIFO_EMPTY_CH1_V 0x00000001U #define AHB_DMA_OUTFIFO_EMPTY_CH1_S 1 /** AHB_DMA_OUTFIFO_CNT_CH1 : RO; bitpos: [14:8]; default: 0; - * Represents the number of data bytes in L1 TX FIFO for TX channel 1 + * Represents the number of data bytes in L1 TX FIFO for TX channel 1. */ #define AHB_DMA_OUTFIFO_CNT_CH1 0x0000007FU #define AHB_DMA_OUTFIFO_CNT_CH1_M (AHB_DMA_OUTFIFO_CNT_CH1_V << AHB_DMA_OUTFIFO_CNT_CH1_S) #define AHB_DMA_OUTFIFO_CNT_CH1_V 0x0000007FU #define AHB_DMA_OUTFIFO_CNT_CH1_S 8 /** AHB_DMA_OUT_REMAIN_UNDER_1B_CH1 : RO; bitpos: [23]; default: 1; - * reserved + * Reserved. */ #define AHB_DMA_OUT_REMAIN_UNDER_1B_CH1 (BIT(23)) #define AHB_DMA_OUT_REMAIN_UNDER_1B_CH1_M (AHB_DMA_OUT_REMAIN_UNDER_1B_CH1_V << AHB_DMA_OUT_REMAIN_UNDER_1B_CH1_S) #define AHB_DMA_OUT_REMAIN_UNDER_1B_CH1_V 0x00000001U #define AHB_DMA_OUT_REMAIN_UNDER_1B_CH1_S 23 /** AHB_DMA_OUT_REMAIN_UNDER_2B_CH1 : RO; bitpos: [24]; default: 1; - * reserved + * Reserved. */ #define AHB_DMA_OUT_REMAIN_UNDER_2B_CH1 (BIT(24)) #define AHB_DMA_OUT_REMAIN_UNDER_2B_CH1_M (AHB_DMA_OUT_REMAIN_UNDER_2B_CH1_V << AHB_DMA_OUT_REMAIN_UNDER_2B_CH1_S) #define AHB_DMA_OUT_REMAIN_UNDER_2B_CH1_V 0x00000001U #define AHB_DMA_OUT_REMAIN_UNDER_2B_CH1_S 24 /** AHB_DMA_OUT_REMAIN_UNDER_3B_CH1 : RO; bitpos: [25]; default: 1; - * reserved + * Reserved. */ #define AHB_DMA_OUT_REMAIN_UNDER_3B_CH1 (BIT(25)) #define AHB_DMA_OUT_REMAIN_UNDER_3B_CH1_M (AHB_DMA_OUT_REMAIN_UNDER_3B_CH1_V << AHB_DMA_OUT_REMAIN_UNDER_3B_CH1_S) #define AHB_DMA_OUT_REMAIN_UNDER_3B_CH1_V 0x00000001U #define AHB_DMA_OUT_REMAIN_UNDER_3B_CH1_S 25 /** AHB_DMA_OUT_REMAIN_UNDER_4B_CH1 : RO; bitpos: [26]; default: 1; - * reserved + * Reserved. */ #define AHB_DMA_OUT_REMAIN_UNDER_4B_CH1 (BIT(26)) #define AHB_DMA_OUT_REMAIN_UNDER_4B_CH1_M (AHB_DMA_OUT_REMAIN_UNDER_4B_CH1_V << AHB_DMA_OUT_REMAIN_UNDER_4B_CH1_S) @@ -2178,16 +2164,16 @@ extern "C" { */ #define AHB_DMA_OUT_PUSH_CH1_REG (DR_REG_AHB_DMA_BASE + 0x19c) /** AHB_DMA_OUTFIFO_WDATA_CH1 : R/W; bitpos: [8:0]; default: 0; - * Configures whether to push data into AHB_DMA FIFO. - * 0: Invalid. No effect - * 1: Push + * Represents the data that need to be pushed into AHB DMA TX FIFO. */ #define AHB_DMA_OUTFIFO_WDATA_CH1 0x000001FFU #define AHB_DMA_OUTFIFO_WDATA_CH1_M (AHB_DMA_OUTFIFO_WDATA_CH1_V << AHB_DMA_OUTFIFO_WDATA_CH1_S) #define AHB_DMA_OUTFIFO_WDATA_CH1_V 0x000001FFU #define AHB_DMA_OUTFIFO_WDATA_CH1_S 0 /** AHB_DMA_OUTFIFO_PUSH_CH1 : WT; bitpos: [9]; default: 0; - * Configures the data that need to be pushed into AHB_DMA FIFO. + * Configures whether to push data into AHB DMA TX FIFO. + * 0: Invalid. No effect + * 1: Push */ #define AHB_DMA_OUTFIFO_PUSH_CH1 (BIT(9)) #define AHB_DMA_OUTFIFO_PUSH_CH1_M (AHB_DMA_OUTFIFO_PUSH_CH1_V << AHB_DMA_OUTFIFO_PUSH_CH1_S) @@ -2195,11 +2181,11 @@ extern "C" { #define AHB_DMA_OUTFIFO_PUSH_CH1_S 9 /** AHB_DMA_OUT_LINK_CH1_REG register - * Push control register of TX channel 1 + * Linked list descriptor configuration and control register of TX channel 1 */ #define AHB_DMA_OUT_LINK_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1a0) /** AHB_DMA_OUTLINK_STOP_CH1 : WT; bitpos: [0]; default: 0; - * Configures whether to stop AHB_DMA's TX channel 1 from transmitting data. + * Configures whether to stop TX channel 1 from transmitting data. * 0: Invalid. No effect * 1: Stop */ @@ -2208,7 +2194,7 @@ extern "C" { #define AHB_DMA_OUTLINK_STOP_CH1_V 0x00000001U #define AHB_DMA_OUTLINK_STOP_CH1_S 0 /** AHB_DMA_OUTLINK_START_CH1 : WT; bitpos: [1]; default: 0; - * Configures whether to enable AHB_DMA's TX channel 1 for data transfer. + * Configures whether to enable TX channel 1 for data transfer. * 0: Disable * 1: Enable */ @@ -2217,7 +2203,7 @@ extern "C" { #define AHB_DMA_OUTLINK_START_CH1_V 0x00000001U #define AHB_DMA_OUTLINK_START_CH1_S 1 /** AHB_DMA_OUTLINK_RESTART_CH1 : WT; bitpos: [2]; default: 0; - * Configures whether to restart TX channel 1 for AHB_DMA transfer. + * Configures whether to restart TX channel 1 for AHB DMA transfer. * 0: Invalid. No effect * 1: Restart */ @@ -2236,26 +2222,28 @@ extern "C" { #define AHB_DMA_OUTLINK_PARK_CH1_S 3 /** AHB_DMA_OUT_STATE_CH1_REG register - * Transmit status of TX channel 1 + * TX channel 1 status */ #define AHB_DMA_OUT_STATE_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1a4) /** AHB_DMA_OUTLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0; - * Represents the lower 18 bits of the address of the next transmit descriptor to be - * processed. + * Represents the lower 18 bits of the next transmit descriptor address that is + * pre-read (but not processed yet). If the current transmit descriptor is the last + * descriptor, then this field represents the address of the current transmit + * descriptor. */ #define AHB_DMA_OUTLINK_DSCR_ADDR_CH1 0x0003FFFFU #define AHB_DMA_OUTLINK_DSCR_ADDR_CH1_M (AHB_DMA_OUTLINK_DSCR_ADDR_CH1_V << AHB_DMA_OUTLINK_DSCR_ADDR_CH1_S) #define AHB_DMA_OUTLINK_DSCR_ADDR_CH1_V 0x0003FFFFU #define AHB_DMA_OUTLINK_DSCR_ADDR_CH1_S 0 /** AHB_DMA_OUT_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0; - * reserved + * Reserved. */ #define AHB_DMA_OUT_DSCR_STATE_CH1 0x00000003U #define AHB_DMA_OUT_DSCR_STATE_CH1_M (AHB_DMA_OUT_DSCR_STATE_CH1_V << AHB_DMA_OUT_DSCR_STATE_CH1_S) #define AHB_DMA_OUT_DSCR_STATE_CH1_V 0x00000003U #define AHB_DMA_OUT_DSCR_STATE_CH1_S 18 /** AHB_DMA_OUT_STATE_CH1 : RO; bitpos: [22:20]; default: 0; - * reserved + * Reserved. */ #define AHB_DMA_OUT_STATE_CH1 0x00000007U #define AHB_DMA_OUT_STATE_CH1_M (AHB_DMA_OUT_STATE_CH1_V << AHB_DMA_OUT_STATE_CH1_S) @@ -2289,12 +2277,13 @@ extern "C" { #define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1_S 0 /** AHB_DMA_OUT_DSCR_CH1_REG register - * Current transmit descriptor address of TX channel 1 + * Address of the next transmit descriptor pointed by the current pre-read transmit + * descriptor on TX channel 1 */ #define AHB_DMA_OUT_DSCR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1b0) /** AHB_DMA_OUTLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0; * Represents the address of the next transmit descriptor y+1 pointed by the current - * transmit descriptor that has already been fetched. + * transmit descriptor that is pre-read. */ #define AHB_DMA_OUTLINK_DSCR_CH1 0xFFFFFFFFU #define AHB_DMA_OUTLINK_DSCR_CH1_M (AHB_DMA_OUTLINK_DSCR_CH1_V << AHB_DMA_OUTLINK_DSCR_CH1_S) @@ -2302,12 +2291,11 @@ extern "C" { #define AHB_DMA_OUTLINK_DSCR_CH1_S 0 /** AHB_DMA_OUT_DSCR_BF0_CH1_REG register - * The last transmit descriptor address of TX channel 1 + * Address of the current pre-read transmit descriptor on TX channel 1 */ #define AHB_DMA_OUT_DSCR_BF0_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1b4) /** AHB_DMA_OUTLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the current transmit descriptor y that has already been - * fetched. + * Represents the address of the current transmit descriptor y that is pre-read. */ #define AHB_DMA_OUTLINK_DSCR_BF0_CH1 0xFFFFFFFFU #define AHB_DMA_OUTLINK_DSCR_BF0_CH1_M (AHB_DMA_OUTLINK_DSCR_BF0_CH1_V << AHB_DMA_OUTLINK_DSCR_BF0_CH1_S) @@ -2315,25 +2303,25 @@ extern "C" { #define AHB_DMA_OUTLINK_DSCR_BF0_CH1_S 0 /** AHB_DMA_OUT_DSCR_BF1_CH1_REG register - * The second-to-last transmit descriptor address of TX channel 1 + * Address of the previous pre-read transmit descriptor on TX channel 1 */ #define AHB_DMA_OUT_DSCR_BF1_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1b8) /** AHB_DMA_OUTLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the previous transmit descriptor y-1 that has already - * been fetched. + * Represents the address of the previous transmit descriptor y-1 that is pre-read. */ #define AHB_DMA_OUTLINK_DSCR_BF1_CH1 0xFFFFFFFFU #define AHB_DMA_OUTLINK_DSCR_BF1_CH1_M (AHB_DMA_OUTLINK_DSCR_BF1_CH1_V << AHB_DMA_OUTLINK_DSCR_BF1_CH1_S) #define AHB_DMA_OUTLINK_DSCR_BF1_CH1_V 0xFFFFFFFFU #define AHB_DMA_OUTLINK_DSCR_BF1_CH1_S 0 -/** AHB_DMA_OUT_PERI_CH1_REG register +/** AHB_DMA_OUT_PRI_CH1_REG register * Priority register of TX channel 1 */ -#define AHB_DMA_OUT_PERI_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1bc) +#define AHB_DMA_OUT_PRI_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1bc) /** AHB_DMA_TX_PRI_CH1 : R/W; bitpos: [3:0]; default: 0; - * Configures the priority of TX channel 1.The larger of the value, the higher of the - * priority.. + * Configures the priority of TX channel 1. The larger the value, the higher the + * priority. + * Value range: 0 ~ 5 */ #define AHB_DMA_TX_PRI_CH1 0x0000000FU #define AHB_DMA_TX_PRI_CH1_M (AHB_DMA_TX_PRI_CH1_V << AHB_DMA_TX_PRI_CH1_S) @@ -2347,13 +2335,14 @@ extern "C" { /** AHB_DMA_PERI_OUT_SEL_CH1 : R/W; bitpos: [5:0]; default: 63; * Configures the peripheral connected to TX channel 1. * 0: Dummy - * 1: SPI2 + * 1: GP-SPI * 2: Dummy - * 3: I2S0 + * 3: I2S * 4 ~ 6: Dummy * 7: SHA - * 8: ADC_DAC - * 9~15: Dummy + * 8: ADC + * 9 ~ 15: Dummy + * 16 ~ 63: Invalid */ #define AHB_DMA_PERI_OUT_SEL_CH1 0x0000003FU #define AHB_DMA_PERI_OUT_SEL_CH1_M (AHB_DMA_PERI_OUT_SEL_CH1_V << AHB_DMA_PERI_OUT_SEL_CH1_S) @@ -2361,7 +2350,7 @@ extern "C" { #define AHB_DMA_PERI_OUT_SEL_CH1_S 0 /** AHB_DMA_OUT_DONE_DES_ADDR_CH1_REG register - * TX done outlink descriptor address of TX channel 1 + * Address of the completed outlink descriptor on TX channel 1 */ #define AHB_DMA_OUT_DONE_DES_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1d0) /** AHB_DMA_OUT_DONE_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; @@ -2376,20 +2365,23 @@ extern "C" { * TX channel 0 arbitration weight configuration register */ #define AHB_DMA_TX_CH_ARB_WEIGHT_CH0_REG (DR_REG_AHB_DMA_BASE + 0x2dc) -/** AHB_DMA_TX_ARB_WEIGHT_VALUE_CH0 : R/W; bitpos: [3:0]; default: 0; - * Configures the weight(i.e the number of tokens) of TX channel0 +/** AHB_DMA_TX_CH_ARB_WEIGHT_CH0 : R/W; bitpos: [3:0]; default: 0; + * Configures the weight (i.e. the number of tokens) of TX channel0. + * Value range: 0 ~ 15. */ -#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH0 0x0000000FU -#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH0_M (AHB_DMA_TX_ARB_WEIGHT_VALUE_CH0_V << AHB_DMA_TX_ARB_WEIGHT_VALUE_CH0_S) -#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH0_V 0x0000000FU -#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH0_S 0 +#define AHB_DMA_TX_CH_ARB_WEIGHT_CH0 0x0000000FU +#define AHB_DMA_TX_CH_ARB_WEIGHT_CH0_M (AHB_DMA_TX_CH_ARB_WEIGHT_CH0_V << AHB_DMA_TX_CH_ARB_WEIGHT_CH0_S) +#define AHB_DMA_TX_CH_ARB_WEIGHT_CH0_V 0x0000000FU +#define AHB_DMA_TX_CH_ARB_WEIGHT_CH0_S 0 -/** AHB_DMA_TX_ARB_WEIGHT_OPT_DIR_CH0_REG register +/** AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH0_REG register * TX channel 0 weight arbitration optimization enable register */ -#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x2e0) +#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH0_REG (DR_REG_AHB_DMA_BASE + 0x2e0) /** AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH0 : R/W; bitpos: [0]; default: 0; - * reserved + * Configures whether to enable weight optimization for TX channel 0. + * 0: Enable + * 1: Disable */ #define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH0 (BIT(0)) #define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH0_M (AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH0_V << AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH0_S) @@ -2400,20 +2392,23 @@ extern "C" { * TX channel 1 arbitration weight configuration register */ #define AHB_DMA_TX_CH_ARB_WEIGHT_CH1_REG (DR_REG_AHB_DMA_BASE + 0x304) -/** AHB_DMA_TX_ARB_WEIGHT_VALUE_CH1 : R/W; bitpos: [3:0]; default: 0; - * Configures the weight(i.e the number of tokens) of TX channel1 +/** AHB_DMA_TX_CH_ARB_WEIGHT_CH1 : R/W; bitpos: [3:0]; default: 0; + * Configures the weight (i.e. the number of tokens) of TX channel1. + * Value range: 0 ~ 15. */ -#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH1 0x0000000FU -#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH1_M (AHB_DMA_TX_ARB_WEIGHT_VALUE_CH1_V << AHB_DMA_TX_ARB_WEIGHT_VALUE_CH1_S) -#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH1_V 0x0000000FU -#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH1_S 0 +#define AHB_DMA_TX_CH_ARB_WEIGHT_CH1 0x0000000FU +#define AHB_DMA_TX_CH_ARB_WEIGHT_CH1_M (AHB_DMA_TX_CH_ARB_WEIGHT_CH1_V << AHB_DMA_TX_CH_ARB_WEIGHT_CH1_S) +#define AHB_DMA_TX_CH_ARB_WEIGHT_CH1_V 0x0000000FU +#define AHB_DMA_TX_CH_ARB_WEIGHT_CH1_S 0 -/** AHB_DMA_TX_ARB_WEIGHT_OPT_DIR_CH1_REG register +/** AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH1_REG register * TX channel 1 weight arbitration optimization enable register */ -#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x308) +#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH1_REG (DR_REG_AHB_DMA_BASE + 0x308) /** AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH1 : R/W; bitpos: [0]; default: 0; - * reserved + * Configures whether to enable weight optimization for TX channel 1. + * 0: Enable + * 1: Disable */ #define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH1 (BIT(0)) #define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH1_M (AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH1_V << AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH1_S) @@ -2424,20 +2419,23 @@ extern "C" { * RX channel 0 arbitration weight configuration register */ #define AHB_DMA_RX_CH_ARB_WEIGHT_CH0_REG (DR_REG_AHB_DMA_BASE + 0x354) -/** AHB_DMA_RX_ARB_WEIGHT_VALUE_CH0 : R/W; bitpos: [3:0]; default: 0; - * Configures the weight(i.e the number of tokens) of RX channel0 +/** AHB_DMA_RX_CH_ARB_WEIGHT_CH0 : R/W; bitpos: [3:0]; default: 0; + * Configures the weight (i.e. the number of tokens) of RX channel0. + * Value range: 0 ~ 15. */ -#define AHB_DMA_RX_ARB_WEIGHT_VALUE_CH0 0x0000000FU -#define AHB_DMA_RX_ARB_WEIGHT_VALUE_CH0_M (AHB_DMA_RX_ARB_WEIGHT_VALUE_CH0_V << AHB_DMA_RX_ARB_WEIGHT_VALUE_CH0_S) -#define AHB_DMA_RX_ARB_WEIGHT_VALUE_CH0_V 0x0000000FU -#define AHB_DMA_RX_ARB_WEIGHT_VALUE_CH0_S 0 +#define AHB_DMA_RX_CH_ARB_WEIGHT_CH0 0x0000000FU +#define AHB_DMA_RX_CH_ARB_WEIGHT_CH0_M (AHB_DMA_RX_CH_ARB_WEIGHT_CH0_V << AHB_DMA_RX_CH_ARB_WEIGHT_CH0_S) +#define AHB_DMA_RX_CH_ARB_WEIGHT_CH0_V 0x0000000FU +#define AHB_DMA_RX_CH_ARB_WEIGHT_CH0_S 0 -/** AHB_DMA_RX_ARB_WEIGHT_OPT_DIR_CH0_REG register +/** AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH0_REG register * RX channel 0 weight arbitration optimization enable register */ -#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x358) +#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH0_REG (DR_REG_AHB_DMA_BASE + 0x358) /** AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH0 : R/W; bitpos: [0]; default: 0; - * reserved + * Configures whether to enable weight optimization for RX channel 0. + * 0: Enable + * 1: Disable */ #define AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH0 (BIT(0)) #define AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH0_M (AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH0_V << AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH0_S) @@ -2448,20 +2446,23 @@ extern "C" { * RX channel 1 arbitration weight configuration register */ #define AHB_DMA_RX_CH_ARB_WEIGHT_CH1_REG (DR_REG_AHB_DMA_BASE + 0x37c) -/** AHB_DMA_RX_ARB_WEIGHT_VALUE_CH1 : R/W; bitpos: [3:0]; default: 0; - * Configures the weight(i.e the number of tokens) of RX channel1 +/** AHB_DMA_RX_CH_ARB_WEIGHT_CH1 : R/W; bitpos: [3:0]; default: 0; + * Configures the weight (i.e. the number of tokens) of RX channel1. + * Value range: 0 ~ 15. */ -#define AHB_DMA_RX_ARB_WEIGHT_VALUE_CH1 0x0000000FU -#define AHB_DMA_RX_ARB_WEIGHT_VALUE_CH1_M (AHB_DMA_RX_ARB_WEIGHT_VALUE_CH1_V << AHB_DMA_RX_ARB_WEIGHT_VALUE_CH1_S) -#define AHB_DMA_RX_ARB_WEIGHT_VALUE_CH1_V 0x0000000FU -#define AHB_DMA_RX_ARB_WEIGHT_VALUE_CH1_S 0 +#define AHB_DMA_RX_CH_ARB_WEIGHT_CH1 0x0000000FU +#define AHB_DMA_RX_CH_ARB_WEIGHT_CH1_M (AHB_DMA_RX_CH_ARB_WEIGHT_CH1_V << AHB_DMA_RX_CH_ARB_WEIGHT_CH1_S) +#define AHB_DMA_RX_CH_ARB_WEIGHT_CH1_V 0x0000000FU +#define AHB_DMA_RX_CH_ARB_WEIGHT_CH1_S 0 -/** AHB_DMA_RX_ARB_WEIGHT_OPT_DIR_CH1_REG register +/** AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1_REG register * RX channel 1 weight arbitration optimization enable register */ -#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x380) +#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1_REG (DR_REG_AHB_DMA_BASE + 0x380) /** AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1 : R/W; bitpos: [0]; default: 0; - * reserved + * Configures whether to enable weight optimization for RX channel 1. + * 0: Enable + * 1: Disable */ #define AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1 (BIT(0)) #define AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1_M (AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1_V << AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1_S) @@ -2469,11 +2470,11 @@ extern "C" { #define AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1_S 0 /** AHB_DMA_IN_LINK_ADDR_CH0_REG register - * Link list descriptor address configuration of RX channel 0 + * Linked list descriptor configuration register of RX channel 0 */ #define AHB_DMA_IN_LINK_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x3ac) /** AHB_DMA_INLINK_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0; - * Configures the 32 bits of the first receive descriptor's address + * Represents the first receive descriptor's address. */ #define AHB_DMA_INLINK_ADDR_CH0 0xFFFFFFFFU #define AHB_DMA_INLINK_ADDR_CH0_M (AHB_DMA_INLINK_ADDR_CH0_V << AHB_DMA_INLINK_ADDR_CH0_S) @@ -2481,11 +2482,11 @@ extern "C" { #define AHB_DMA_INLINK_ADDR_CH0_S 0 /** AHB_DMA_IN_LINK_ADDR_CH1_REG register - * Link list descriptor address configuration of RX channel 1 + * Linked list descriptor configuration register of RX channel 1 */ #define AHB_DMA_IN_LINK_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x3b0) /** AHB_DMA_INLINK_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0; - * Configures the 32 bits of the first receive descriptor's address + * Represents the first receive descriptor's address. */ #define AHB_DMA_INLINK_ADDR_CH1 0xFFFFFFFFU #define AHB_DMA_INLINK_ADDR_CH1_M (AHB_DMA_INLINK_ADDR_CH1_V << AHB_DMA_INLINK_ADDR_CH1_S) @@ -2493,11 +2494,11 @@ extern "C" { #define AHB_DMA_INLINK_ADDR_CH1_S 0 /** AHB_DMA_OUT_LINK_ADDR_CH0_REG register - * Link list descriptor address configuration of TX channel 0 + * Linked list descriptor configuration register of TX channel 0 */ #define AHB_DMA_OUT_LINK_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x3b8) /** AHB_DMA_OUTLINK_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0; - * Configures the 32 bits of the first receive descriptor's address. + * Represents the first transmit descriptor's address. */ #define AHB_DMA_OUTLINK_ADDR_CH0 0xFFFFFFFFU #define AHB_DMA_OUTLINK_ADDR_CH0_M (AHB_DMA_OUTLINK_ADDR_CH0_V << AHB_DMA_OUTLINK_ADDR_CH0_S) @@ -2505,11 +2506,11 @@ extern "C" { #define AHB_DMA_OUTLINK_ADDR_CH0_S 0 /** AHB_DMA_OUT_LINK_ADDR_CH1_REG register - * Link list descriptor address configuration of TX channel 1 + * Linked list descriptor configuration register of TX channel 1 */ #define AHB_DMA_OUT_LINK_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x3bc) /** AHB_DMA_OUTLINK_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0; - * Configures the 32 bits of the first receive descriptor's address. + * Represents the first transmit descriptor's address. */ #define AHB_DMA_OUTLINK_ADDR_CH1 0xFFFFFFFFU #define AHB_DMA_OUTLINK_ADDR_CH1_M (AHB_DMA_OUTLINK_ADDR_CH1_V << AHB_DMA_OUTLINK_ADDR_CH1_S) @@ -2521,7 +2522,7 @@ extern "C" { */ #define AHB_DMA_INTR_MEM_START_ADDR_REG (DR_REG_AHB_DMA_BASE + 0x3c4) /** AHB_DMA_ACCESS_INTR_MEM_START_ADDR : R/W; bitpos: [31:0]; default: 0; - * Accessible address space start address configuration register + * Configures the start address of accessible address space. */ #define AHB_DMA_ACCESS_INTR_MEM_START_ADDR 0xFFFFFFFFU #define AHB_DMA_ACCESS_INTR_MEM_START_ADDR_M (AHB_DMA_ACCESS_INTR_MEM_START_ADDR_V << AHB_DMA_ACCESS_INTR_MEM_START_ADDR_S) @@ -2541,11 +2542,11 @@ extern "C" { #define AHB_DMA_ACCESS_INTR_MEM_END_ADDR_S 0 /** AHB_DMA_ARB_TIMEOUT_TX_REG register - * TX arbitration timeout configuration register + * Reserved */ #define AHB_DMA_ARB_TIMEOUT_TX_REG (DR_REG_AHB_DMA_BASE + 0x3cc) /** AHB_DMA_ARB_TIMEOUT_TX : R/W; bitpos: [15:0]; default: 0; - * Configures the time slot for TX. Measurement unit: AHB bus clock cycle. + * Reserved. */ #define AHB_DMA_ARB_TIMEOUT_TX 0x0000FFFFU #define AHB_DMA_ARB_TIMEOUT_TX_M (AHB_DMA_ARB_TIMEOUT_TX_V << AHB_DMA_ARB_TIMEOUT_TX_S) @@ -2553,11 +2554,11 @@ extern "C" { #define AHB_DMA_ARB_TIMEOUT_TX_S 0 /** AHB_DMA_ARB_TIMEOUT_RX_REG register - * RX arbitration timeout configuration register + * Reserved */ #define AHB_DMA_ARB_TIMEOUT_RX_REG (DR_REG_AHB_DMA_BASE + 0x3d0) /** AHB_DMA_ARB_TIMEOUT_RX : R/W; bitpos: [15:0]; default: 0; - * Configures the time slot for RX. Measurement unit: AHB bus clock cycle. + * Reserved. */ #define AHB_DMA_ARB_TIMEOUT_RX 0x0000FFFFU #define AHB_DMA_ARB_TIMEOUT_RX_M (AHB_DMA_ARB_TIMEOUT_RX_V << AHB_DMA_ARB_TIMEOUT_RX_S) @@ -2565,13 +2566,11 @@ extern "C" { #define AHB_DMA_ARB_TIMEOUT_RX_S 0 /** AHB_DMA_WEIGHT_EN_TX_REG register - * TX weight arbitration enable register + * Reserved */ #define AHB_DMA_WEIGHT_EN_TX_REG (DR_REG_AHB_DMA_BASE + 0x3d4) /** AHB_DMA_WEIGHT_EN_TX : R/W; bitpos: [0]; default: 0; - * Configures whether to enable weight arbitration for TX. - * 0: Disable - * 1: Enable + * Reserved. */ #define AHB_DMA_WEIGHT_EN_TX (BIT(0)) #define AHB_DMA_WEIGHT_EN_TX_M (AHB_DMA_WEIGHT_EN_TX_V << AHB_DMA_WEIGHT_EN_TX_S) @@ -2579,13 +2578,11 @@ extern "C" { #define AHB_DMA_WEIGHT_EN_TX_S 0 /** AHB_DMA_WEIGHT_EN_RX_REG register - * RX weight arbitration enable register + * Reserved */ #define AHB_DMA_WEIGHT_EN_RX_REG (DR_REG_AHB_DMA_BASE + 0x3d8) /** AHB_DMA_WEIGHT_EN_RX : R/W; bitpos: [0]; default: 0; - * Configures whether to enable weight arbitration for RX. - * 0: Disable - * 1: Enable + * Reserved. */ #define AHB_DMA_WEIGHT_EN_RX (BIT(0)) #define AHB_DMA_WEIGHT_EN_RX_M (AHB_DMA_WEIGHT_EN_RX_V << AHB_DMA_WEIGHT_EN_RX_S) @@ -2593,19 +2590,20 @@ extern "C" { #define AHB_DMA_WEIGHT_EN_RX_S 0 /** AHB_DMA_ARB_TIMEOUT_REG register - * TX arbitration timeout configuration register + * Weight arbitration timeout configuration register */ #define AHB_DMA_ARB_TIMEOUT_REG (DR_REG_AHB_DMA_BASE + 0x3dc) -/** AHB_DMA_ARB_TIMEOUT_NUM : R/W; bitpos: [15:0]; default: 0; - * Configures the time slot. Measurement unit: AHB bus clock cycle. +/** AHB_DMA_ARB_TIMEOUT : R/W; bitpos: [15:0]; default: 0; + * Configures the time slot for weight arbitration. Measurement unit: AHB bus clock + * cycle. */ -#define AHB_DMA_ARB_TIMEOUT_NUM 0x0000FFFFU -#define AHB_DMA_ARB_TIMEOUT_NUM_M (AHB_DMA_ARB_TIMEOUT_NUM_V << AHB_DMA_ARB_TIMEOUT_NUM_S) -#define AHB_DMA_ARB_TIMEOUT_NUM_V 0x0000FFFFU -#define AHB_DMA_ARB_TIMEOUT_NUM_S 0 +#define AHB_DMA_ARB_TIMEOUT 0x0000FFFFU +#define AHB_DMA_ARB_TIMEOUT_M (AHB_DMA_ARB_TIMEOUT_V << AHB_DMA_ARB_TIMEOUT_S) +#define AHB_DMA_ARB_TIMEOUT_V 0x0000FFFFU +#define AHB_DMA_ARB_TIMEOUT_S 0 /** AHB_DMA_WEIGHT_EN_REG register - * TX weight arbitration enable register + * Weight arbitration enable register */ #define AHB_DMA_WEIGHT_EN_REG (DR_REG_AHB_DMA_BASE + 0x400) /** AHB_DMA_WEIGHT_EN : R/W; bitpos: [0]; default: 0; @@ -2619,67 +2617,77 @@ extern "C" { #define AHB_DMA_WEIGHT_EN_S 0 /** AHB_DMA_MODULE_CLK_EN_REG register - * Module clock force on register + * Force clock enable register for all internal GDMA modules */ #define AHB_DMA_MODULE_CLK_EN_REG (DR_REG_AHB_DMA_BASE + 0x404) /** AHB_DMA_AHB_APB_SYNC_CLK_EN : R/W; bitpos: [1:0]; default: 3; - * Configures whether to force on ahb_apb_sync 1~0 module clock. For bit n: - * 0 : Not force on ahb_apb_sync n clock - * 1 : Force on ahb_apb_sync n clock + * Configures whether to force enable the clock for the GDMA register configuration + * synchronization module. + * Bit 0 corresponds to TX and RX channel 0, bit 1 corresponds to TX and RX channel 1, + * and so on. + * 0: Not forced to enable + * 1: Forced to enable */ #define AHB_DMA_AHB_APB_SYNC_CLK_EN 0x00000003U #define AHB_DMA_AHB_APB_SYNC_CLK_EN_M (AHB_DMA_AHB_APB_SYNC_CLK_EN_V << AHB_DMA_AHB_APB_SYNC_CLK_EN_S) #define AHB_DMA_AHB_APB_SYNC_CLK_EN_V 0x00000003U #define AHB_DMA_AHB_APB_SYNC_CLK_EN_S 0 /** AHB_DMA_OUT_DSCR_CLK_EN : R/W; bitpos: [3:2]; default: 7; - * Configures whether to force on out_dscr 1~0 module clock. For bit n: - * 0 : Not force on out_dscr n clock - * 1 : Force on out_dscr n clock + * Configures whether to force enable the clock for the GDMA TX descriptor processing + * module. + * Bit 0 corresponds to TX channel 0, bit 1 corresponds to TX channel 1, and so on. + * 0: Not forced to enable + * 1: Forced to enable */ #define AHB_DMA_OUT_DSCR_CLK_EN 0x00000003U #define AHB_DMA_OUT_DSCR_CLK_EN_M (AHB_DMA_OUT_DSCR_CLK_EN_V << AHB_DMA_OUT_DSCR_CLK_EN_S) #define AHB_DMA_OUT_DSCR_CLK_EN_V 0x00000003U #define AHB_DMA_OUT_DSCR_CLK_EN_S 2 /** AHB_DMA_OUT_CTRL_CLK_EN : R/W; bitpos: [5:4]; default: 7; - * Configures whether to force on out_ctrl 1~0 module clock. For bit n: - * 0 : Not force on out_ctrl n clock - * 1 : Force on out_ctrl n clock + * Configures whether to force enable the clock for the GDMA TX data processing module. + * Bit 0 corresponds to TX channel 0, bit 1 corresponds to TX channel 1, and so on. + * 0: Not forced to enable + * 1: Forced to enable */ #define AHB_DMA_OUT_CTRL_CLK_EN 0x00000003U #define AHB_DMA_OUT_CTRL_CLK_EN_M (AHB_DMA_OUT_CTRL_CLK_EN_V << AHB_DMA_OUT_CTRL_CLK_EN_S) #define AHB_DMA_OUT_CTRL_CLK_EN_V 0x00000003U #define AHB_DMA_OUT_CTRL_CLK_EN_S 4 /** AHB_DMA_IN_DSCR_CLK_EN : R/W; bitpos: [7:6]; default: 7; - * Configures whether to force on in_dscr 1~0 module clock. For bit n: - * 0 : Not force on in_dscr n clock - * 1 : Force on in_dscr n clock + * Configures whether to force enable the clock for the GDMA RX descriptor processing + * module. + * Bit 0 corresponds to RX channel 0, bit 1 corresponds to RX channel 1, and so on. + * 0: Not forced to enable + * 1: Forced to enable */ #define AHB_DMA_IN_DSCR_CLK_EN 0x00000003U #define AHB_DMA_IN_DSCR_CLK_EN_M (AHB_DMA_IN_DSCR_CLK_EN_V << AHB_DMA_IN_DSCR_CLK_EN_S) #define AHB_DMA_IN_DSCR_CLK_EN_V 0x00000003U #define AHB_DMA_IN_DSCR_CLK_EN_S 6 /** AHB_DMA_IN_CTRL_CLK_EN : R/W; bitpos: [9:8]; default: 7; - * Configures whether to force on in_ctrl 1~0 module clock. For bit n: - * 0 : Not force on in_ctrl n clock - * 1 : Force on in_ctrl n clock + * Configures whether to force enable the clock for the GDMA RX data processing module. + * Bit 0 corresponds to RX channel 0, bit 1 corresponds to RX channel 1, and so on. + * 0: Not forced to enable + * 1: Forced to enable */ #define AHB_DMA_IN_CTRL_CLK_EN 0x00000003U #define AHB_DMA_IN_CTRL_CLK_EN_M (AHB_DMA_IN_CTRL_CLK_EN_V << AHB_DMA_IN_CTRL_CLK_EN_S) #define AHB_DMA_IN_CTRL_CLK_EN_V 0x00000003U #define AHB_DMA_IN_CTRL_CLK_EN_S 8 /** AHB_DMA_CMD_ARB_CLK_EN : R/W; bitpos: [27]; default: 0; - * Configures whether to force on cmd_arb module clock. - * 0 : Not force on cmd_arb clock - * 1 : Force on cmd_arb clock + * Configures whether to force enable the clock for the GDMA arbiter module. + * 0: Not forced to enable + * 1: Forced to enable */ #define AHB_DMA_CMD_ARB_CLK_EN (BIT(27)) #define AHB_DMA_CMD_ARB_CLK_EN_M (AHB_DMA_CMD_ARB_CLK_EN_V << AHB_DMA_CMD_ARB_CLK_EN_S) #define AHB_DMA_CMD_ARB_CLK_EN_V 0x00000001U #define AHB_DMA_CMD_ARB_CLK_EN_S 27 /** AHB_DMA_AHBINF_CLK_EN : R/W; bitpos: [28]; default: 0; - * Configures whether to force on ahbinf module clock. - * 0 : Not force on ahbinf clock - * 1 : Force on ahbinf clock + * Configures whether to force enable the clock for the GDMA bus interface processing + * module. + * 0: Not forced to enable + * 1: Forced to enable */ #define AHB_DMA_AHBINF_CLK_EN (BIT(28)) #define AHB_DMA_AHBINF_CLK_EN_M (AHB_DMA_AHBINF_CLK_EN_V << AHB_DMA_AHBINF_CLK_EN_S) @@ -2687,11 +2695,12 @@ extern "C" { #define AHB_DMA_AHBINF_CLK_EN_S 28 /** AHB_DMA_AHBINF_RESP_ERR_STATUS0_REG register - * AHB response error status 0 register + * AHB bus error response status register 0 */ #define AHB_DMA_AHBINF_RESP_ERR_STATUS0_REG (DR_REG_AHB_DMA_BASE + 0x408) /** AHB_DMA_AHBINF_RESP_ERR_ADDR : RO; bitpos: [31:0]; default: 0; - * Represents the address of the AHB response error. + * Represents the address of the current AHB bus transfer that triggers an error + * response. */ #define AHB_DMA_AHBINF_RESP_ERR_ADDR 0xFFFFFFFFU #define AHB_DMA_AHBINF_RESP_ERR_ADDR_M (AHB_DMA_AHBINF_RESP_ERR_ADDR_V << AHB_DMA_AHBINF_RESP_ERR_ADDR_S) @@ -2699,26 +2708,48 @@ extern "C" { #define AHB_DMA_AHBINF_RESP_ERR_ADDR_S 0 /** AHB_DMA_AHBINF_RESP_ERR_STATUS1_REG register - * AHB response error status 1 register + * AHB bus error response status register 1 */ #define AHB_DMA_AHBINF_RESP_ERR_STATUS1_REG (DR_REG_AHB_DMA_BASE + 0x40c) /** AHB_DMA_AHBINF_RESP_ERR_WR : RO; bitpos: [0]; default: 0; - * Represents the AHB response error is write request. + * Represents the type of the transfer that triggered the AHB bus error response + * received by the GDMA. + * 0: Read + * 1: Write */ #define AHB_DMA_AHBINF_RESP_ERR_WR (BIT(0)) #define AHB_DMA_AHBINF_RESP_ERR_WR_M (AHB_DMA_AHBINF_RESP_ERR_WR_V << AHB_DMA_AHBINF_RESP_ERR_WR_S) #define AHB_DMA_AHBINF_RESP_ERR_WR_V 0x00000001U #define AHB_DMA_AHBINF_RESP_ERR_WR_S 0 /** AHB_DMA_AHBINF_RESP_ERR_ID : RO; bitpos: [4:1]; default: 15; - * Represents the AHB response error request id. + * Represents the ID of the transfer that triggers the AHB bus error response. + * 0: Reserved + * 1: Transfer between GP-SPI2 and memory + * 2: Reserved + * 3: Reserved + * 4: Transfer between Audio Sample Rate Converter and memory + * 5: Reserved + * 6: Reserved + * 7: Transfer between SHA and memory + * 8: Transfer between ADC and memory + * 9: Reserved + * 10: Memory-to-memory transfer on channel 0 + * 11: Memory-to-memory transfer on channel 1 + * 12: Reserved + * 13: Reserved + * 14: Reserved + * 15: Invalid */ #define AHB_DMA_AHBINF_RESP_ERR_ID 0x0000000FU #define AHB_DMA_AHBINF_RESP_ERR_ID_M (AHB_DMA_AHBINF_RESP_ERR_ID_V << AHB_DMA_AHBINF_RESP_ERR_ID_S) #define AHB_DMA_AHBINF_RESP_ERR_ID_V 0x0000000FU #define AHB_DMA_AHBINF_RESP_ERR_ID_S 1 /** AHB_DMA_AHBINF_RESP_ERR_CH_ID : RO; bitpos: [6:5]; default: 0; - * Represents the AHB response error request channel id.bit[1]=1:TX channel. - * bit[1]=0:RX channel. + * Represents the channel ID of the transfer that triggers the AHB bus error response. + * Bit[0]: Channel number. Value range: 0 ~ 1 + * Bit[1]: Channel direction. + * 0: RX + * 1: TX */ #define AHB_DMA_AHBINF_RESP_ERR_CH_ID 0x00000003U #define AHB_DMA_AHBINF_RESP_ERR_CH_ID_M (AHB_DMA_AHBINF_RESP_ERR_CH_ID_V << AHB_DMA_AHBINF_RESP_ERR_CH_ID_S) diff --git a/components/soc/esp32c61/register/soc/ahb_dma_struct.h b/components/soc/esp32c61/register/soc/ahb_dma_struct.h index 6ffda86b1e5..16c93bdfe62 100644 --- a/components/soc/esp32c61/register/soc/ahb_dma_struct.h +++ b/components/soc/esp32c61/register/soc/ahb_dma_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -333,25 +333,6 @@ typedef union { uint32_t val; } ahb_dma_out_int_clr_chn_reg_t; -/** Type of ahb_test register - * only for test - */ -typedef union { - struct { - /** ahb_testmode : R/W; bitpos: [2:0]; default: 0; - * reserved - */ - uint32_t ahb_testmode:3; - uint32_t reserved_3:1; - /** ahb_testaddr : R/W; bitpos: [5:4]; default: 0; - * reserved - */ - uint32_t ahb_testaddr:2; - uint32_t reserved_6:26; - }; - uint32_t val; -} ahb_dma_ahb_test_reg_t; - /** Type of misc_conf register * reserved */ @@ -430,7 +411,6 @@ typedef union { * 2'b00: single * 2'b01: incr4 * 2'b10: incr8 - * 2'b11: incr16 */ uint32_t in_data_burst_mode_sel_chn:2; uint32_t reserved_8:24; @@ -758,7 +738,6 @@ typedef union { * 2'b00: single * 2'b01: incr4 * 2'b10: incr8 - * 2'b11: incr16 */ uint32_t out_data_burst_mode_sel_chn:2; uint32_t reserved_10:22; @@ -1070,7 +1049,8 @@ typedef union { typedef union { struct { /** tx_arb_weight_opt_dis_chn : R/W; bitpos: [0]; default: 0; - * reserved + * 0: Enable + * 1: Disable */ uint32_t tx_arb_weight_opt_dis_chn:1; uint32_t reserved_1:31; @@ -1098,7 +1078,8 @@ typedef union { typedef union { struct { /** rx_arb_weight_opt_dis_chn : R/W; bitpos: [0]; default: 0; - * reserved + * 0: Enable + * 1: Disable */ uint32_t rx_arb_weight_opt_dis_chn:1; uint32_t reserved_1:31; @@ -1413,8 +1394,7 @@ typedef struct { volatile ahb_dma_in_int_chn_reg_t in_intr[2]; uint32_t reserved_020[4]; volatile ahb_dma_out_int_chn_reg_t out_intr[2]; - uint32_t reserved_050[4]; - volatile ahb_dma_ahb_test_reg_t ahb_test; + uint32_t reserved_050[5]; volatile ahb_dma_misc_conf_reg_t misc_conf; volatile ahb_dma_date_reg_t date; uint32_t reserved_06c;