mirror of
https://github.com/espressif/esp-idf.git
synced 2026-10-03 03:31:41 +03:00
refactor(esp_hw_support): refactor sleep clock, split it to support multiple targets
This commit is contained in:
Lou Tianhao
@@ -6,9 +6,9 @@ set(srcs)
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if(CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP OR
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(CONFIG_SOC_CPU_IN_TOP_DOMAIN AND CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP))
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list(APPEND srcs "cpu_retention/port/${target}/sleep_cpu.c")
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list(APPEND srcs "port/${target}/sleep_cpu.c")
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if(CONFIG_SOC_PM_CPU_RETENTION_BY_SW)
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list(APPEND srcs "cpu_retention/port/${target}/sleep_cpu_asm.S")
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list(APPEND srcs "port/${target}/sleep_cpu_asm.S")
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set_property(TARGET ${COMPONENT_LIB}
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APPEND PROPERTY INTERFACE_LINK_LIBRARIES "-u rv_core_critical_regs_save")
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set_property(TARGET ${COMPONENT_LIB}
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@@ -17,7 +17,11 @@ if(CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP OR
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endif()
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if(CONFIG_SOC_PM_MMU_TABLE_RETENTION_WHEN_TOP_PD AND CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP)
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list(APPEND srcs "cpu_retention/port/${target}/sleep_mmu.c")
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list(APPEND srcs "port/${target}/sleep_mmu.c")
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endif()
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if((CONFIG_SOC_PM_SUPPORT_MODEM_PD OR CONFIG_SOC_PM_SUPPORT_TOP_PD) AND CONFIG_SOC_PAU_SUPPORTED)
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list(APPEND srcs "port/${target}/sleep_clock.c")
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endif()
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add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}")
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+1
-1
@@ -86,7 +86,7 @@ STRUCT_BEGIN
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STRUCT_FIELD (long, 4, RV_SLP_CTX_PMUFUNC, pmufunc) /* A field is used to identify whether it is going
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* to sleep or has just been awakened. We use the
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* lowest 2 bits as indication infomation, 3 means
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* lowest 2 bits as indication information, 3 means
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* being awakened, 1 means going to sleep */
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#if CONFIG_PM_CHECK_SLEEP_RETENTION_FRAME
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STRUCT_FIELD (long, 4, RV_SLP_CSF_CTX_CRC, frame_crc) /* Used to check RvCoreCriticalSleepFrame integrity */
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@@ -0,0 +1,97 @@
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/*
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* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "esp_private/sleep_clock.h"
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#include "soc/pcr_reg.h"
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#include "modem/modem_syscon_reg.h"
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static const char *TAG = "sleep_clock";
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esp_err_t sleep_clock_system_retention_init(void *arg)
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{
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#define N_REGS_PCR() (((PCR_SRAM_POWER_CONF_REG - DR_REG_PCR_BASE) / 4) + 1)
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const static sleep_retention_entries_config_t pcr_regs_retention[] = {
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[0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(0), DR_REG_PCR_BASE, DR_REG_PCR_BASE, N_REGS_PCR(), 0, 0), .owner = ENTRY(0) | ENTRY(2) } /* pcr */
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};
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esp_err_t err = sleep_retention_entries_create(pcr_regs_retention, ARRAY_SIZE(pcr_regs_retention), REGDMA_LINK_PRI_SYS_CLK, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);
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ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for system (PCR) retention");
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ESP_LOGI(TAG, "System Power, Clock and Reset sleep retention initialization");
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return ESP_OK;
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#undef N_REGS_PCR
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}
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#if CONFIG_MAC_BB_PD || CONFIG_BT_LE_SLEEP_ENABLE || CONFIG_IEEE802154_SLEEP_ENABLE
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esp_err_t sleep_clock_modem_retention_init(void *arg)
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{
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#define N_REGS_SYSCON() (((MODEM_SYSCON_MEM_CONF_REG - MODEM_SYSCON_TEST_CONF_REG) / 4) + 1)
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const static sleep_retention_entries_config_t modem_regs_retention[] = {
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[0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEMSYSCON_LINK(0), MODEM_SYSCON_TEST_CONF_REG, MODEM_SYSCON_TEST_CONF_REG, N_REGS_SYSCON(), 0, 0), .owner = ENTRY(0) | ENTRY(1) }, /* MODEM SYSCON */
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};
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esp_err_t err = sleep_retention_entries_create(modem_regs_retention, ARRAY_SIZE(modem_regs_retention), REGDMA_LINK_PRI_MODEM_CLK, SLEEP_RETENTION_MODULE_CLOCK_MODEM);
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ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for modem (SYSCON) retention, 1 level priority");
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ESP_LOGI(TAG, "Modem Power, Clock and Reset sleep retention initialization");
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return ESP_OK;
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#undef N_REGS_SYSCON
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}
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#endif
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bool clock_domain_pd_allowed(void)
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{
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const uint32_t inited_modules = sleep_retention_get_inited_modules();
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const uint32_t created_modules = sleep_retention_get_created_modules();
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const uint32_t sys_clk_dep_modules = (const uint32_t) (BIT(SLEEP_RETENTION_MODULE_SYS_PERIPH));
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/* The clock and reset of MODEM (WiFi, BLE and 15.4) modules are managed
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* through MODEM_SYSCON, when one or more MODEMs are initialized, it is
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* necessary to check the state of CLOCK_MODEM to determine MODEM domain on
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* or off. The clock and reset of digital peripherals are managed through
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* PCR, with TOP domain similar to MODEM domain. */
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uint32_t modem_clk_dep_modules = 0;
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#if SOC_WIFI_SUPPORTED
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modem_clk_dep_modules |= BIT(SLEEP_RETENTION_MODULE_WIFI_MAC) | BIT(SLEEP_RETENTION_MODULE_WIFI_BB);
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#endif
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#if SOC_BT_SUPPORTED
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modem_clk_dep_modules |= BIT(SLEEP_RETENTION_MODULE_BLE_MAC) | BIT(SLEEP_RETENTION_MODULE_BT_BB);
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#endif
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#if SOC_IEEE802154_SUPPORTED
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modem_clk_dep_modules |= BIT(SLEEP_RETENTION_MODULE_802154_MAC) | BIT(SLEEP_RETENTION_MODULE_BT_BB);
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#endif
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uint32_t mask = 0;
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if (inited_modules & sys_clk_dep_modules) {
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mask |= BIT(SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);
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}
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if (inited_modules & modem_clk_dep_modules) {
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#if SOC_WIFI_SUPPORTED || SOC_BT_SUPPORTED || SOC_IEEE802154_SUPPORTED
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mask |= BIT(SLEEP_RETENTION_MODULE_CLOCK_MODEM);
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#endif
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}
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return ((inited_modules & mask) == (created_modules & mask));
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}
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ESP_SYSTEM_INIT_FN(sleep_clock_startup_init, SECONDARY, BIT(0), 106)
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{
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sleep_retention_module_init_param_t init_param = {
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.cbs = { .create = { .handle = sleep_clock_system_retention_init, .arg = NULL } },
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.attribute = SLEEP_RETENTION_MODULE_ATTR_PASSIVE
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};
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sleep_retention_module_init(SLEEP_RETENTION_MODULE_CLOCK_SYSTEM, &init_param);
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#if CONFIG_MAC_BB_PD || CONFIG_BT_LE_SLEEP_ENABLE || CONFIG_IEEE802154_SLEEP_ENABLE
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init_param = (sleep_retention_module_init_param_t) {
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.cbs = { .create = { .handle = sleep_clock_modem_retention_init, .arg = NULL } },
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.attribute = SLEEP_RETENTION_MODULE_ATTR_PASSIVE
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};
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sleep_retention_module_init(SLEEP_RETENTION_MODULE_CLOCK_MODEM, &init_param);
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#endif
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return ESP_OK;
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}
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+1
-1
@@ -86,7 +86,7 @@ STRUCT_BEGIN
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STRUCT_FIELD (long, 4, RV_SLP_CTX_PMUFUNC, pmufunc) /* A field is used to identify whether it is going
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* to sleep or has just been awakened. We use the
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* lowest 2 bits as indication infomation, 3 means
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* lowest 2 bits as indication information, 3 means
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* being awakened, 1 means going to sleep */
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#if CONFIG_PM_CHECK_SLEEP_RETENTION_FRAME
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STRUCT_FIELD (long, 4, RV_SLP_CSF_CTX_CRC, frame_crc) /* Used to check RvCoreCriticalSleepFrame integrity */
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@@ -0,0 +1,101 @@
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/*
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* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "esp_private/sleep_clock.h"
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#include "soc/pcr_reg.h"
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#include "modem/modem_syscon_reg.h"
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#include "modem/modem_lpcon_reg.h"
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static const char *TAG = "sleep_clock";
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esp_err_t sleep_clock_system_retention_init(void *arg)
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{
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#define N_REGS_PCR() (((PCR_PWDET_SAR_CLK_CONF_REG - DR_REG_PCR_BASE) / 4) + 1)
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const static sleep_retention_entries_config_t pcr_regs_retention[] = {
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[0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(0), DR_REG_PCR_BASE, DR_REG_PCR_BASE, N_REGS_PCR(), 0, 0), .owner = ENTRY(0) | ENTRY(2) } /* pcr */
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};
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esp_err_t err = sleep_retention_entries_create(pcr_regs_retention, ARRAY_SIZE(pcr_regs_retention), REGDMA_LINK_PRI_SYS_CLK, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);
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ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for system (PCR) retention");
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ESP_LOGI(TAG, "System Power, Clock and Reset sleep retention initialization");
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return ESP_OK;
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#undef N_REGS_PCR
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}
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#if CONFIG_MAC_BB_PD || CONFIG_BT_LE_SLEEP_ENABLE || CONFIG_IEEE802154_SLEEP_ENABLE
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esp_err_t sleep_clock_modem_retention_init(void *arg)
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{
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#define N_REGS_SYSCON() (((MODEM_SYSCON_MEM_CONF_REG - MODEM_SYSCON_TEST_CONF_REG) / 4) + 1)
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#define N_REGS_LPCON() (((MODEM_LPCON_MEM_CONF_REG - MODEM_LPCON_TEST_CONF_REG) / 4) + 1)
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const static sleep_retention_entries_config_t modem_regs_retention[] = {
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[0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEMSYSCON_LINK(0), MODEM_SYSCON_TEST_CONF_REG, MODEM_SYSCON_TEST_CONF_REG, N_REGS_SYSCON(), 0, 0), .owner = ENTRY(0) | ENTRY(1) }, /* MODEM SYSCON */
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#if SOC_PM_RETENTION_SW_TRIGGER_REGDMA
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[1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEMLPCON_LINK(0), MODEM_LPCON_TEST_CONF_REG, MODEM_LPCON_TEST_CONF_REG, N_REGS_LPCON(), 0, 0), .owner = ENTRY(0) | ENTRY(1) } /* MODEM LPCON */
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#endif
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};
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esp_err_t err = sleep_retention_entries_create(modem_regs_retention, ARRAY_SIZE(modem_regs_retention), REGDMA_LINK_PRI_MODEM_CLK, SLEEP_RETENTION_MODULE_CLOCK_MODEM);
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ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for modem (SYSCON) retention, 1 level priority");
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ESP_LOGI(TAG, "Modem Power, Clock and Reset sleep retention initialization");
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return ESP_OK;
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#undef N_REGS_LPCON
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#undef N_REGS_SYSCON
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}
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#endif
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bool clock_domain_pd_allowed(void)
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{
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const uint32_t inited_modules = sleep_retention_get_inited_modules();
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const uint32_t created_modules = sleep_retention_get_created_modules();
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const uint32_t sys_clk_dep_modules = (const uint32_t) (BIT(SLEEP_RETENTION_MODULE_SYS_PERIPH));
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/* The clock and reset of MODEM (WiFi, BLE and 15.4) modules are managed
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* through MODEM_SYSCON, when one or more MODEMs are initialized, it is
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* necessary to check the state of CLOCK_MODEM to determine MODEM domain on
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* or off. The clock and reset of digital peripherals are managed through
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* PCR, with TOP domain similar to MODEM domain. */
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uint32_t modem_clk_dep_modules = 0;
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#if SOC_BT_SUPPORTED
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modem_clk_dep_modules |= BIT(SLEEP_RETENTION_MODULE_BLE_MAC) | BIT(SLEEP_RETENTION_MODULE_BT_BB);
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#endif
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#if SOC_IEEE802154_SUPPORTED
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modem_clk_dep_modules |= BIT(SLEEP_RETENTION_MODULE_802154_MAC) | BIT(SLEEP_RETENTION_MODULE_BT_BB);
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#endif
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uint32_t mask = 0;
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if (inited_modules & sys_clk_dep_modules) {
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mask |= BIT(SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);
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}
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if (inited_modules & modem_clk_dep_modules) {
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#if SOC_BT_SUPPORTED || SOC_IEEE802154_SUPPORTED
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mask |= BIT(SLEEP_RETENTION_MODULE_CLOCK_MODEM);
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#endif
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}
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return ((inited_modules & mask) == (created_modules & mask));
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}
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ESP_SYSTEM_INIT_FN(sleep_clock_startup_init, SECONDARY, BIT(0), 106)
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{
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sleep_retention_module_init_param_t init_param = {
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.cbs = { .create = { .handle = sleep_clock_system_retention_init, .arg = NULL } },
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.attribute = SLEEP_RETENTION_MODULE_ATTR_PASSIVE
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};
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sleep_retention_module_init(SLEEP_RETENTION_MODULE_CLOCK_SYSTEM, &init_param);
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#if CONFIG_MAC_BB_PD || CONFIG_BT_LE_SLEEP_ENABLE || CONFIG_IEEE802154_SLEEP_ENABLE
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init_param = (sleep_retention_module_init_param_t) {
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.cbs = { .create = { .handle = sleep_clock_modem_retention_init, .arg = NULL } },
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.attribute = SLEEP_RETENTION_MODULE_ATTR_PASSIVE
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};
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sleep_retention_module_init(SLEEP_RETENTION_MODULE_CLOCK_MODEM, &init_param);
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#endif
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return ESP_OK;
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}
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+1
-1
@@ -87,7 +87,7 @@ STRUCT_BEGIN
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STRUCT_FIELD (long, 4, RV_SLP_CTX_PMUFUNC, pmufunc) /* A field is used to identify whether it is going
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* to sleep or has just been awakened. We use the
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* lowest 2 bits as indication infomation, 3 means
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* lowest 2 bits as indication information, 3 means
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* being awakened, 1 means going to sleep */
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#if CONFIG_PM_CHECK_SLEEP_RETENTION_FRAME
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STRUCT_FIELD (long, 4, RV_SLP_CSF_CTX_CRC, frame_crc) /* Used to check RvCoreCriticalSleepFrame integrity */
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@@ -0,0 +1,53 @@
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/*
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* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "esp_private/sleep_clock.h"
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#include "soc/hp_sys_clkrst_reg.h"
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static const char *TAG = "sleep_clock";
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esp_err_t sleep_clock_system_retention_init(void *arg)
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{
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#define N_REGS_PCR() (((HP_SYS_CLKRST_HPCORE_WDT_RESET_SOURCE0_REG - DR_REG_HP_SYS_CLKRST_BASE) / 4) + 1)
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const static sleep_retention_entries_config_t pcr_regs_retention[] = {
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[0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(0x0), DR_REG_HP_SYS_CLKRST_BASE, DR_REG_HP_SYS_CLKRST_BASE, N_REGS_PCR(), 0, 0), .owner = ENTRY(0) }, /* pcr */
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[1] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(0x01), HP_SYS_CLKRST_ROOT_CLK_CTRL0_REG, HP_SYS_CLKRST_REG_SOC_CLK_DIV_UPDATE, HP_SYS_CLKRST_REG_SOC_CLK_DIV_UPDATE_M, 1, 0), .owner = ENTRY(0) },
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[2] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(0x02), HP_SYS_CLKRST_ROOT_CLK_CTRL0_REG, 0x0, HP_SYS_CLKRST_REG_SOC_CLK_DIV_UPDATE_M, 1, 0), .owner = ENTRY(0) },
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[3] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(0x03), HP_SYS_CLKRST_PERI_CLK_CTRL02_REG, HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE, HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE_M, 1, 0), .owner = ENTRY(0) },
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[4] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(0x04), HP_SYS_CLKRST_PERI_CLK_CTRL02_REG, 0x0, HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE_M, 1, 0), .owner = ENTRY(0) },
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};
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esp_err_t err = sleep_retention_entries_create(pcr_regs_retention, ARRAY_SIZE(pcr_regs_retention), REGDMA_LINK_PRI_SYS_CLK, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);
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ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for system (PCR) retention");
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ESP_LOGI(TAG, "System Power, Clock and Reset sleep retention initialization");
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return ESP_OK;
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#undef N_REGS_PCR
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}
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bool clock_domain_pd_allowed(void)
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{
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const uint32_t inited_modules = sleep_retention_get_inited_modules();
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const uint32_t created_modules = sleep_retention_get_created_modules();
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const uint32_t sys_clk_dep_modules = (const uint32_t) (BIT(SLEEP_RETENTION_MODULE_SYS_PERIPH));
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uint32_t mask = 0;
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if (inited_modules & sys_clk_dep_modules) {
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mask |= BIT(SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);
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}
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return ((inited_modules & mask) == (created_modules & mask));
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}
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ESP_SYSTEM_INIT_FN(sleep_clock_startup_init, SECONDARY, BIT(0), 106)
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{
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sleep_retention_module_init_param_t init_param = {
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.cbs = { .create = { .handle = sleep_clock_system_retention_init, .arg = NULL } },
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.attribute = SLEEP_RETENTION_MODULE_ATTR_PASSIVE
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};
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sleep_retention_module_init(SLEEP_RETENTION_MODULE_CLOCK_SYSTEM, &init_param);
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return ESP_OK;
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}
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