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Merge branch 'bugfix/fix_external_coexistence_depends_on_wifi_connect_issue_v6.0' into 'release/v6.0'

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Bugfix/fix external coexistence depends on wifi connect issue v6.0(Backport v6.0)

See merge request espressif/esp-idf!46313
This commit is contained in:
Jiang Jiang Jian
2026-03-20 10:15:39 +08:00
parent dfee985a92 7be45fc569
commit d65170e2fb
19 changed files with 291 additions and 29 deletions
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components/esp_hw_support/include/esp_private/periph_ctrl.h
+19
View File
@@ -174,6 +174,25 @@ void phy_module_disable(void);
*/
bool phy_module_has_clock_bits(uint32_t mask);
/**
* @brief Enable coex module
*
* @note Calling this function will only enable coex module.
* @note For ESP32S2, ESP32S3, and ESP32C3, this function has no effect because
* the coex module clock is controlled by the modem clock. On these chips,
* you must call esp_wifi_init() to enable the modem clock before using
* external coexistence features.
*/
void coex_module_enable(void);
/**
* @brief Disable coex module
*
* @note Calling this function will only disable coex module.
* @note For ESP32S2, ESP32S3, and ESP32C3, this function has no effect because
* the coex module clock is controlled by the modem clock.
*/
void coex_module_disable(void);
#undef __PERIPH_CTRL_DEPRECATE_ATTR
#ifdef __cplusplus
components/esp_hw_support/periph_ctrl.c
+44
View File
@@ -105,6 +105,12 @@ IRAM_ATTR void wifi_bt_common_module_enable(void)
periph_ll_wifi_bt_module_enable_clk();
}
ref_counts[PERIPH_WIFI_BT_COMMON_MODULE]++;
#if CONFIG_IDF_TARGET_ESP32C2
if (ref_counts[PERIPH_COEX_MODULE] == 0) {
periph_ll_coex_module_enable_clk_clear_rst();
}
ref_counts[PERIPH_COEX_MODULE]++;
#endif
esp_os_exit_critical_safe(&periph_spinlock);
#endif
}
@@ -119,6 +125,12 @@ IRAM_ATTR void wifi_bt_common_module_disable(void)
if (ref_counts[PERIPH_WIFI_BT_COMMON_MODULE] == 0) {
periph_ll_wifi_bt_module_disable_clk();
}
#if CONFIG_IDF_TARGET_ESP32C2
ref_counts[PERIPH_COEX_MODULE]--;
if (ref_counts[PERIPH_COEX_MODULE] == 0) {
periph_ll_coex_module_disable_clk_set_rst();
}
#endif
esp_os_exit_critical_safe(&periph_spinlock);
#endif
}
@@ -231,4 +243,36 @@ IRAM_ATTR bool phy_module_has_clock_bits(uint32_t mask)
}
return true;
}
IRAM_ATTR void coex_module_enable(void)
{
#if SOC_MODEM_CLOCK_IS_INDEPENDENT
modem_clock_module_enable(PERIPH_COEX_MODULE);
#else
esp_os_enter_critical_safe(&periph_spinlock);
#if CONFIG_IDF_TARGET_ESP32C2
if (ref_counts[PERIPH_COEX_MODULE] == 0) {
periph_ll_coex_module_enable_clk_clear_rst();
}
ref_counts[PERIPH_COEX_MODULE]++;
#endif
esp_os_exit_critical_safe(&periph_spinlock);
#endif
}
IRAM_ATTR void coex_module_disable(void)
{
#if SOC_MODEM_CLOCK_IS_INDEPENDENT
modem_clock_module_disable(PERIPH_COEX_MODULE);
#else
esp_os_enter_critical_safe(&periph_spinlock);
#if CONFIG_IDF_TARGET_ESP32C2
ref_counts[PERIPH_COEX_MODULE]--;
if (ref_counts[PERIPH_COEX_MODULE] == 0) {
periph_ll_coex_module_disable_clk_set_rst();
}
#endif
esp_os_exit_critical_safe(&periph_spinlock);
#endif
}
#endif //#if SOC_BT_SUPPORTED || SOC_WIFI_SUPPORTED || SOC_IEEE802154_SUPPORTED