Merge branch 'bugfix/fix_external_coexistence_depends_on_wifi_connect_issue_v6.0' into 'release/v6.0'

Bugfix/fix external coexistence depends on wifi connect issue v6.0(Backport v6.0)

See merge request espressif/esp-idf!46313

components/esp_coex/src/coexist.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2018-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2018-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -18,9 +18,7 @@
 #include "esp_private/gpio.h"
 #endif
 
-#if SOC_MODEM_CLOCK_IS_INDEPENDENT
-#include "esp_private/esp_modem_clock.h"
-#endif
+#include "esp_private/periph_ctrl.h"
 
 #if CONFIG_ESP_COEX_SW_COEXIST_ENABLE && CONFIG_SOC_IEEE802154_SUPPORTED
 #include "esp_coex_i154.h"
@@ -268,16 +266,11 @@ esp_err_t esp_enable_extern_coex_gpio_pin(external_coex_wire_t wire_type, esp_ex
         return ESP_ERR_INVALID_ARG;
 #endif /* SOC_EXTERNAL_COEX_ADVANCE */
     }
-#if SOC_MODEM_CLOCK_IS_INDEPENDENT
-    modem_clock_module_enable(PERIPH_COEX_MODULE);
-#endif
+    coex_module_enable();
 #if SOC_EXTERNAL_COEX_ADVANCE
     esp_coex_external_params(g_external_coex_params, 0, 0);
 #endif
     esp_err_t ret = esp_coex_external_set(EXTERN_COEX_PTI_MID, EXTERN_COEX_PTI_MID, EXTERN_COEX_PTI_HIGH);
-#if SOC_MODEM_CLOCK_IS_INDEPENDENT
-    modem_clock_module_disable(PERIPH_COEX_MODULE);
-#endif
     if (ESP_OK != ret) {
         return ESP_FAIL;
     }
@@ -287,7 +280,7 @@ esp_err_t esp_enable_extern_coex_gpio_pin(external_coex_wire_t wire_type, esp_ex
 esp_err_t esp_disable_extern_coex_gpio_pin(void)
 {
     esp_coex_external_stop();
-
+    coex_module_disable();
     return ESP_OK;
 }
 #endif /* External Coex */

components/esp_coex/src/coexist_debug.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2018-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2018-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -19,9 +19,7 @@
 #include "soc/gpio_sig_map.h"
 #include "esp_rom_gpio.h"
 #include "soc/soc.h"
-#if SOC_MODEM_CLOCK_IS_INDEPENDENT
-#include "esp_private/esp_modem_clock.h"
-#endif
+#include "esp_private/periph_ctrl.h"
 
 #if CONFIG_ESP_COEX_GPIO_DEBUG
 static char* TAG = "coexist debug";
@@ -192,13 +190,9 @@ esp_err_t esp_coexist_debug_matrix_init(int evt, int sig, bool rev)
 
 esp_err_t esp_coexist_gpio_debug_matrix_config(int event)
 {
-#if SOC_MODEM_CLOCK_IS_INDEPENDENT
-    modem_clock_module_enable(PERIPH_COEX_MODULE);
-#endif
+    coex_module_enable();
     esp_err_t ret = coex_gpio_debug_matrix_config(event);
-#if SOC_MODEM_CLOCK_IS_INDEPENDENT
-    modem_clock_module_disable(PERIPH_COEX_MODULE);
-#endif
+    coex_module_disable();
     return ret;
 }
 
@@ -265,14 +259,10 @@ esp_err_t esp_coexist_debug_init(void)
         gpio_set_level(s_io_nums[i], false);
     }
 
-#if SOC_MODEM_CLOCK_IS_INDEPENDENT
-    modem_clock_module_enable(PERIPH_COEX_MODULE);
-#endif
+    coex_module_enable();
     /* Init coexist hardware signal */
     ESP_ERROR_CHECK(coex_gpio_debug_matrix_init());
-#if SOC_MODEM_CLOCK_IS_INDEPENDENT
-    modem_clock_module_disable(PERIPH_COEX_MODULE);
-#endif
+    coex_module_disable();
 
     return ESP_OK;
 }

components/esp_coex/test_apps/.build-test-rules.yml

@@ -0,0 +1,6 @@
+# Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps
+
+components/esp_coex/test_apps/:
+  disable:
+    - if: IDF_TARGET not in ["esp32s2", "esp32s3", "esp32c3", "esp32c2", "esp32c6", "esp32h2", "esp32c5", "esp32c61"]
+      reason: only supported with s2, s3, c3, c2, c6, h2, c5 and c61

components/esp_coex/test_apps/external_coex_function/CMakeLists.txt

@@ -0,0 +1,10 @@
+#This is the project CMakeLists.txt file for the test subproject
+cmake_minimum_required(VERSION 3.22)
+
+set(EXTRA_COMPONENT_DIRS "$ENV{IDF_PATH}/tools/test_apps/components")
+
+# "Trim" the build. Include the minimal set of components, main, and anything it depends on.
+set(COMPONENTS main)
+
+include($ENV{IDF_PATH}/tools/cmake/project.cmake)
+project(external_coex_function)

components/esp_coex/test_apps/external_coex_function/README.md

@@ -0,0 +1,3 @@
+| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S2 | ESP32-S3 |
+| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- |
+

components/esp_coex/test_apps/external_coex_function/main/CMakeLists.txt

@@ -0,0 +1,4 @@
+idf_component_register(SRC_DIRS .
+                       PRIV_INCLUDE_DIRS . ${CMAKE_CURRENT_BINARY_DIR}
+                       PRIV_REQUIRES cmock test_utils nvs_flash esp_common esp_wifi esp_event esp_coex
+                       WHOLE_ARCHIVE)

components/esp_coex/test_apps/external_coex_function/main/app_main.c

@@ -0,0 +1,48 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Unlicense OR CC0-1.0
+ */
+#include "unity.h"
+#include "nvs_flash.h"
+#include "nvs.h"
+#include "esp_err.h"
+#include "esp_netif.h"
+
+#include "esp_heap_caps.h"
+
+// Some resources are lazy allocated in wifi or event handler
+#define TEST_MEMORY_LEAK_THRESHOLD (-1536)
+
+static size_t before_free_8bit;
+static size_t before_free_32bit;
+
+static void check_leak(size_t before_free, size_t after_free, const char *type)
+{
+    ssize_t delta = after_free - before_free;
+    printf("MALLOC_CAP_%s: Before %u bytes free, After %u bytes free (delta %d)\n", type, before_free, after_free, delta);
+    TEST_ASSERT_MESSAGE(delta >= TEST_MEMORY_LEAK_THRESHOLD, "memory leak");
+}
+
+void setUp(void)
+{
+    before_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT);
+    before_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT);
+}
+
+void tearDown(void)
+{
+    size_t after_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT);
+    size_t after_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT);
+    check_leak(before_free_8bit, after_free_8bit, "8BIT");
+    check_leak(before_free_32bit, after_free_32bit, "32BIT");
+}
+
+void app_main(void)
+{
+    ESP_ERROR_CHECK(nvs_flash_init());
+    ESP_ERROR_CHECK(esp_netif_init());
+    unity_run_menu();
+    ESP_ERROR_CHECK(esp_netif_deinit());
+    ESP_ERROR_CHECK(nvs_flash_deinit());
+}

components/esp_coex/test_apps/external_coex_function/main/test_enable_extern_coex.c

@@ -0,0 +1,64 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Unlicense OR CC0-1.0
+ */
+#include "unity.h"
+#include "esp_wifi.h"
+#include "esp_coexist.h"
+#include "soc/soc_caps.h"
+#include "esp_log.h"
+#include "test_utils.h"
+#include "unity_test_utils.h"
+#include "esp_private/periph_ctrl.h"
+
+#define TAG "test_external_coex"
+#define EMPH_STR(s) "****** "s" ******"
+
+TEST_CASE("enable external coex", "[external_coex]")
+{
+#if !SOC_MODEM_CLOCK_IS_INDEPENDENT && !CONFIG_IDF_TARGET_ESP32C2
+    wifi_init_config_t cfg = WIFI_INIT_CONFIG_DEFAULT();
+    cfg.nvs_enable = false;
+    ESP_LOGI(TAG, EMPH_STR("esp_wifi_init"));
+    TEST_ESP_OK(esp_wifi_init(&cfg));
+#endif
+
+#if CONFIG_IDF_TARGET_ESP32S2
+#define EXTERNAL_COEX_CONF 0x60035118
+#define WDEV_RW_BT_COEX_EN (BIT(0))
+#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3
+#define EXTERNAL_COEX_CONF 0x60035084
+#define WDEV_RW_BT_COEX_EN (BIT(0))
+#elif CONFIG_IDF_TARGET_ESP32C2
+#define EXTERNAL_COEX_CONF 0x6004C4A0
+#define WDEV_RW_BT_COEX_EN (BIT(9))
+#elif CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32C61
+#define EXTERNAL_COEX_CONF 0x600AF4A0
+#define WDEV_RW_BT_COEX_EN (BIT(9))
+#elif CONFIG_IDF_TARGET_ESP32H2
+#define EXTERNAL_COEX_CONF 0x600AD4A0
+#define WDEV_RW_BT_COEX_EN (BIT(9))
+#endif
+
+    esp_extern_coex_work_mode_t mode = EXTERNAL_COEX_LEADER_ROLE;
+    external_coex_wire_t type = EXTERN_COEX_WIRE_3;
+    esp_external_coex_gpio_set_t gpio_pin = {.request = 0, .priority = 1, .grant = 2};
+    TEST_ESP_OK(esp_external_coex_set_work_mode(mode));
+    TEST_ESP_OK(esp_enable_extern_coex_gpio_pin(type, gpio_pin));
+
+    ESP_LOGI(TAG, "external coex config 0x%lx", REG_READ(EXTERNAL_COEX_CONF));
+    TEST_ASSERT(REG_GET_BIT(EXTERNAL_COEX_CONF, WDEV_RW_BT_COEX_EN));
+
+    TEST_ESP_OK(esp_disable_extern_coex_gpio_pin());
+    coex_module_enable();
+    TEST_ASSERT(REG_GET_BIT(EXTERNAL_COEX_CONF, WDEV_RW_BT_COEX_EN) == 0);
+    coex_module_disable();
+
+#if !SOC_MODEM_CLOCK_IS_INDEPENDENT && !CONFIG_IDF_TARGET_ESP32C2
+    ESP_LOGI(TAG, EMPH_STR("esp_wifi_deinit"));
+    TEST_ESP_OK(esp_wifi_deinit());
+#endif
+
+    ESP_LOGI(TAG, "test passed...");
+}

components/esp_coex/test_apps/external_coex_function/pytest_external_coex_function.py

@@ -0,0 +1,56 @@
+# SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
+# SPDX-License-Identifier: Unlicense OR CC0-1.0
+import pytest
+from pytest_embedded import Dut
+from pytest_embedded_idf.utils import idf_parametrize
+
+
+@pytest.mark.generic
+@idf_parametrize(
+    'target', ['esp32h2', 'esp32c3', 'esp32s2', 'esp32s3', 'esp32c6', 'esp32c61', 'esp32c5'], indirect=['target']
+)
+def test_external_coex_unit_test(dut: Dut) -> None:
+    dut.run_all_single_board_cases()
+
+
+@pytest.mark.xtal_26mhz
+@pytest.mark.generic
+@pytest.mark.parametrize(
+    'config, baud',
+    [
+        ('esp32c2_xtal26m', '74880'),
+    ],
+    indirect=True,
+)
+@idf_parametrize('target', ['esp32c2'], indirect=['target'])
+def test_external_coex_unit_test_esp32c2_xtal26m(dut: Dut) -> None:
+    dut.run_all_single_board_cases()
+
+
+@pytest.mark.esp32c2eco4
+@pytest.mark.xtal_26mhz
+@pytest.mark.generic
+@pytest.mark.parametrize(
+    'config, baud',
+    [
+        ('esp32c2eco4_xtal26m', '74880'),
+    ],
+    indirect=True,
+)
+@idf_parametrize('target', ['esp32c2'], indirect=['target'])
+def test_external_coex_unit_test_esp32c2eco4_xtal26m(dut: Dut) -> None:
+    dut.run_all_single_board_cases()
+
+
+@pytest.mark.esp32c3eco7
+@pytest.mark.generic
+@pytest.mark.parametrize(
+    'config',
+    [
+        'esp32c3eco7',
+    ],
+    indirect=True,
+)
+@idf_parametrize('target', ['esp32c3'], indirect=['target'])
+def test_external_coex_unit_test_esp32c3eco7(dut: Dut) -> None:
+    dut.run_all_single_board_cases()

components/esp_coex/test_apps/external_coex_function/sdkconfig.ci.esp32c2_xtal26m

@@ -0,0 +1,2 @@
+CONFIG_IDF_TARGET="esp32c2"
+CONFIG_XTAL_FREQ_26=y

components/esp_coex/test_apps/external_coex_function/sdkconfig.ci.esp32c2eco4_xtal26m

@@ -0,0 +1,3 @@
+CONFIG_IDF_TARGET="esp32c2"
+CONFIG_XTAL_FREQ_26=y
+CONFIG_ESP32C2_REV_MIN_200=y

components/esp_coex/test_apps/external_coex_function/sdkconfig.ci.esp32c3eco7

@@ -0,0 +1,2 @@
+CONFIG_IDF_TARGET="esp32c3"
+CONFIG_ESP32C3_REV_MIN_101=y

components/esp_coex/test_apps/external_coex_function/sdkconfig.defaults

@@ -0,0 +1,4 @@
+
+# ignore task watchdog triggered by unity_run_menu
+CONFIG_ESP_TASK_WDT_EN=n
+CONFIG_ESP_COEX_EXTERNAL_COEXIST_ENABLE=y

components/esp_hal_clock/esp32c2/include/hal/clk_gate_ll.h

@@ -142,6 +142,17 @@ static inline void periph_ll_phy_calibration_module_disable_clk_set_rst(void)
     DPORT_SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0);
 }
 
+static inline void periph_ll_coex_module_enable_clk_clear_rst(void)
+{
+    DPORT_SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_COEX_EN_M);
+    DPORT_CLEAR_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0);
+}
+
+static inline void periph_ll_coex_module_disable_clk_set_rst(void)
+{
+    DPORT_CLEAR_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_COEX_EN_M);
+    DPORT_SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0);
+}
 #ifdef __cplusplus
 }
 #endif

components/esp_hw_support/include/esp_private/periph_ctrl.h

@@ -174,6 +174,25 @@ void phy_module_disable(void);
  */
 bool phy_module_has_clock_bits(uint32_t mask);
 
+/**
+ * @brief Enable coex module
+ *
+ * @note Calling this function will only enable coex module.
+ * @note For ESP32S2, ESP32S3, and ESP32C3, this function has no effect because
+ *       the coex module clock is controlled by the modem clock. On these chips,
+ *       you must call esp_wifi_init() to enable the modem clock before using
+ *       external coexistence features.
+ */
+void coex_module_enable(void);
+
+/**
+ * @brief Disable coex module
+ *
+ * @note Calling this function will only disable coex module.
+ * @note For ESP32S2, ESP32S3, and ESP32C3, this function has no effect because
+ *       the coex module clock is controlled by the modem clock.
+ */
+void coex_module_disable(void);
 #undef __PERIPH_CTRL_DEPRECATE_ATTR
 
 #ifdef __cplusplus

components/esp_hw_support/periph_ctrl.c

@@ -105,6 +105,12 @@ IRAM_ATTR void wifi_bt_common_module_enable(void)
         periph_ll_wifi_bt_module_enable_clk();
     }
     ref_counts[PERIPH_WIFI_BT_COMMON_MODULE]++;
+#if CONFIG_IDF_TARGET_ESP32C2
+    if (ref_counts[PERIPH_COEX_MODULE] == 0) {
+        periph_ll_coex_module_enable_clk_clear_rst();
+    }
+    ref_counts[PERIPH_COEX_MODULE]++;
+#endif
     esp_os_exit_critical_safe(&periph_spinlock);
 #endif
 }
@@ -119,6 +125,12 @@ IRAM_ATTR void wifi_bt_common_module_disable(void)
     if (ref_counts[PERIPH_WIFI_BT_COMMON_MODULE] == 0) {
         periph_ll_wifi_bt_module_disable_clk();
     }
+#if CONFIG_IDF_TARGET_ESP32C2
+    ref_counts[PERIPH_COEX_MODULE]--;
+    if (ref_counts[PERIPH_COEX_MODULE] == 0) {
+        periph_ll_coex_module_disable_clk_set_rst();
+    }
+#endif
     esp_os_exit_critical_safe(&periph_spinlock);
 #endif
 }
@@ -231,4 +243,36 @@ IRAM_ATTR bool phy_module_has_clock_bits(uint32_t mask)
     }
     return true;
 }
+
+IRAM_ATTR void coex_module_enable(void)
+{
+#if SOC_MODEM_CLOCK_IS_INDEPENDENT
+    modem_clock_module_enable(PERIPH_COEX_MODULE);
+#else
+    esp_os_enter_critical_safe(&periph_spinlock);
+#if CONFIG_IDF_TARGET_ESP32C2
+    if (ref_counts[PERIPH_COEX_MODULE] == 0) {
+        periph_ll_coex_module_enable_clk_clear_rst();
+    }
+    ref_counts[PERIPH_COEX_MODULE]++;
+#endif
+    esp_os_exit_critical_safe(&periph_spinlock);
+#endif
+}
+
+IRAM_ATTR void coex_module_disable(void)
+{
+#if SOC_MODEM_CLOCK_IS_INDEPENDENT
+    modem_clock_module_disable(PERIPH_COEX_MODULE);
+#else
+    esp_os_enter_critical_safe(&periph_spinlock);
+#if CONFIG_IDF_TARGET_ESP32C2
+    ref_counts[PERIPH_COEX_MODULE]--;
+    if (ref_counts[PERIPH_COEX_MODULE] == 0) {
+        periph_ll_coex_module_disable_clk_set_rst();
+    }
+#endif
+    esp_os_exit_critical_safe(&periph_spinlock);
+#endif
+}
 #endif  //#if SOC_BT_SUPPORTED || SOC_WIFI_SUPPORTED || SOC_IEEE802154_SUPPORTED

components/soc/esp32c2/include/soc/periph_defs.h

@@ -21,6 +21,7 @@ typedef enum {
     PERIPH_WIFI_BT_COMMON_MODULE,
     PERIPH_SYSTIMER_MODULE,
     PERIPH_PHY_CALIBRATION_MODULE,
+    PERIPH_COEX_MODULE,
     PERIPH_MODULE_MAX
 } shared_periph_module_t;
 

components/soc/esp32c2/register/soc/syscon_reg.h

@@ -178,8 +178,10 @@ extern "C" {
 #define SYSTEM_WIFI_CLK_BT_EN_S  0
 /* Mask for clock bits used by both WIFI and Bluetooth, 0, 1, 2, 3, 7, 8, 9, 10, 19, 20, 21, 22, 23 */
 #define SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M 0x78078F
-/* Mask for clock bits used by phy calibration, bit 22, 29, 30, 31 */
-#define SYSTEM_WIFI_CLK_PHY_EN_M    0xE0400000
+/* Mask for clock bits used by phy calibration, bit 22, 30, 31 */
+#define SYSTEM_WIFI_CLK_PHY_EN_M    0xC0400000
+/* Mask for clock bits used by coex, bit 29 */
+#define SYSTEM_WIFI_CLK_COEX_EN_M    0x20000000
 
 /* Digital team to check */
 //bluetooth baseband bit11