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feat(esp_hw_support): support PMU clock ICG management for esp32s31
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@@ -19,6 +19,7 @@
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#include "hal/pmu_hal.h"
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#include "pmu_param.h"
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#include "pmu_bit_defs.h"
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#include "soc/pmu_icg_mapping.h"
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#endif
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#ifdef __cplusplus
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@@ -278,7 +279,7 @@ uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t sleep_flags, soc_rtc_slow_clk
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* @return hardware time overhead in us
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*/
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const pmu_sleep_config_t* pmu_sleep_config_default(pmu_sleep_config_t *config, uint32_t sleep_flags, uint32_t clk_flags, uint32_t adjustment, soc_rtc_slow_clk_src_t slowclk_src, uint32_t slowclk_period, uint32_t fastclk_period, bool dslp);
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const pmu_sleep_config_t* pmu_sleep_config_default(pmu_sleep_config_t *config, uint32_t sleep_flags, pmu_sleep_clk_icg_flags_t clk_flags, uint32_t adjustment, soc_rtc_slow_clk_src_t slowclk_src, uint32_t slowclk_period, uint32_t fastclk_period, bool dslp);
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/**
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* @brief Prepare the chip to enter sleep mode
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@@ -8,6 +8,7 @@
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#include <stdbool.h>
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#include "sdkconfig.h"
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#include "esp_sleep.h"
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#include "hal/uart_types.h"
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#ifdef __cplusplus
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extern "C" {
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@@ -134,7 +135,7 @@ void esp_sleep_restore_isolated_digital_gpio(void);
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*/
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typedef enum {
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ESP_SLEEP_CLOCK_IOMUX, //!< The clock ICG cell mapping of IOMUX
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ESP_SLEEP_CLOCK_LEDC, //!< The clock ICG cell mapping of LEDC
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ESP_SLEEP_CLOCK_LEDC0, //!< The clock ICG cell mapping of LEDC0
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ESP_SLEEP_CLOCK_UART0, //!< The clock ICG cell mapping of UART0
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ESP_SLEEP_CLOCK_UART1, //!< The clock ICG cell mapping of UART1
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#if SOC_UART_HP_NUM > 2
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@@ -152,6 +153,9 @@ typedef enum {
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ESP_SLEEP_CLOCK_MAX //!< Number of ICG cells
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} esp_sleep_clock_t;
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// Get UART sleep clock with giving uart num (num must be a valid HP UART port)
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#define SLEEP_UART_ICG(num) ((esp_sleep_clock_t)(ESP_SLEEP_CLOCK_UART0 + (num)))
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/**
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* @brief Clock ICG options
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*/
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