Mirrors/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2026-10-03 03:31:41 +03:00
Code Issues Packages Projects Releases Wiki Activity

refactor(ppa): avoid the use of yuv422_pack_order field in PPA driver

Browse Source
This commit is contained in:
Song Ruo Jing
2025-11-24 11:38:07 +08:00
parent 222d81976a
commit d5c0ab7ad2
12 changed files with 144 additions and 96 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/soc/esp32p4/register/hw_ver3/soc/ppa_reg.h
+2 -2
View File
@@ -287,7 +287,7 @@ extern "C" {
#define PPA_RGB2YUV_PROTOCOL_V 0x00000001U
#define PPA_RGB2YUV_PROTOCOL_S 11
/** PPA_YUV422_RX_BYTE_ORDER : R/W; bitpos: [13:12]; default: 0;
* YUV422 input byte order when reg_sr_rx_cm is 4'd9. 0: YVYU, 1:YUYV, 2: VYUY, 3: UYVY
* YUV422 input byte order when reg_sr_rx_cm is 4'd9. 0: YVYU, 1:YUYV, 2: VYUY, 3: UYVY (high addr -> low addr)
*/
#define PPA_YUV422_RX_BYTE_ORDER 0x00000003U
#define PPA_YUV422_RX_BYTE_ORDER_M (PPA_YUV422_RX_BYTE_ORDER_V << PPA_YUV422_RX_BYTE_ORDER_S)
@@ -351,7 +351,7 @@ extern "C" {
#define PPA_BLEND_TX_RGB2YUV_PROTOCOL_V 0x00000001U
#define PPA_BLEND_TX_RGB2YUV_PROTOCOL_S 15
/** PPA_BLEND0_RX_YUV422_BYTE_ORDER : R/W; bitpos: [17:16]; default: 0;
* YUV422 input byte order when reg_sr_rx_cm is 4'd9. 0: YVYU, 1:YUYV, 2: VYUY, 3: UYVY
* YUV422 input byte order when reg_sr_rx_cm is 4'd9. 0: YVYU, 1:YUYV, 2: VYUY, 3: UYVY (high addr -> low addr)
*/
#define PPA_BLEND0_RX_YUV422_BYTE_ORDER 0x00000003U
#define PPA_BLEND0_RX_YUV422_BYTE_ORDER_M (PPA_BLEND0_RX_YUV422_BYTE_ORDER_V << PPA_BLEND0_RX_YUV422_BYTE_ORDER_S)
components/soc/esp32p4/register/hw_ver3/soc/ppa_struct.h
+2 -2
View File
@@ -116,7 +116,7 @@ typedef union {
*/
uint32_t rgb2yuv_protocol:1;
/** yuv422_rx_byte_order : R/W; bitpos: [13:12]; default: 0;
* YUV422 input byte order when reg_sr_rx_cm is 4'd9. 0: YVYU, 1:YUYV, 2: VYUY, 3: UYVY
* YUV422 input byte order when reg_sr_rx_cm is 4'd9. 0: YVYU, 1:YUYV, 2: VYUY, 3: UYVY (high addr -> low addr)
*/
uint32_t yuv422_rx_byte_order:2;
uint32_t reserved_14:18;
@@ -161,7 +161,7 @@ typedef union {
*/
uint32_t blend_tx_rgb2yuv_protocol:1;
/** blend0_rx_yuv422_byte_order : R/W; bitpos: [17:16]; default: 0;
* YUV422 input byte order when reg_sr_rx_cm is 4'd9. 0: YVYU, 1:YUYV, 2: VYUY, 3: UYVY
* YUV422 input byte order when reg_sr_rx_cm is 4'd9. 0: YVYU, 1:YUYV, 2: VYUY, 3: UYVY (high addr -> low addr)
*/
uint32_t blend0_rx_yuv422_byte_order:2;
uint32_t reserved_18:14;