feat(esp_hw_support): update cpu_pd support for esp32p4 v3.0

This commit is contained in:
wuzhenghui
2025-11-04 16:03:27 +08:00
parent 819fa8ccb2
commit d4b3d01b4d
11 changed files with 32 additions and 11 deletions
@@ -22,7 +22,7 @@ extern "C" {
* This file contains declarations of cpu retention related functions in light sleep mode.
*/
#if ESP_SLEEP_POWER_DOWN_CPU || SOC_PM_SUPPORT_CPU_PD
#if ESP_SLEEP_POWER_DOWN_CPU || (SOC_PM_SUPPORT_CPU_PD && !CONFIG_ESP32P4_SELECTS_REV_LESS_V3)
/**
* @brief Whether to allow the cpu power domain to be powered off.
*
@@ -72,7 +72,7 @@ typedef enum {
#if SOC_PM_SUPPORT_RC_FAST_PD
ESP_PD_DOMAIN_RC_FAST, //!< Internal Fast oscillator
#endif
#if SOC_PM_SUPPORT_CPU_PD
#if SOC_PM_SUPPORT_CPU_PD && !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
ESP_PD_DOMAIN_CPU, //!< CPU core
#endif
#if SOC_PM_SUPPORT_VDDSDIO_PD
@@ -139,7 +139,11 @@ enum {
ESP_ERR_SLEEP_TOO_SHORT_SLEEP_DURATION = ESP_ERR_INVALID_ARG,
};
#define ESP_SLEEP_POWER_DOWN_CPU (CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP || (SOC_CPU_IN_TOP_DOMAIN && CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP))
#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3
#define ESP_SLEEP_POWER_DOWN_CPU CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
#else
#define ESP_SLEEP_POWER_DOWN_CPU CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP
#endif
/**
* @brief Disable wakeup source
@@ -5,7 +5,7 @@ endif()
set(srcs)
if(CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP OR
(CONFIG_SOC_CPU_IN_TOP_DOMAIN AND CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP))
(CONFIG_ESP32P4_SELECTS_REV_LESS_V3 AND CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP))
list(APPEND srcs "port/${target}/sleep_cpu.c")
if(CONFIG_SOC_PM_CPU_RETENTION_BY_SW)
list(APPEND srcs "port/${target}/sleep_cpu_asm.S")
@@ -80,6 +80,9 @@ STRUCT_BEGIN
STRUCT_FIELD (long, 4, RV_SLP_CTX_MSTATUS, mstatus) /* Machine Status */
STRUCT_FIELD (long, 4, RV_SLP_CTX_MTVEC, mtvec) /* Machine Trap-Vector Base Address */
STRUCT_FIELD (long, 4, RV_SLP_CTX_MTVT, mtvt)
#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
STRUCT_FIELD (long, 4, RV_SLP_CTX_MINTTHRESH, mintthresh) /* Machine intr threshold */ // TODO
#endif
STRUCT_FIELD (long, 4, RV_SLP_CTX_MCAUSE, mcause) /* Machine Trap Cause */
STRUCT_FIELD (long, 4, RV_SLP_CTX_MTVAL, mtval) /* Machine Trap Value */
STRUCT_FIELD (long, 4, RV_SLP_CTX_MIE, mie) /* Machine intr enable */
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -12,6 +12,7 @@
#include "soc/cache_reg.h"
#define CACHE_MAP_L1_CACHE_MASK (BIT(0) | BIT(1) | BIT(4))
#define MTVT (0x307)
#define MINTTHRESH (0x347)
.section .tcm.data,"aw"
.global rv_core_critical_regs_frame
@@ -93,6 +94,10 @@ rv_core_critical_regs_save:
sw t3, RV_SLP_CTX_MCAUSE(t0)
csrr t4, MTVT
sw t4, RV_SLP_CTX_MTVT(t0)
#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
csrr t4, MINTTHRESH
sw t4, RV_SLP_CTX_MINTTHRESH(t0)
#endif
csrr t1, mtval
sw t1, RV_SLP_CTX_MTVAL(t0)
csrr t2, mie
@@ -177,6 +182,10 @@ rv_core_critical_regs_restore:
csrw mstatus, t2
lw t4, RV_SLP_CTX_MTVT(t0)
csrw MTVT, t4
#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
lw t1, RV_SLP_CTX_MINTTHRESH(t0)
csrw MINTTHRESH, t1
#endif
lw t3, RV_SLP_CTX_MTVEC(t0)
csrw mtvec, t3
lw t1, RV_SLP_CTX_MCAUSE(t0)
+1 -1
View File
@@ -2540,7 +2540,7 @@ static uint32_t get_power_down_flags(void)
}
#endif
#if SOC_PM_SUPPORT_CPU_PD && ESP_SLEEP_POWER_DOWN_CPU
#if SOC_PM_SUPPORT_CPU_PD && ESP_SLEEP_POWER_DOWN_CPU && !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
if ((s_config.domain[ESP_PD_DOMAIN_CPU].pd_option != ESP_PD_OPTION_ON) && cpu_domain_pd_allowed()) {
pd_flags |= RTC_SLEEP_PD_CPU;
}