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synced 2026-10-02 11:10:54 +03:00
refactor(usb): Make usb hal layer independent
This commit is contained in:
Tomas Rezucha
@@ -158,10 +158,6 @@ if(CONFIG_SOC_IEEE802154_SUPPORTED)
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endif()
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endif()
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if(CONFIG_SOC_USB_OTG_SUPPORTED)
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list(APPEND srcs "${target_folder}/usb_dwc_periph.c")
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endif()
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if(CONFIG_SOC_DAC_SUPPORTED)
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list(APPEND srcs "${target_folder}/dac_periph.c")
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endif()
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@@ -1,48 +0,0 @@
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/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stddef.h>
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#include "soc/gpio_sig_map.h"
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#include "soc/interrupts.h"
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#include "soc/usb_periph.h"
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/* -------------------------------- Private --------------------------------- */
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static const usb_otg_signal_conn_t otg_signals = {
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// Inputs
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.iddig = USB_OTG_IDDIG_IN_IDX,
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.avalid = USB_OTG_AVALID_IN_IDX,
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.bvalid = USB_SRP_BVALID_IN_IDX,
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.vbusvalid = USB_OTG_VBUSVALID_IN_IDX,
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.sessend = USB_SRP_SESSEND_IN_IDX,
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// Outputs
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.idpullup = USB_OTG_IDPULLUP_OUT_IDX,
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.dppulldown = USB_OTG_DPPULLDOWN_OUT_IDX,
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.dmpulldown = USB_OTG_DMPULLDOWN_OUT_IDX,
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.drvvbus = USB_OTG_DRVVBUS_OUT_IDX,
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.chrgvbus = USB_SRP_CHRGVBUS_OUT_IDX,
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.dischrgvbus = USB_SRP_DISCHRGVBUS_OUT_IDX,
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};
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static const usb_internal_phy_io_t internal_phy_io = {
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.dp = 21,
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.dm = 22,
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};
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/* --------------------------------- Public --------------------------------- */
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const usb_dwc_info_t usb_dwc_info = {
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.controllers = {
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[0] = {
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.fsls_signals = NULL,
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.otg_signals = &otg_signals,
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.internal_phy_io = &internal_phy_io,
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.supported_phys = USB_PHY_INST_FSLS_INTERN_0,
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.irq = ETS_USB_OTG11_INTR_SOURCE,
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.irq_2nd_cpu = -1,
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},
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},
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};
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@@ -1,59 +0,0 @@
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/*
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* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stddef.h>
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#include "soc/interrupts.h"
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#include "soc/gpio_sig_map.h"
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#include "soc/usb_periph.h"
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#include "soc/usb_dwc_struct.h"
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/* -------------------------------- Private --------------------------------- */
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static const usb_otg_signal_conn_t dwc_fs_otg_signals = {
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// Inputs
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.iddig = USB_OTG11_IDDIG_PAD_IN_IDX,
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.avalid = USB_OTG11_AVALID_PAD_IN_IDX,
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.bvalid = USB_SRP_BVALID_PAD_IN_IDX,
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.vbusvalid = USB_OTG11_VBUSVALID_PAD_IN_IDX,
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.sessend = USB_SRP_SESSEND_PAD_IN_IDX,
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// Outputs
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.idpullup = USB_OTG11_IDPULLUP_PAD_OUT_IDX,
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.dppulldown = USB_OTG11_DPPULLDOWN_PAD_OUT_IDX,
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.dmpulldown = USB_OTG11_DMPULLDOWN_PAD_OUT_IDX,
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.drvvbus = USB_OTG11_DRVVBUS_PAD_OUT_IDX,
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.chrgvbus = USB_SRP_CHRGVBUS_PAD_OUT_IDX,
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.dischrgvbus = USB_SRP_DISCHRGVBUS_PAD_OUT_IDX,
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};
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static const usb_internal_phy_io_t internal_phy_io = {
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.dp = 27,
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.dm = 26,
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};
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/* --------------------------------- Public --------------------------------- */
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const usb_dwc_info_t usb_dwc_info = {
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.controllers = {
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// High-Speed USB-DWC
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[0] = {
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.fsls_signals = NULL,
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.otg_signals = NULL,
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.internal_phy_io = NULL, // HS PHY is not mapped to any GPIO
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.supported_phys = USB_PHY_INST_UTMI_0,
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.irq = ETS_USB_OTG_INTR_SOURCE,
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.irq_2nd_cpu = ETS_USB_OTG_ENDP_MULTI_PROC_INTR_SOURCE,
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},
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// Full-Speed USB-DWC
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[1] = {
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.fsls_signals = NULL,
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.otg_signals = &dwc_fs_otg_signals,
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.internal_phy_io = &internal_phy_io,
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.supported_phys = USB_PHY_INST_FSLS_INTERN_0,
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.irq = ETS_USB_OTG11_CH0_INTR_SOURCE,
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.irq_2nd_cpu = -1,
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},
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},
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};
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@@ -1,60 +0,0 @@
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/*
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* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "soc/gpio_sig_map.h"
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#include "soc/interrupts.h"
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#include "soc/usb_periph.h"
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/* -------------------------------- Private --------------------------------- */
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static const usb_fsls_serial_signal_conn_t fsls_signals = {
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// Inputs
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.rx_dp = USB_EXTPHY_VP_IDX,
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.rx_dm = USB_EXTPHY_VM_IDX,
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.rx_rcv = USB_EXTPHY_RCV_IDX,
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// Outputs
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.suspend_n = USB_EXTPHY_SUSPND_IDX,
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.tx_enable_n = USB_EXTPHY_OEN_IDX,
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.tx_dp = USB_EXTPHY_VPO_IDX,
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.tx_dm = USB_EXTPHY_VMO_IDX,
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.fs_edge_sel = USB_EXTPHY_SPEED_IDX,
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};
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static const usb_otg_signal_conn_t otg_signals = {
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// Inputs
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.iddig = USB_OTG_IDDIG_IN_IDX,
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.avalid = USB_OTG_AVALID_IN_IDX,
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.bvalid = USB_SRP_BVALID_IN_IDX,
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.vbusvalid = USB_OTG_VBUSVALID_IN_IDX,
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.sessend = USB_SRP_SESSEND_IN_IDX,
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// Outputs
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.idpullup = USB_OTG_IDPULLUP_IDX,
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.dppulldown = USB_OTG_DPPULLDOWN_IDX,
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.dmpulldown = USB_OTG_DMPULLDOWN_IDX,
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.drvvbus = USB_OTG_DRVVBUS_IDX,
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.chrgvbus = USB_SRP_CHRGVBUS_IDX,
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.dischrgvbus = USB_SRP_DISCHRGVBUS_IDX,
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};
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static const usb_internal_phy_io_t internal_phy_io = {
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.dp = 20,
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.dm = 19,
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};
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/* --------------------------------- Public --------------------------------- */
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const usb_dwc_info_t usb_dwc_info = {
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.controllers = {
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[0] = {
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.fsls_signals = &fsls_signals,
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.otg_signals = &otg_signals,
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.internal_phy_io = &internal_phy_io,
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.supported_phys = USB_PHY_INST_FSLS_INTERN_0,
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.irq = ETS_USB_INTR_SOURCE,
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.irq_2nd_cpu = -1,
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},
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},
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};
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@@ -1,60 +0,0 @@
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/*
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* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "soc/gpio_sig_map.h"
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#include "soc/interrupts.h"
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#include "soc/usb_periph.h"
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/* -------------------------------- Private --------------------------------- */
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static const usb_fsls_serial_signal_conn_t fsls_signals = {
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// Inputs
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.rx_dp = USB_EXTPHY_VP_IDX,
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.rx_dm = USB_EXTPHY_VM_IDX,
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.rx_rcv = USB_EXTPHY_RCV_IDX,
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// Outputs
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.suspend_n = USB_EXTPHY_SUSPND_IDX,
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.tx_enable_n = USB_EXTPHY_OEN_IDX,
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.tx_dp = USB_EXTPHY_VPO_IDX,
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.tx_dm = USB_EXTPHY_VMO_IDX,
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.fs_edge_sel = USB_EXTPHY_SPEED_IDX,
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};
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static const usb_otg_signal_conn_t otg_signals = {
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// Inputs
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.iddig = USB_OTG_IDDIG_IN_IDX,
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.avalid = USB_OTG_AVALID_IN_IDX,
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.bvalid = USB_SRP_BVALID_IN_IDX,
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.vbusvalid = USB_OTG_VBUSVALID_IN_IDX,
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.sessend = USB_SRP_SESSEND_IN_IDX,
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// Outputs
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.idpullup = USB_OTG_IDPULLUP_IDX,
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.dppulldown = USB_OTG_DPPULLDOWN_IDX,
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.dmpulldown = USB_OTG_DMPULLDOWN_IDX,
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.drvvbus = USB_OTG_DRVVBUS_IDX,
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.chrgvbus = USB_SRP_CHRGVBUS_IDX,
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.dischrgvbus = USB_SRP_DISCHRGVBUS_IDX,
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};
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static const usb_internal_phy_io_t internal_phy_io = {
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.dp = 20,
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.dm = 19,
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};
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/* --------------------------------- Public --------------------------------- */
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const usb_dwc_info_t usb_dwc_info = {
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.controllers = {
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[0] = {
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.fsls_signals = &fsls_signals,
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.otg_signals = &otg_signals,
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.internal_phy_io = &internal_phy_io,
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.supported_phys = USB_PHY_INST_FSLS_INTERN_0,
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.irq = ETS_USB_INTR_SOURCE,
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.irq_2nd_cpu = -1,
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},
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},
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};
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@@ -1,112 +0,0 @@
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/*
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* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include <stdbool.h>
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#include "soc/soc_pins.h"
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#include "soc/soc_caps.h"
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#include "soc/gpio_sig_map.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if SOC_USB_OTG_SUPPORTED
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/* ---------------------------------- Types --------------------------------- */
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/**
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* @brief USB PHY Instance Type
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*/
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typedef enum {
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USB_PHY_INST_FSLS_INTERN_0 = (1 << 0),
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USB_PHY_INST_FSLS_INTERN_1 = (1 << 1),
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USB_PHY_INST_UTMI_0 = (1 << 2),
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USB_PHY_INST_EXTERN = (1 << 3),
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} usb_phy_inst_t;
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/**
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* @brief USB PHY FSLS Serial Interface Signals
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*
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* Structure to store the GPIO matrix signal indexes for a USB PHY FSLS Serial
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* interface's signals.
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*
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* @note Refer to section "2.2.1.13 FsLsSerialMode" of the UTMI+ for more
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* details regarding the FSLS Serial Interface.
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*/
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typedef struct {
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// Inputs
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int rx_dp;
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int rx_dm;
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int rx_rcv;
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// Outputs
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int suspend_n;
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int tx_enable_n;
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int tx_dp;
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int tx_dm;
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int fs_edge_sel;
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} usb_fsls_serial_signal_conn_t;
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/**
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* @brief USB PHY UTMI OTG Interface Signal Index Type
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*
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* Structure to store the GPIO matrix signal indexes for a UTMI PHY interface's
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* OTG signals.
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*/
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typedef struct {
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// Inputs
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int iddig;
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int avalid;
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int bvalid;
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int vbusvalid;
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int sessend;
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// Outputs
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int idpullup;
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int dppulldown;
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int dmpulldown;
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int drvvbus;
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int chrgvbus;
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int dischrgvbus;
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} usb_otg_signal_conn_t;
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/**
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* @brief Internal USB PHY IO
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*
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* Structure to store the IO numbers for a particular internal USB PHY
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*/
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typedef struct {
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int dp;
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int dm;
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} usb_internal_phy_io_t;
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/**
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* @brief USB Controller Information
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*
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* Structure to store information for all USB-DWC instances
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*
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* For targets with multiple USB controllers, we support only fixed mapping of the PHYs.
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* This is a software limitation; the hardware supports swapping Controllers and PHYs.
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*/
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typedef struct {
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struct {
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const usb_fsls_serial_signal_conn_t * const fsls_signals; // Must be set if external PHY is supported by controller
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const usb_otg_signal_conn_t * const otg_signals;
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const usb_internal_phy_io_t * const internal_phy_io; // Must be set for internal FSLS PHY(s)
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const usb_phy_inst_t supported_phys; // Bitmap of supported PHYs by this controller
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const int irq;
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const int irq_2nd_cpu; // The USB-DWC can provide 2nd interrupt so each CPU can have its own interrupt line. Set to -1 if not supported
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} controllers [SOC_USB_OTG_PERIPH_NUM];
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} usb_dwc_info_t;
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extern const usb_dwc_info_t usb_dwc_info;
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#endif // SOC_USB_OTG_SUPPORTED
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#ifdef __cplusplus
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}
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#endif
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