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Merge branch 'fix/p4_min_rev_usage_v6.0' into 'release/v6.0'

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P4: fix wrong rev_min usage in rom and other places (v6.0)

See merge request espressif/esp-idf!45223
This commit is contained in:
Jiang Jiang Jian
2026-01-30 10:50:51 +08:00
parent 1f2045975f 79f7427729
commit d3e1887bbc
17 changed files with 56 additions and 42 deletions
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components/esp_system/port/cpu_start.c
+2 -2
View File
@@ -686,7 +686,7 @@ NOINLINE_ATTR static void system_early_init(const soc_reset_reason_t *rst_reas)
#if SOC_CPU_CORES_NUM > 1 // there is no 'single-core mode' for natively single-core processors
#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
#if CONFIG_IDF_TARGET_ESP32P4 && CONFIG_ESP32P4_REV_MIN_FULL >= 300
#if CONFIG_IDF_TARGET_ESP32P4 && !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
// Ensure autoclock gating mode for core1 is enabled, it gets disabled in single-core mode.
REG_SET_BIT(HP_SYS_CLKRST_CPU_WAITI_CTRL0_REG, HP_SYS_CLKRST_REG_CORE1_WAITI_ICG_EN);
#endif
@@ -704,7 +704,7 @@ NOINLINE_ATTR static void system_early_init(const soc_reset_reason_t *rst_reas)
REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RESETING);
#endif
#elif CONFIG_IDF_TARGET_ESP32P4
#if CONFIG_ESP32P4_REV_MIN_FULL >= 300
#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
// In single core mode, the CPU system should ignore the WFI state of core1 when entering WFI autoclock gating mode.
REG_CLR_BIT(HP_SYS_CLKRST_CPU_WAITI_CTRL0_REG, HP_SYS_CLKRST_REG_CORE1_WAITI_ICG_EN);
#endif
components/esp_system/port/soc/esp32p4/system_internal.c
+14 -11
View File
@@ -32,6 +32,7 @@
#include "hal/axi_dma_ll.h"
#include "hal/dw_gdma_ll.h"
#include "hal/dma2d_ll.h"
#include "hal/efuse_hal.h"
void esp_system_reset_modules_on_exit(void)
{
@@ -123,19 +124,21 @@ void esp_system_reset_modules_on_exit(void)
CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN2_REG, HP_SYS_CLKRST_REG_RST_EN_RSA);
CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN2_REG, HP_SYS_CLKRST_REG_RST_EN_SHA);
#if CONFIG_ESP32P4_REV_MIN_FULL <= 100
// enable soc clk and reset parent crypto
SET_PERI_REG_MASK(HP_SYS_CLKRST_SOC_CLK_CTRL1_REG, HP_SYS_CLKRST_REG_CRYPTO_SYS_CLK_EN);
SET_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN2_REG, HP_SYS_CLKRST_REG_RST_EN_CRYPTO);
CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN2_REG, HP_SYS_CLKRST_REG_RST_EN_CRYPTO);
#if CONFIG_ESP32P4_REV_MIN_FULL < 101
if (efuse_hal_chip_revision() < 101) {
// enable soc clk and reset parent crypto
SET_PERI_REG_MASK(HP_SYS_CLKRST_SOC_CLK_CTRL1_REG, HP_SYS_CLKRST_REG_CRYPTO_SYS_CLK_EN);
SET_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN2_REG, HP_SYS_CLKRST_REG_RST_EN_CRYPTO);
CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN2_REG, HP_SYS_CLKRST_REG_RST_EN_CRYPTO);
// enable soc clk for key manager
SET_PERI_REG_MASK(HP_SYS_CLKRST_SOC_CLK_CTRL1_REG, HP_SYS_CLKRST_REG_KEY_MANAGER_SYS_CLK_EN);
// enable soc clk for key manager
SET_PERI_REG_MASK(HP_SYS_CLKRST_SOC_CLK_CTRL1_REG, HP_SYS_CLKRST_REG_KEY_MANAGER_SYS_CLK_EN);
// enable key manager peripheral clock and reset
SET_PERI_REG_MASK(HP_SYS_CLKRST_PERI_CLK_CTRL25_REG, HP_SYS_CLKRST_REG_CRYPTO_KM_CLK_EN);
SET_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN2_REG, HP_SYS_CLKRST_REG_RST_EN_KM);
CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN2_REG, HP_SYS_CLKRST_REG_RST_EN_KM);
// enable key manager peripheral clock and reset
SET_PERI_REG_MASK(HP_SYS_CLKRST_PERI_CLK_CTRL25_REG, HP_SYS_CLKRST_REG_CRYPTO_KM_CLK_EN);
SET_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN2_REG, HP_SYS_CLKRST_REG_RST_EN_KM);
CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN2_REG, HP_SYS_CLKRST_REG_RST_EN_KM);
}
#endif
#if CONFIG_ESP32P4_REV_MIN_FULL == 0