Merge branch 'fix/handle_shared_intr_v5.3' into 'release/v5.3'

Fix/handle shared intr (v5.3)

See merge request espressif/esp-idf!44073

components/hal/esp32p4/include/hal/ledc_ll.h

@@ -30,6 +30,8 @@ extern "C" {
 #define LEDC_LL_FRACTIONAL_BITS    (8)
 #define LEDC_LL_FRACTIONAL_MAX     ((1 << LEDC_LL_FRACTIONAL_BITS) - 1)
 #define LEDC_LL_GLOBAL_CLOCKS      SOC_LEDC_CLKS
+/// Get the mask of the fade end interrupt status register.
+#define LEDC_LL_FADE_END_INTR_MASK  (0xffUL << LEDC_DUTY_CHNG_END_CH0_INT_ENA_S)
 
 /**
  * @brief Enable peripheral register clock
@@ -507,7 +509,6 @@ static inline void ledc_ll_set_fade_end_intr(ledc_dev_t *hw, ledc_mode_t speed_m
  *
  * @param hw Beginning address of the peripheral registers
  * @param speed_mode LEDC speed_mode, low-speed mode only
- * @param channel_num LEDC channel index (0-5), select from ledc_channel_t
  * @param intr_status The fade end interrupt status
  *
  * @return None
@@ -519,6 +520,18 @@ static inline void ledc_ll_get_fade_end_intr_status(ledc_dev_t *hw, ledc_mode_t
     *intr_status = (value >> int_en_base) & 0xff;
 }
 
+/**
+ * @brief Get the address of the fade end interrupt status register.
+ *
+ * @param hw Beginning address of the peripheral registers
+ * @return Pointer to the fade end interrupt status register.
+ */
+static inline volatile void* ledc_ll_get_fade_end_intr_addr(ledc_dev_t *hw)
+{
+    return &hw->int_st.val;
+}
+
+
 /**
  * @brief Clear fade end interrupt status
  *

components/hal/esp32p4/include/hal/uart_ll.h

@@ -601,6 +601,11 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw)
     return hw->int_st.val;
 }
 
+FORCE_INLINE_ATTR volatile void* uart_ll_get_intr_status_reg(uart_dev_t *hw)
+{
+    return &hw->int_st.val;
+}
+
 /**
  * @brief  Clear the UART interrupt status based on the given mask.
  *