feat(riscv_trace): add resync mode validation for existing targets

components/esp_hal_debug_assist/esp32c5/include/hal/riscv_trace_ll.h

@@ -142,6 +142,13 @@ static inline void riscv_trace_ll_set_dm_trigger_ena(trace_dev_t *hw, bool enabl
  * Resynchronization
  *--------------------------------------------------------------------------*/
 
+/** @brief Whether the resync counter can represent the given mode. */
+static inline bool riscv_trace_ll_resync_mode_is_supported(uint32_t mode)
+{
+    return mode == RISCV_TRACE_RESYNC_DISABLED || mode == RISCV_TRACE_RESYNC_PACKET ||
+           mode == RISCV_TRACE_RESYNC_CYCLE;
+}
+
 static inline void riscv_trace_ll_set_resync_mode(trace_dev_t *hw, uint32_t mode)
 {
     hw->resync_prolonged.resync_mode = mode;

components/esp_hal_debug_assist/esp32p4/include/hal/riscv_trace_ll.h

@@ -156,6 +156,13 @@ static inline void riscv_trace_ll_set_dm_trigger_ena(trace_dev_t *hw, bool enabl
  * Resynchronization
  *--------------------------------------------------------------------------*/
 
+/** @brief Whether the resync counter can represent the given mode. */
+static inline bool riscv_trace_ll_resync_mode_is_supported(uint32_t mode)
+{
+    return mode == RISCV_TRACE_RESYNC_DISABLED || mode == RISCV_TRACE_RESYNC_PACKET ||
+           mode == RISCV_TRACE_RESYNC_CYCLE;
+}
+
 static inline void riscv_trace_ll_set_resync_mode(trace_dev_t *hw, uint32_t mode)
 {
     hw->resync_prolonged.resync_mode = mode;

components/esp_hal_debug_assist/esp32s31/include/hal/riscv_trace_ll.h

@@ -152,6 +152,13 @@ static inline void riscv_trace_ll_set_dm_trigger_ena(trace_dev_t *hw, bool enabl
  * Resynchronization
  *--------------------------------------------------------------------------*/
 
+/** @brief Whether the resync counter can represent the given mode. */
+static inline bool riscv_trace_ll_resync_mode_is_supported(uint32_t mode)
+{
+    return mode == RISCV_TRACE_RESYNC_DISABLED || mode == RISCV_TRACE_RESYNC_PACKET ||
+           mode == RISCV_TRACE_RESYNC_CYCLE;
+}
+
 static inline void riscv_trace_ll_set_resync_mode(trace_dev_t *hw, uint32_t mode)
 {
     hw->resync_prolonged.resync_mode = mode;

components/esp_hal_debug_assist/include/hal/riscv_trace_types.h

@@ -34,6 +34,20 @@ typedef enum {
     RISCV_TRACE_PRIV_MACHINE    = 3, /*!< Machine mode */
 } riscv_trace_priv_t;
 
+/**
+ * @brief Resynchronization mode selected by the resync counter.
+ *
+ * Values follow the v2.0 (2-bit) register encoding, which the driver's public
+ * enum also uses. Targets with a narrower field implement a subset and their LL
+ * translates the value when writing the register (see
+ * riscv_trace_ll_resync_mode_is_supported()).
+ */
+typedef enum {
+    RISCV_TRACE_RESYNC_DISABLED = 0, /*!< Periodic resync disabled */
+    RISCV_TRACE_RESYNC_PACKET   = 2, /*!< Resync counter counts by packet */
+    RISCV_TRACE_RESYNC_CYCLE    = 3, /*!< Resync counter counts by cycle */
+} riscv_trace_resync_mode_t;
+
 /**
  * @brief Trace encoder work-status field.
  *

components/esp_riscv_trace/src/esp_riscv_trace.c

@@ -120,6 +120,7 @@ static uint32_t trace_buffer_caps(esp_riscv_trace_buffer_mem_t mem)
            : ESP_RISCV_TRACE_BUFFER_CAPS_INTERNAL;
 }
 
+#if SOC_RISCV_TRACE_FILTER_SUPPORTED
 static bool is_valid_filter_comparator(const esp_riscv_trace_filter_comparator_t *c)
 {
     return (c->input == ESP_RISCV_TRACE_FILTER_INPUT_IADDR ||
@@ -155,6 +156,7 @@ static esp_err_t validate_filter_config(const esp_riscv_trace_filter_config_t *c
     }
     return ESP_OK;
 }
+#endif // SOC_RISCV_TRACE_FILTER_SUPPORTED
 
 static esp_err_t validate_trace_config(esp_riscv_trace_core_t core_id, const esp_riscv_trace_config_t *config,
                                        esp_riscv_trace_handle_t *ret_handle)
@@ -167,6 +169,8 @@ static esp_err_t validate_trace_config(esp_riscv_trace_core_t core_id, const esp
     ESP_RETURN_ON_FALSE(is_valid_address_mode(config->address_mode), ESP_ERR_INVALID_ARG, TAG, "invalid address mode");
     ESP_RETURN_ON_FALSE(is_valid_mem_mode(config->mem_mode), ESP_ERR_INVALID_ARG, TAG, "invalid memory mode");
     ESP_RETURN_ON_FALSE(is_valid_resync_mode(config->resync_mode), ESP_ERR_INVALID_ARG, TAG, "invalid resync mode");
+    ESP_RETURN_ON_FALSE(riscv_trace_ll_resync_mode_is_supported((uint32_t)config->resync_mode),
+                        ESP_ERR_NOT_SUPPORTED, TAG, "resync mode not supported on this target");
     ESP_RETURN_ON_FALSE(is_valid_ahb_burst(config->ahb_burst), ESP_ERR_INVALID_ARG, TAG, "invalid AHB burst");
     ESP_RETURN_ON_FALSE(is_valid_core_mask(config->core_mask), ESP_ERR_INVALID_ARG, TAG, "invalid core mask");
     ESP_RETURN_ON_FALSE(is_valid_buffer_mem(config->buffer_mem), ESP_ERR_INVALID_ARG, TAG, "invalid buffer memory");