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feat(riscv_trace): add resync mode validation for existing targets

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This commit is contained in:
Erhan Kurubas
2026-08-07 14:44:03 +02:00
parent 91534a8488
commit d3246931b1
5 changed files with 39 additions and 0 deletions
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components/esp_hal_debug_assist/esp32c5/include/hal/riscv_trace_ll.h
+7
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@@ -142,6 +142,13 @@ static inline void riscv_trace_ll_set_dm_trigger_ena(trace_dev_t *hw, bool enabl
* Resynchronization
*--------------------------------------------------------------------------*/
/** @brief Whether the resync counter can represent the given mode. */
static inline bool riscv_trace_ll_resync_mode_is_supported(uint32_t mode)
{
return mode == RISCV_TRACE_RESYNC_DISABLED || mode == RISCV_TRACE_RESYNC_PACKET ||
mode == RISCV_TRACE_RESYNC_CYCLE;
}
static inline void riscv_trace_ll_set_resync_mode(trace_dev_t *hw, uint32_t mode)
{
hw->resync_prolonged.resync_mode = mode;
components/esp_hal_debug_assist/esp32p4/include/hal/riscv_trace_ll.h
+7
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@@ -156,6 +156,13 @@ static inline void riscv_trace_ll_set_dm_trigger_ena(trace_dev_t *hw, bool enabl
* Resynchronization
*--------------------------------------------------------------------------*/
/** @brief Whether the resync counter can represent the given mode. */
static inline bool riscv_trace_ll_resync_mode_is_supported(uint32_t mode)
{
return mode == RISCV_TRACE_RESYNC_DISABLED || mode == RISCV_TRACE_RESYNC_PACKET ||
mode == RISCV_TRACE_RESYNC_CYCLE;
}
static inline void riscv_trace_ll_set_resync_mode(trace_dev_t *hw, uint32_t mode)
{
hw->resync_prolonged.resync_mode = mode;
components/esp_hal_debug_assist/esp32s31/include/hal/riscv_trace_ll.h
+7
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@@ -152,6 +152,13 @@ static inline void riscv_trace_ll_set_dm_trigger_ena(trace_dev_t *hw, bool enabl
* Resynchronization
*--------------------------------------------------------------------------*/
/** @brief Whether the resync counter can represent the given mode. */
static inline bool riscv_trace_ll_resync_mode_is_supported(uint32_t mode)
{
return mode == RISCV_TRACE_RESYNC_DISABLED || mode == RISCV_TRACE_RESYNC_PACKET ||
mode == RISCV_TRACE_RESYNC_CYCLE;
}
static inline void riscv_trace_ll_set_resync_mode(trace_dev_t *hw, uint32_t mode)
{
hw->resync_prolonged.resync_mode = mode;
components/esp_hal_debug_assist/include/hal/riscv_trace_types.h
+14
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@@ -34,6 +34,20 @@ typedef enum {
RISCV_TRACE_PRIV_MACHINE = 3, /*!< Machine mode */
} riscv_trace_priv_t;
/**
* @brief Resynchronization mode selected by the resync counter.
*
* Values follow the v2.0 (2-bit) register encoding, which the driver's public
* enum also uses. Targets with a narrower field implement a subset and their LL
* translates the value when writing the register (see
* riscv_trace_ll_resync_mode_is_supported()).
*/
typedef enum {
RISCV_TRACE_RESYNC_DISABLED = 0, /*!< Periodic resync disabled */
RISCV_TRACE_RESYNC_PACKET = 2, /*!< Resync counter counts by packet */
RISCV_TRACE_RESYNC_CYCLE = 3, /*!< Resync counter counts by cycle */
} riscv_trace_resync_mode_t;
/**
* @brief Trace encoder work-status field.
*