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https://github.com/espressif/esp-idf.git
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change: declutter SPI DMA debug logs
SPI component is overly verbose about its handling of pre-DMA cache<->memory synchronization. This commit moves the logs to verbose level.
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@@ -1197,7 +1197,7 @@ static SPI_MASTER_ISR_ATTR esp_err_t setup_dma_priv_buffer(spi_host_t *host, uin
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}
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}
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need_malloc |= (((uint32_t)buffer | len) & (alignment - 1));
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ESP_EARLY_LOGD(SPI_TAG, "%s %p, len %d, is_ptr_ext %d, use_psram: %d, alignment: %d, need_malloc: %d from %s", is_tx ? "TX" : "RX", buffer, len, is_ptr_ext, use_psram, alignment, need_malloc, (mem_cap & MALLOC_CAP_SPIRAM) ? "psram" : "internal");
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ESP_EARLY_LOGV(SPI_TAG, "%s %p, len %d, is_ptr_ext %d, use_psram: %d, alignment: %d, need_malloc: %d from %s", is_tx ? "TX" : "RX", buffer, len, is_ptr_ext, use_psram, alignment, need_malloc, (mem_cap & MALLOC_CAP_SPIRAM) ? "psram" : "internal");
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if (need_malloc) {
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ESP_RETURN_ON_FALSE_ISR(!(flags & SPI_TRANS_DMA_BUFFER_ALIGN_MANUAL), ESP_ERR_INVALID_ARG, SPI_TAG, "Set flag SPI_TRANS_DMA_BUFFER_ALIGN_MANUAL but %s addr&len not align to %d, or not dma_capable", is_tx ? "TX" : "RX", alignment);
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len = (len + alignment - 1) & (~(alignment - 1)); // up align alignment
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@@ -102,7 +102,7 @@ esp_err_t esp_cache_msync(void *addr, size_t size, int flags)
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uint32_t cache_id = 0;
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valid = cache_hal_vaddr_to_cache_level_id(vaddr, size, &cache_level, &cache_id);
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if (!valid) {
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ESP_EARLY_LOGD(TAG, "vaddr is not in cacheable range, do nothing");
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ESP_EARLY_LOGV(TAG, "vaddr is not in cacheable range, do nothing");
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return ESP_ERR_NOT_SUPPORTED;
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}
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