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refactor(clk_tree): use general api to enable the clk

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This commit is contained in:
Chen Jichang
2026-05-15 13:55:37 +08:00
committed by BOT
parent 8f7209c611
commit d1a64bffc0
52 changed files with 1095 additions and 673 deletions
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components/esp_psram/device/esp_psram_impl_ap_hex.c
+7 -7
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@@ -13,10 +13,9 @@
#include "esp_private/esp_psram_impl.h"
#include "hal/psram_ctrlr_ll.h"
#include "hal/mspi_ll.h"
#include "clk_ctrl_os.h"
// Reset and Clock Control registers are mixing with other peripherals, so we need to use a critical section
#define PSRAM_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
#include "soc/rtc.h"
#include "esp_check.h"
#include "esp_private/esp_clk_tree_common.h"
#define AP_HEX_PSRAM_SYNC_READ 0x0000
#define AP_HEX_PSRAM_SYNC_WRITE 0x8080
@@ -410,13 +409,14 @@ static void s_configure_psram_ecc(void)
esp_err_t esp_psram_impl_enable(void)
{
#if SOC_CLK_MPLL_SUPPORTED
periph_rtc_mpll_acquire();
// We need to use the acquire and freq_set functions directly instead of general clk_tree API for IRAM safe function
esp_clk_tree_mpll_acquire();
uint32_t real_mpll_freq = 0;
periph_rtc_mpll_freq_set(AP_HEX_PSRAM_MPLL_DEFAULT_FREQ_MHZ * 1000000, &real_mpll_freq);
esp_clk_tree_mpll_freq_set(AP_HEX_PSRAM_MPLL_DEFAULT_FREQ_MHZ * 1000000, &real_mpll_freq);
ESP_EARLY_LOGD(TAG, "real_mpll_freq: %d", real_mpll_freq);
#endif
PSRAM_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
psram_ctrlr_ll_enable_module_clock(PSRAM_CTRLR_LL_MSPI_ID_2, true);
psram_ctrlr_ll_reset_module_clock(PSRAM_CTRLR_LL_MSPI_ID_2);
psram_ctrlr_ll_select_clk_source(PSRAM_CTRLR_LL_MSPI_ID_2, PSRAM_CLK_SRC_MPLL);