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Merge branch 'fix/make_deepsleep_gpio_wakeup_usable_for_pd_top_lightsleep_v6.0' into 'release/v6.0'
change(esp_hw_support): deepsleep gpio wakeup API renaming to support PD_TOP lightsleep wakeup (v6.0) See merge request espressif/esp-idf!45416
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@@ -563,7 +563,7 @@ config SOC_GPIO_SUPPORT_ETM
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bool
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default y
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config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
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config SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
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bool
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default y
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@@ -579,11 +579,11 @@ config SOC_GPIO_OUT_RANGE_MAX
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int
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default 28
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config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
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config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK
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int
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default 0
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config SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT
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config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT
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int
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default 7
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@@ -221,8 +221,9 @@
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#define SOC_GPIO_SUPPORT_ETM 1
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// Target has the full LP IO subsystem
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// GPIO0~7 on ESP32C5 can support chip deep sleep wakeup
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#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1)
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// GPIO0~7 on ESP32C5 can support chip HP peripheral powerdown-ed sleep wakeup
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#define SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP (1)
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#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
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// LP IO peripherals have independent clock gating to manage
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#define SOC_LP_IO_CLOCK_IS_INDEPENDENT (1)
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@@ -232,8 +233,8 @@
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#define SOC_GPIO_IN_RANGE_MAX 28
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#define SOC_GPIO_OUT_RANGE_MAX 28
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#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6)
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#define SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT (7)
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#define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6)
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#define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT (7)
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// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_7~GPIO_NUM_28)
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#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x0000000001FFFF80ULL
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