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Merge branch 'fix/make_deepsleep_gpio_wakeup_usable_for_pd_top_lightsleep_v6.0' into 'release/v6.0'

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change(esp_hw_support): deepsleep gpio wakeup API renaming to support PD_TOP lightsleep wakeup (v6.0)

See merge request espressif/esp-idf!45416
This commit is contained in:
Jiang Jiang Jian
2026-02-02 10:48:40 +08:00
parent 8e3e325ba6 3c44b8fb85
commit d0f992c02f
38 changed files with 400 additions and 174 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
+3 -3
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@@ -291,7 +291,7 @@ config SOC_GPIO_SUPPORT_FORCE_HOLD
bool
default y
config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
config SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
bool
default y
@@ -303,11 +303,11 @@ config SOC_GPIO_OUT_RANGE_MAX
int
default 20
config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK
int
default 0
config SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT
config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT
int
default 6
components/soc/esp32c2/include/soc/soc_caps.h
+6 -6
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@@ -126,21 +126,21 @@
#define SOC_GPIO_PIN_COUNT 21
#define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1
// Target has no full RTC IO subsystem, GPIO0~5 remain RTC function (powered by VDD3V3_RTC, and can be used as deep-sleep wakeup pins)
// Target has no full RTC IO subsystem, GPIO0~5 remain RTC function (powered by VDD3V3_RTC, and can be used as HP peripheral powerdown-ed sleep wakeup pins)
// Force hold is a new function of ESP32-C2
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
// GPIO0~5 on ESP32-C2 can support chip deep sleep wakeup
#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1)
// GPIO0~5 on ESP32-C2 can support chip HP peripheral powerdown-ed sleep wakeup
#define SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP (1)
#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
#define SOC_GPIO_VALID_GPIO_MASK ((1U<<SOC_GPIO_PIN_COUNT) - 1)
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
#define SOC_GPIO_IN_RANGE_MAX 20
#define SOC_GPIO_OUT_RANGE_MAX 20
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5)
#define SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT (6)
#define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5)
#define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT (6)
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_6~GPIO_NUM_20)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x00000000001FFFC0ULL
components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
+3 -3
View File
@@ -387,7 +387,7 @@ config SOC_GPIO_SUPPORT_FORCE_HOLD
bool
default y
config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
config SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
bool
default y
@@ -399,11 +399,11 @@ config SOC_GPIO_OUT_RANGE_MAX
int
default 21
config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK
int
default 0
config SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT
config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT
int
default 6
components/soc/esp32c3/include/soc/soc_caps.h
+6 -6
View File
@@ -165,21 +165,21 @@
#define SOC_GPIO_PIN_COUNT 22
#define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1
// Target has no full RTC IO subsystem, GPIO0~5 remain RTC function (powered by VDD3V3_RTC, and can be used as deep-sleep wakeup pins)
// Target has no full RTC IO subsystem, GPIO0~5 remain RTC function (powered by VDD3V3_RTC, and can be used as HP peripheral powerdown-ed wakeup pins)
// Force hold is a new function of ESP32-C3
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
// GPIO0~5 on ESP32C3 can support chip deep sleep wakeup
#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1)
// GPIO0~5 on ESP32C3 can support chip HP peripheral powerdown-ed sleep wakeup
#define SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP (1)
#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
#define SOC_GPIO_VALID_GPIO_MASK ((1U<<SOC_GPIO_PIN_COUNT) - 1)
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
#define SOC_GPIO_IN_RANGE_MAX 21
#define SOC_GPIO_OUT_RANGE_MAX 21
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5)
#define SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT (6)
#define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5)
#define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT (6)
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_6~GPIO_NUM_21)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x00000000003FFFC0ULL
components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
+3 -3
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@@ -563,7 +563,7 @@ config SOC_GPIO_SUPPORT_ETM
bool
default y
config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
config SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
bool
default y
@@ -579,11 +579,11 @@ config SOC_GPIO_OUT_RANGE_MAX
int
default 28
config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK
int
default 0
config SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT
config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT
int
default 7
components/soc/esp32c5/include/soc/soc_caps.h
+5 -4
View File
@@ -221,8 +221,9 @@
#define SOC_GPIO_SUPPORT_ETM 1
// Target has the full LP IO subsystem
// GPIO0~7 on ESP32C5 can support chip deep sleep wakeup
#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1)
// GPIO0~7 on ESP32C5 can support chip HP peripheral powerdown-ed sleep wakeup
#define SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP (1)
#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
// LP IO peripherals have independent clock gating to manage
#define SOC_LP_IO_CLOCK_IS_INDEPENDENT (1)
@@ -232,8 +233,8 @@
#define SOC_GPIO_IN_RANGE_MAX 28
#define SOC_GPIO_OUT_RANGE_MAX 28
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6)
#define SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT (7)
#define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6)
#define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT (7)
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_7~GPIO_NUM_28)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x0000000001FFFF80ULL
components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
+3 -3
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@@ -479,7 +479,7 @@ config SOC_GPIO_SUPPORT_ETM
bool
default y
config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
config SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
bool
default y
@@ -495,11 +495,11 @@ config SOC_GPIO_OUT_RANGE_MAX
int
default 30
config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK
int
default 0
config SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT
config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT
int
default 8
components/soc/esp32c6/include/soc/soc_caps.h
+5 -4
View File
@@ -195,8 +195,9 @@
#define SOC_GPIO_SUPPORT_ETM 1
// Target has the full LP IO subsystem
// GPIO0~7 on ESP32C6 can support chip deep sleep wakeup
#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1)
// GPIO0~7 on ESP32C6 can support chip HP peripheral powerdown-ed sleep wakeup
#define SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP (1)
#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
// LP IO peripherals have independent clock gating to manage
#define SOC_LP_IO_CLOCK_IS_INDEPENDENT (1)
@@ -206,8 +207,8 @@
#define SOC_GPIO_IN_RANGE_MAX 30
#define SOC_GPIO_OUT_RANGE_MAX 30
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7)
#define SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT (8)
#define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7)
#define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT (8)
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_8~GPIO_NUM_30)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x000000007FFFFF00ULL
components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
+3 -3
View File
@@ -447,15 +447,15 @@ config SOC_GPIO_OUT_RANGE_MAX
int
default 29
config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
config SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
bool
default y
config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK
int
default 0
config SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT
config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT
int
default 7
components/soc/esp32c61/include/soc/soc_caps.h
+5 -4
View File
@@ -188,10 +188,11 @@
#define SOC_GPIO_IN_RANGE_MAX 29
#define SOC_GPIO_OUT_RANGE_MAX 29
// GPIO0~6 on ESP32C61 can support chip deep sleep wakeup
#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1)
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6)
#define SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT (7)
// GPIO0~6 on ESP32C61 can support chip HP peripheral powerdown-ed sleep wakeup
#define SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP (1)
#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
#define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6)
#define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT (7)
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_7~GPIO_NUM_29)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x3FFFFF80ULL
components/soc/esp32h2/include/soc/soc_caps.h
+1 -1
View File
@@ -224,7 +224,7 @@
// LP IO peripherals have independent clock gating to manage
#define SOC_LP_IO_CLOCK_IS_INDEPENDENT (1)
// GPIO7~14 on ESP32H2 can support chip deep sleep wakeup through EXT1 wake up
// GPIO7~14 on ESP32H2 can support chip HP peripheral powerdown-ed sleep wakeup through EXT1 wake up
#define SOC_GPIO_VALID_GPIO_MASK ((1U << SOC_GPIO_PIN_COUNT) - 1)
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
+3 -3
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@@ -347,15 +347,15 @@ config SOC_LP_IO_CLOCK_IS_INDEPENDENT
bool
default y
config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
config SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
bool
default y
config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK
int
default 0
config SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT
config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT
int
default 6
components/soc/esp32h4/include/soc/soc_caps.h
+4 -3
View File
@@ -221,9 +221,10 @@
// LP IO peripherals have independent clock gating to manage
#define SOC_LP_IO_CLOCK_IS_INDEPENDENT (1)
#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP 1
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5)
#define SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT (6)
#define SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP (1)
#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
#define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5)
#define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT (6)
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_6~GPIO_NUM_39)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK (SOC_GPIO_VALID_GPIO_MASK & ~((1ULL<<6) - 1))
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
+3 -3
View File
@@ -679,7 +679,7 @@ config SOC_GPIO_SUPPORT_ETM
bool
default y
config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
config SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
bool
default y
@@ -703,11 +703,11 @@ config SOC_GPIO_OUT_RANGE_MAX
int
default 54
config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK
int
default 0
config SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT
config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT
int
default 16
components/soc/esp32p4/include/soc/soc_caps.h
+5 -4
View File
@@ -254,8 +254,9 @@
// Target has the full LP IO subsystem
// GPIO0~15 on ESP32P4 can support chip deep sleep wakeup
#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1)
#define SOC_LP_IO_HAS_INDEPENDENT_WAKEUP_SOURCE (1)
#define SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP (1)
#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
#define SOC_LP_IO_HAS_INDEPENDENT_WAKEUP_SOURCE (1)
// LP IO peripherals have independent clock gating to manage
#define SOC_LP_IO_CLOCK_IS_INDEPENDENT (1)
@@ -266,8 +267,8 @@
#define SOC_GPIO_IN_RANGE_MAX 54
#define SOC_GPIO_OUT_RANGE_MAX 54
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | 0xFFFF)
#define SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT (16)
#define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK (0ULL | 0xFFFF)
#define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT (16)
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_16~GPIO_NUM_54)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x007FFFFFFFFF0000ULL