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Merge branch 'feat/usb_host_pwr_clk_gating_ll_backport_5.5' into 'release/v5.5'

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feat(usb_host): Add power and clock gating LL, HAL backport 5.5

See merge request espressif/esp-idf!42983
This commit is contained in:
morris
2025-11-27 11:15:47 +08:00
parent 1d5fcc6d2e a032b61bd0
commit d0f6d3699f
4 changed files with 129 additions and 0 deletions
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components/hal/esp32s2/include/hal/usb_dwc_ll.h
+27
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@@ -8,6 +8,7 @@
#include <stdint.h>
#include <stdbool.h>
#include "esp_attr.h"
#include "soc/usb_dwc_struct.h"
#include "soc/usb_dwc_cfg.h"
#include "hal/usb_dwc_types.h"
@@ -976,6 +977,32 @@ static inline void usb_dwc_ll_qtd_get_status(usb_dwc_ll_dma_qtd_t *qtd, int *rem
qtd->buffer_status_val = 0;
}
// ---------------------------- Power and Clock Gating Register --------------------------------
FORCE_INLINE_ATTR void usb_dwc_ll_set_stoppclk(usb_dwc_dev_t *hw, bool stop)
{
hw->pcgcctl_reg.stoppclk = stop;
}
FORCE_INLINE_ATTR bool usb_dwc_ll_get_stoppclk_st(usb_dwc_dev_t *hw)
{
return hw->pcgcctl_reg.stoppclk;
}
FORCE_INLINE_ATTR void usb_dwc_ll_set_gatehclk(usb_dwc_dev_t *hw, bool gate)
{
hw->pcgcctl_reg.gatehclk = gate;
}
FORCE_INLINE_ATTR bool usb_dwc_ll_get_gatehclk_st(usb_dwc_dev_t *hw)
{
return hw->pcgcctl_reg.gatehclk;
}
FORCE_INLINE_ATTR bool usb_dwc_ll_get_physleep_st(usb_dwc_dev_t *hw)
{
return hw->pcgcctl_reg.physleep;
}
#ifdef __cplusplus
}
#endif